This page has links to some documentaton resources available for Yosys.

Yosys Manual

A quick first-steps tutorial can be found in the README file.

The Yosys manual can be downloaded here (PDF).

The YosysHQ ReadTheDocs has links to many resources for Yosys and Yosys-based tools.


The best places to ask questions are the YosysHQ Community Slack and #yosys on Libera Chat. The best place to report a bug is on GitHub.

Presentation Slides

This presentation slides cover a wide range of topics related to Yosys. (The LaTeX source is part of the Yosys source distribution. Feel free to adapt the slides as needed.)

Application Notes

Papers and other Publications

Yosys is used in many academic projects. Below are a few papers from the authors of Yosys. If you would like to use Yosys in your research or teaching, but you need VHDL features not implemented in the open source frontend such as VHDL or SystemVerilog Assertion support, contact YosysHQ for an academic license!

  • C. Wolf, J. Glaser. Yosys - A Free Verilog Synthesis Suite. In Proceedings of Austrochip 2013. [download pdf]
  • J. Glaser and C. Wolf. Methodology and Example-Driven Interconnect Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable Architectures. In Jan Haase, editor, Models, Methods, and Tools for Complex Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp 201-221. Springer, 2013. [download pdf]
  • D. Shah, E. Hung, C. Wolf, S. Bazanski, D. Gisselquist, and M. Milanovic. Yosys + nextpnr: an Open Source Framework from Verilog to Bitstream for Commercial FPGAs. In 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2019. [arXiv]
In papers and reports, please refer to Yosys as follows: Claire Wolf. Yosys Open SYnthesis Suite., e.g. using the following BibTeX code:
	author = {Claire Wolf},
	title = {Yosys Open SYnthesis Suite},
	howpublished = "\url{}"

Command Reference