This page contains links to other projects.

Related Projects

These tools are built by members of the Yosys devteam.

  • Amaranth HDL -- A Python embedded DSL for hardware description that emits Yosys RTLIL
  • sby -- a front-end driver program for Yosys-based formal hardware verification flows
  • mcy -- Mutation Cover with Yosys
  • nextpnr -- A portable FPGA place and route tool
  • Project IceStorm -- Documenting the Lattice iCE40 FPGAs Bitstream format
  • Project Trellis -- Documenting the Lattice ECP5 Bitstream format
  • Project Oxide -- Documenting Lattice's 28nm FPGA parts

Online Services

  • EDA Playground -- Web Interface to many EDA tools, including Yosys
  • Blinklight -- A visual FPGA dev tool for simple designs

Free Verilog Simulators

Free Software for High-Level Circuit Synthesis and/or Analysis

  • Chisel -- Constructing Hardware in a Scala Embedded Language
  • PandA -- high-level synthesis of C based descriptions
  • CLaSH -- A compiler from Haskell to Verilog/VHDL
  • MyHDL -- an open source Python package that lets you go from Python to silicon
  • Migen -- a Python-based tool that aims at automating further the VLSI design process
  • LiteX -- Framework for rapidly assembling SoCs for use on FPGA
  • Cx -- A modern C-like language to create digital hardware

Free Software for Low-Level Circuit Synthesis and/or Analysis

  • ABC -- extensive tools for synthesis and verification of binary sequential logic
  • AIGER -- a format, library and set of utilities for And-Inverter Graphs
  • MiniSAT -- the SAT solver library used in Yosys
  • Torc -- infrastructure and tool set for mapping, placing, and routing
  • RapidSmith -- a research-based, open source FPGA CAD tool for modern Xilinx FPGAs
  • Open Circuit Design -- collection of open-source EDA tools, including Qflow
  • Coriolis2 -- an ASIC place and route flow
  • Workcraft -- a framework for interpreted graph models
  • netlistsvg -- SVG schematic from a Yosys JSON netlist
  • HAL -- The Hardware Analyzer

Verilog Tutorials