This should effectively be y=0, but verilator 1f56312 evaluates y=a instead.
module issue_041(a, y); input [2:0] a; output [3:0] y; assign y = (a >> 2'b11) >> 1; endmodule
Self-contained test case: test012.v, test012.cc, test012.sh
History:
2014-05-10 Reported as Issue #763
2014-05-11 Fixed in GIT commit 6ce2a52