The following module should set the output to constant 0, because the 4'b0 makes the whole expression unsigned.
module issue_032(y); wire signed [3:0] a = -5; wire signed [3:0] b = 0; output y; assign y = (1 ? a : 4'b0) < (1 ? b : b); initial #1 $display("%b", y); endmodule
But Icarus Verilog (git 3e41a93) assigns 1 instead. Interestingly the bug goes away if the (1 ? b : b) is replaced by b.
2014-03-06 Reported bug on GitHub
2014-03-06 Fixed in GIT commit bc9382e