read_verilog - read modules from Verilog file

    read_verilog [options] [filename]

Load modules from a Verilog file to the current design. A large subset of
Verilog-2005 is supported.

        enable support for SystemVerilog features. (only a small subset
        of SystemVerilog is supported)

        enable support for SystemVerilog assertions and some Yosys extensions
        replace the implicit -D SYNTHESIS with -D FORMAL

        don't add implicit -D SYNTHESIS

        ignore assert() statements

        ignore assume() statements

        ignore restrict() statements

        treat all assert() statements like assume() statements

        treat all assume() statements like assert() statements

        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug

        dump abstract syntax tree (before simplification)

        dump abstract syntax tree (after simplification)

        do not include hex memory addresses in dump (easier to diff dumps)

        dump ast as Verilog code (before simplification)

        dump ast as Verilog code (after simplification)

        dump generated RTLIL netlist

        enable parser debug output

        usually latches are synthesized into logic loops
        this option prohibits this and sets the output to 'x'
        in what would be the latches hold condition

        this behavior can also be achieved by setting the
        'nolatches' attribute on the respective module or
        always block.

        under certain conditions memories are converted to registers
        early during simplification to ensure correct handling of
        complex corner cases. this option disables this behavior.

        this can also be achieved by setting the 'nomem2reg'
        attribute on the respective module or register.

        This is potentially dangerous. Usually the front-end has good
        reasons for converting an array to a list of registers.
        Prohibiting this step will likely result in incorrect synthesis

        always convert memories to registers. this can also be
        achieved by setting the 'mem2reg' attribute on the respective
        module or register.

        do not infer $meminit cells and instead convert initialized
        memories to registers directly in the front-end.

        dump Verilog code after pre-processor

        do not run the pre-processor

        disable DPI-C support

        do not automatically add a (* blackbox *) attribute to an
        empty module.

        only create empty blackbox modules. This implies -DBLACKBOX.
        modules with the (* whitebox *) attribute will be preserved.
        (* lib_whitebox *) will be treated like (* whitebox *).

        delete (* whitebox *) and (* lib_whitebox *) attributes from
        all modules.

        parse and import specify blocks

        don't perform basic optimizations (such as const folding) in the
        high-level front-end.

        interpret cell types starting with '$' as internal cell types

        add a wire for each module parameter

        ignore re-definitions of modules. (the default behavior is to
        create an error message if the existing module is not a black box
        module, and overwrite the existing module otherwise.)

        overwrite existing modules with the same name

        only read the abstract syntax tree and defer actual compilation
        to a later 'hierarchy' command. Useful in cases where the default
        parameters of modules yield invalid or not synthesizable code.

        make the default of `default_nettype be "none" instead of "wire".

    -setattr <attribute_name>
        set the specified attribute (to the value 1) on all loaded modules

        define the preprocessor symbol 'name' and set its optional value

        add 'dir' to the directories which are used when searching include

The command 'verilog_defaults' can be used to register default options for
subsequent calls to 'read_verilog'.

Note that the Verilog frontend does a pretty good job of processing valid
verilog input, but has not very good error reporting. It generally is
recommended to use a simulator (for example Icarus Verilog) for checking
the syntax of the code, rather than to rely on read_verilog for that.

Depending on if read_verilog is run in -formal mode, either the macro
SYNTHESIS or FORMAL is defined automatically, unless -nosynthesis is used.
In addition, read_verilog always defines the macro YOSYS.

See the Yosys README file for a list of non-standard Verilog features
supported by the Yosys Verilog front-end.