check - check for obvious problems in the design

    check [options] [selection]

This pass identifies the following problems in the current design:

  - combinatorial loops
  - two or more conflicting drivers for one wire
  - used wires that do not have a driver


        also check for wires which have the 'init' attribute set

        also check for wires that have the 'init' attribute set and are not
        driven by an FF cell type

        also check for internal cells that have not been mapped to cells of the
        target architecture

        modify the -mapped behavior to still allow $_TBUF_ cells

        produce a runtime error if any problems are found in the current design