Another Verilotor bug with large shifts

For a=5, b=35 this should return y=0, but Verilator f705f9b returns y=8 instead:

module issue_051(a, b, y);
  input [3:0] a;
  input [5:0] b;
  output [3:0] y;
  assign y = 64'd0 | (a << b);
endmodule

Self-contained test case: test018.v, test018.cc, test018.sh

History:
2014-05-24 Reported as Issue #774
2014-09-25 Fixed in GIT commit e8edbad