Another Verilotor bug with large shifts

CLOSED: fixed in Verilator GIT e8edbad

For a=5, b=35 this should return y=0, but Verilator f705f9b returns y=8 instead:

module issue_051(a, b, y);
  input [3:0] a;
  input [5:0] b;
  output [3:0] y;
  assign y = 64'd0 | (a << b);

Self-contained test case: test018.v,,

2014-05-24 Reported as Issue #774
2014-09-25 Fixed in GIT commit e8edbad

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