Verilator returns incorrect expression result

This should return y=0 for a=31, but Verilator 06744b6 returns y=31 instead:

module issue_050(a, y);
  input [4:0] a;
  output [4:0] y;
  assign y = a >> ((a ? 1 : 2) << a);
endmodule

Self-contained test case: test017.v, test017.cc, test017.sh

History:
2014-05-23 Reported as Issue #773
2014-05-24 Fixed in GIT commit f705f9b