Verilator bug in sign extending special boolean expression

CLOSED: fixed in Verilator GIT 06744b6

This should set y=4'b1111 but Verilator d7e4bc1 sets y=4'b0001 instead.

module issue_046(a, y);
  input signed [3:0] a;
  output [3:0] y;
  assign y = $signed(5'd1 > a-a);

Only slight modifications in the expression make the problem disappear.

Self-contained test case: test015.v,,

2014-05-15 Reported as Issue #768
2014-05-16 Fixed in GIT commit 06744b6

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