Yet another Verilator shift bug

CLOSED: fixed in Verilator GIT 6ce2a52

This should effectively be y=0, but verilator 1f56312 evaluates y=a instead.

module issue_041(a, y);
  input [2:0] a;
  output [3:0] y;
  assign y = (a >> 2'b11) >> 1;

Self-contained test case: test012.v,,

2014-05-10 Reported as Issue #763
2014-05-11 Fixed in GIT commit 6ce2a52

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