The following module should set the output to constant 4'bxxxx:
module test(y); output [3:0] y; assign y = 4'b0 * 4'bx; endmodule
But Icarus Verilog (git a3450bf) is too smart and outputs 4'b0000 instead.
History:
2014-02-27 Reported bug on GitHub
2014-02-25 Fixed in GIT commit ed2e339