Icarus Verilog bug in processing "1'b1 >= |1'bx"

The following module should set y to 1'bx. But Icarus Verilog (git b1ef099) sets the output to 1'b1.

module issue_024(y);
  output y;
  assign y = 1'b1 >= |1'bx;
endmodule

History:
2014-02-17 Reported bug on GitHub
2014-02-16 Fixed in GIT commit 5a06602