Icarus Verilog undef propagation bug in power operator

icarus verilog (git d1c9dd5) does not correctly propagate undef through the power operator. For example, y should be 4'bx when a is zero in the following test case, but iverilog returns 4'd1:

module issue_012(a, y);
  input [3:0] a;
  output [3:0] y;
  assign y = 4'd2 ** (4'd1/a);
endmodule

History:
2014-01-06 Reported bug on GitHub
2014-02-15 Fixed in GIT commit 68f8de2