Verilator bug with shift, expression width and signedness

CLOSED: fixed in Verilator GIT b631b59

Verilator adb39ce seems to have troubles with the following expressions. It seems to correctly interpret -2'sd1 as the value 3, but then has problems identifying the correct bit width for the expression and sign extends it even though the result of << should be unsigned.

module issue_003(a, y);
  input signed [3:0] a;
  output [4:0] y;
  assign y = a << -2'sd1;

Crosscheck: Vivado 2013.4, XST 14.7, Xsim 2013.4 and Modelsim 10.1d implement this correctly.

Self-contained test case: test007.v,,

Verilog testbench for comparison: test007_tb.v

2014-04-30 Reported as Issue #754
2014-04-30 Fixed in GIT commit b631b59

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