VlogHammer Report

Report on expression_00000:

This report is part of the following lists: all quartus xst

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	PASS	6b2a1add	6b2a1add	6b2a1add	6b2a1add
quartus	FAIL	PASS	PASS	FAIL	6b3f25a6	6b3f25a6	6b3f25a6	6b3f25a6
xst	FAIL	PASS	PASS	FAIL	6b3f25a6	6b3f25a6	6b3f25a6	6b3f25a6
yosys	PASS	FAIL	FAIL	PASS	6b2a1add	6b2a1add	6b2a1add	6b2a1add
rtl	PASS	FAIL	FAIL	PASS	6b2a1add	6b2a1add	6b2a1add	6b2a1add

module expression_00000(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  input [3:0] a0;
  input [4:0] a1;
  input [5:0] a2;
  input signed [3:0] a3;
  input signed [4:0] a4;
  input signed [5:0] a5;

  input [3:0] b0;
  input [4:0] b1;
  input [5:0] b2;
  input signed [3:0] b3;
  input signed [4:0] b4;
  input signed [5:0] b5;

  wire [3:0] y0;
  wire [4:0] y1;
  wire [5:0] y2;
  wire signed [3:0] y3;
  wire signed [4:0] y4;
  wire signed [5:0] y5;
  wire [3:0] y6;
  wire [4:0] y7;
  wire [5:0] y8;
  wire signed [3:0] y9;
  wire signed [4:0] y10;
  wire signed [5:0] y11;
  wire [3:0] y12;
  wire [4:0] y13;
  wire [5:0] y14;
  wire signed [3:0] y15;
  wire signed [4:0] y16;
  wire signed [5:0] y17;

  output [89:0] y;
  assign y = {y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17};

  localparam [3:0] p0 = ((-3'sd2)^(-4'sd6));
  localparam [4:0] p1 = (((-5'sd3)?(2'd1):(5'd14))?((2'd0)?(4'sd5):(2'd2)):((-5'sd1)?(5'sd15):(3'd2)));
  localparam [5:0] p2 = (5'sd11);
  localparam signed [3:0] p3 = ((-5'sd2)?((3'd7)?(2'd0):(4'sd0)):((4'd15)?(3'd6):(-4'sd0)));
  localparam signed [4:0] p4 = (&((&((4'sd4)<<(5'd14)))%(4'd13)));
  localparam signed [5:0] p5 = ((!{1{(3'd4)}})?((2'sd0)?(-4'sd5):(3'd0)):(|(^(4'sd6))));
  localparam [3:0] p6 = {(((6'd2 ** (5'd30))===((4'sd4)<=(-5'sd13)))!={(~|(3'sd0)),{(5'sd0),(5'd29)},{(-2'sd1)}})};
  localparam [4:0] p7 = ({1{({2{(-5'sd1)}}^~{1{(5'd31)}})}}<{1{(((2'd1)-(3'sd1))==((4'sd0)&(-5'sd12)))}});
  localparam [5:0] p8 = ((((3'd5)^~(3'd0))?(5'sd13):((5'd12)?(-3'sd3):(-5'sd11)))&&(-3'sd2));
  localparam signed [3:0] p9 = {{(2'sd0),(-5'sd15),(-4'sd5)}};
  localparam signed [4:0] p10 = (^(2'd1));
  localparam signed [5:0] p11 = (~^(~|(&(~&(2'd3)))));
  localparam [3:0] p12 = ((5'sd10)?(3'd4):(-4'sd2));
  localparam [4:0] p13 = (4'd10);
  localparam [5:0] p14 = {{4{(-3'sd3)}},{2{(5'sd11)}},((-2'sd0)===(5'sd10))};
  localparam signed [3:0] p15 = (5'sd11);
  localparam signed [4:0] p16 = {((~^((3'd2)>=(5'sd13)))!=(~|((4'd3)===(3'd1))))};
  localparam signed [5:0] p17 = ({1{{4{(-4'sd4)}}}}>({1{{2{(2'd0)}}}}>((5'd25)<=(-4'sd7))));

  assign y0 = (~|p16);
  assign y1 = {3{(~b2)}};
  assign y2 = ($signed(((a4!==a0)-(p9^p16))));
  assign y3 = (~&(|((4'd8)?(2'sd0):(+a3))));
  assign y4 = {(^{{(-({p15}^~{p1})),((p17!=p13)<<(p1^p2)),{(~(p7||p10))}}})};
  assign y5 = (({(b4?a3:a2),(a3?b5:p16)}<<({a4}?{a5,a0,p4}:{p11,b5}))<<((b1?b2:a2)?(b0-b2):(+{a4,p11})));
  assign y6 = {(b1&a4),(-2'sd1)};
  assign y7 = ({1{b0}}>>>{4{p2}});
  assign y8 = (((-{3{p2}})>(p13+p4))?$unsigned((~^(p0?p0:a1))):({2{a3}}^(&(~&p11))));
  assign y9 = (-a2);
  assign y10 = (((a4^p4)?(b2!==b2):(p11?b5:p13))|((b3===a5)^~(p5&&p16)));
  assign y11 = (^$unsigned({($signed(b0)),(!(+p11))}));
  assign y12 = (2'd3);
  assign y13 = (-2'sd0);
  assign y14 = ($signed(((p14||p2)&{3{p5}}))?(((p14-p14))>=(p7?p14:p14)):((p5<p12)^(p15?p11:p12)));
  assign y15 = (~|((p13||p16)<<<{p10,p2}));
  assign y16 = ((~$signed((^p17)))?((p7)|$signed(p1)):$signed((a5===a2)));
  assign y17 = (~&{2{{({b5}>>>(b5<=b5)),{a0,p12,b1}}}});
endmodule

module expression_00000_tb;
  reg [3:0] a0;
  reg [4:0] a1;
  reg [5:0] a2;
  reg signed [3:0] a3;
  reg signed [4:0] a4;
  reg signed [5:0] a5;
  reg [3:0] b0;
  reg [4:0] b1;
  reg [5:0] b2;
  reg signed [3:0] b3;
  reg signed [4:0] b4;
  reg signed [5:0] b5;
  wire [89:0] y;
  expression_00000 uut (a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  task test_pattern;
    input [5:0] index;
    input [59:0] pattern;
    begin
      { a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5 } <= pattern; #1;
      $display("++RPT++ %d %b %b %b %b %b %b %b %b %b %b %b %b %b", index,
                    a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
    end
  endtask
  initial begin
    test_pattern(  0, 60'b0 );
    test_pattern(  1, ~60'b0 );
    test_pattern(  2, 60'b000000000000000000000000000000111100000111111000100000000000 );
    test_pattern(  3, 60'b010000000110101101100111110101111010000000000100000000000001 );
    test_pattern(  4, 60'b011100000011101010100111011101100010110001000110100000111001 );
    test_pattern(  5, 60'b100000000111000000111011111000100010000000100110000000001111 );
    test_pattern(  6, 60'b110000000001100000000001001100000000001111111001110000111111 );
    test_pattern(  7, 60'b111100000111101000000000111101101110101111111111000000111110 );
    test_pattern(  8, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern(  9, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 10, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 11, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 12, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 13, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 14, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 15, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 16, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 17, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 18, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 19, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 20, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 21, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 22, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 23, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 24, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 25, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 26, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 27, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 28, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 29, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 30, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 31, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 32, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 33, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 34, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 35, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 36, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
    test_pattern( 37, 160'h23ab9f2b8ac73d7a007955f3419bec57f0fe178a );
  end
endmodule

Pattern #0		binary	decimal
input signals	a0	0000	0
	a1	00000	0
	a2	000000	0
	a3	0000	0
	a4	00000	0
	a5	000000	0
	b0	0000	0
	b1	00000	0
	b2	000000	0
	b3	0000	0
	b4	00000	0
	b5	000000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #1		binary	decimal
input signals	a0	1111	15
	a1	11111	31
	a2	111111	63
	a3	1111	-1
	a4	11111	-1
	a5	111111	-1
	b0	1111	15
	b1	11111	31
	b2	111111	63
	b3	1111	-1
	b4	11111	-1
	b5	111111	-1
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #2		binary	decimal
input signals	a0	0000	0
	a1	00000	0
	a2	000000	0
	a3	0000	0
	a4	00000	0
	a5	000000	0
	b0	1111	15
	b1	00000	0
	b2	111111	63
	b3	0001	1
	b4	00000	0
	b5	000000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #3		binary	decimal
input signals	a0	0100	4
	a1	00000	0
	a2	110101	53
	a3	1011	-5
	a4	00111	7
	a5	110101	-11
	b0	1110	14
	b1	10000	16
	b2	000000	0
	b3	1000	-8
	b4	00000	0
	b5	000001	1
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #4		binary	decimal
input signals	a0	0111	7
	a1	00000	0
	a2	011101	29
	a3	0101	5
	a4	00111	7
	a5	011101	29
	b0	1000	8
	b1	10110	22
	b2	001000	8
	b3	1101	-3
	b4	00000	0
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #5		binary	decimal
input signals	a0	1000	8
	a1	00000	0
	a2	111000	56
	a3	0001	1
	a4	11011	-5
	a5	111000	-8
	b0	1000	8
	b1	10000	16
	b2	000100	4
	b3	1100	-4
	b4	00000	0
	b5	001111	15
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #6		binary	decimal
input signals	a0	1100	12
	a1	00000	0
	a2	001100	12
	a3	0000	0
	a4	00001	1
	a5	001100	12
	b0	0000	0
	b1	00001	1
	b2	111111	63
	b3	0011	3
	b4	10000	-16
	b5	111111	-1
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #7		binary	decimal
input signals	a0	1111	15
	a1	00000	0
	a2	111101	61
	a3	0000	0
	a4	00000	0
	a5	111101	-3
	b0	1011	11
	b1	10101	21
	b2	111111	63
	b3	1110	-2
	b4	00000	0
	b5	111110	-2
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #8		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #9		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #10		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #11		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #12		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #13		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #14		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #15		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #16		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #17		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #18		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #19		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #20		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #21		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #22		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #23		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #24		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #25		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #26		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #27		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #28		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #29		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #30		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #31		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #32		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #33		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #34		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #35		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #36		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Pattern #37		binary	decimal
input signals	a0	0001	1
	a1	10011	19
	a2	011111	31
	a3	0110	6
	a4	00101	5
	a5	011111	31
	b0	1100	12
	b1	00111	7
	b2	111100	60
	b3	0010	2
	b4	11110	-2
	b5	001010	10
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11111	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	00001	1

Report on expression_00001:

This report is part of the following lists: all quartus xst

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	PASS	99e292a8	99e292a8	99e292a8	99e292a8
quartus	FAIL	PASS	FAIL	FAIL	b66c2422	b66c2422	b66c2422	b66c2422
xst	FAIL	FAIL	PASS	FAIL	bf226509	bf226509	bf226509	bf226509
yosys	PASS	FAIL	FAIL	PASS	99e292a8	99e292a8	99e292a8	99e292a8
rtl	PASS	FAIL	FAIL	PASS	99e292a8	99e292a8	99e292a8	99e292a8

module expression_00001(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  input [3:0] a0;
  input [4:0] a1;
  input [5:0] a2;
  input signed [3:0] a3;
  input signed [4:0] a4;
  input signed [5:0] a5;

  input [3:0] b0;
  input [4:0] b1;
  input [5:0] b2;
  input signed [3:0] b3;
  input signed [4:0] b4;
  input signed [5:0] b5;

  wire [3:0] y0;
  wire [4:0] y1;
  wire [5:0] y2;
  wire signed [3:0] y3;
  wire signed [4:0] y4;
  wire signed [5:0] y5;
  wire [3:0] y6;
  wire [4:0] y7;
  wire [5:0] y8;
  wire signed [3:0] y9;
  wire signed [4:0] y10;
  wire signed [5:0] y11;
  wire [3:0] y12;
  wire [4:0] y13;
  wire [5:0] y14;
  wire signed [3:0] y15;
  wire signed [4:0] y16;
  wire signed [5:0] y17;

  output [89:0] y;
  assign y = {y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17};

  localparam [3:0] p0 = (-3'sd3);
  localparam [4:0] p1 = {((-5'sd11)<=(-4'sd3))};
  localparam [5:0] p2 = {{((-2'sd0)?(-3'sd1):(5'd19)),{(4'd9),(3'sd3),(3'd3)},{(5'd13),(4'd12),(-2'sd0)}}};
  localparam signed [3:0] p3 = {1{{4{(5'sd13)}}}};
  localparam signed [4:0] p4 = ((~|((-3'sd2)<=(4'sd3)))-((2'd1)?(-5'sd4):(2'd0)));
  localparam signed [5:0] p5 = ((5'd0)&&(-2'sd0));
  localparam [3:0] p6 = {3{((4'd2 ** (2'd3))!=((4'd5)?(2'd1):(5'sd9)))}};
  localparam [4:0] p7 = ({((2'd1)?(-3'sd3):(-4'sd0)),((3'd3)^(-3'sd1)),{(2'd1),(3'd5),(4'sd0)}}?(((4'sd0)?(5'd28):(2'd2))
    !=((2'sd0)?(-2'sd1):(2'd3))):(3'sd1));
  localparam [5:0] p8 = (-3'sd0);
  localparam signed [3:0] p9 = {({(-3'sd2),(-2'sd1)}===((3'd6)<<(3'd7))),{{{(4'd0),(5'd29),(-4'sd1)},(-(-5'sd8))}}};
  localparam signed [4:0] p10 = (-(~&{3{((~|(4'sd3))||((4'sd2)<<<(2'd2)))}}));
  localparam signed [5:0] p11 = ((~^{(&(2'd3)),(~^(5'd17))})?{4{(2'd0)}}:(((4'sd1)>>(-3'sd0))?((3'd2)?(-4'sd0):(-5'sd0))
    :((2'sd0)?(3'd1):(5'd20))));
  localparam [3:0] p12 = (((5'd10)^~(-4'sd7))<<{2{(5'd4)}});
  localparam [4:0] p13 = (-3'sd2);
  localparam [5:0] p14 = (^(~(~(!((((3'd4)<(4'd15))<(+(2'sd0)))&&(!((!(2'd3))^((4'd3)>>(3'd1)))))))));
  localparam signed [3:0] p15 = (!(4'sd6));
  localparam signed [4:0] p16 = {((5'sd7)?((4'd7)-(-3'sd3)):{(4'sd3)})};
  localparam signed [5:0] p17 = ((-2'sd0)>(5'd10));

  assign y0 = $signed((((a0^~p15)?(b2):$unsigned(b3))^~$signed($unsigned($unsigned((6'd2 ** p14))))));
  assign y1 = {3{(~p7)}};
  assign y2 = ({(&(p13^~p9)),(~(p6>p13))}?((a4?p15:p10)?(p2^p11):{p14}):(({p5,p16}-(b1<=p13))));
  assign y3 = {({(((a5)^~(b1?a4:a4))?((p8||p17)>>{a2,a4,b4}):{(b3?a4:a5),{a3,p12,p10},{p8,p15,a3}})})};
  assign y4 = ((~^(a1^~b1))!=((~|a5)||(p3^p12)));
  assign y5 = (((5'd10)>>(-2'sd0))!=({1{(-2'sd1)}}<<<{1{(-5'sd3)}}));
  assign y6 = (!(&{4{(p3?p6:p14)}}));
  assign y7 = {1{{{2{(2'd2)}},{2{(+p8)}},(3'sd1)}}};
  assign y8 = (4'd14);
  assign y9 = $signed(((+$signed((^(6'd2 ** a2))))<$unsigned($unsigned(((+a3))))));
  assign y10 = (-((+((+{2{(~^p13)}})))^~(!{{b5,b1,a0},(a1&p12),(a4+a3)})));
  assign y11 = (~&(-{(-3'sd3),($unsigned($signed($unsigned({p0,b4,b1})))),{(!{p1}),(~&{p6})}}));
  assign y12 = (-2'sd0);
  assign y13 = (~&{2{((a2?a5:b0)===(&b0))}});
  assign y14 = ((-((~(b3))?{2{b2}}:{2{b5}}))<(~&{1{((5'd14)?(~|(a2>>>a1)):(b4?b3:a2))}}));
  assign y15 = (|{{{p2,p0},{b2}},((p11>p5))});
  assign y16 = (+({3{b0}}?{1{(&b1)}}:{1{(p14?p3:p1)}}));
  assign y17 = (+{({b0,b4,b3}),((-4'sd0)||{b4,a1}),(^$unsigned((~^(~&a2))))});
endmodule

module expression_00001_tb;
  reg [3:0] a0;
  reg [4:0] a1;
  reg [5:0] a2;
  reg signed [3:0] a3;
  reg signed [4:0] a4;
  reg signed [5:0] a5;
  reg [3:0] b0;
  reg [4:0] b1;
  reg [5:0] b2;
  reg signed [3:0] b3;
  reg signed [4:0] b4;
  reg signed [5:0] b5;
  wire [89:0] y;
  expression_00001 uut (a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  task test_pattern;
    input [5:0] index;
    input [59:0] pattern;
    begin
      { a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5 } <= pattern; #1;
      $display("++RPT++ %d %b %b %b %b %b %b %b %b %b %b %b %b %b", index,
                    a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
    end
  endtask
  initial begin
    test_pattern(  0, 60'b0 );
    test_pattern(  1, ~60'b0 );
    test_pattern(  2, 60'b011111111010011101010010110101000000011101111111110011100101 );
    test_pattern(  3, 60'b100110011110111101000010110101000011000000000010000000000111 );
    test_pattern(  4, 60'b100111111110111010111101000010000000000000000000110000000010 );
    test_pattern(  5, 60'b110111111000101111111001111111000011111000010011011000011011 );
    test_pattern(  6, 60'b111100000000000111110111001111000110111000000001100001111111 );
    test_pattern(  7, 60'b111110000000100101010001000001111100000000000001000001000110 );
    test_pattern(  8, 60'b111111101000100000111010000111000000000110111101010000110011 );
    test_pattern(  9, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 10, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 11, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 12, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 13, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 14, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 15, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 16, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 17, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 18, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 19, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 20, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 21, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 22, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 23, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 24, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 25, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 26, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 27, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 28, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 29, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 30, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 31, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 32, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 33, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 34, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 35, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 36, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 37, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
    test_pattern( 38, 160'h80ef47d32857725f4fd3fea28dca11f49c94cf3c );
  end
endmodule

Pattern #0		binary	decimal
input signals	a0	0000	0
	a1	00000	0
	a2	000000	0
	a3	0000	0
	a4	00000	0
	a5	000000	0
	b0	0000	0
	b1	00000	0
	b2	000000	0
	b3	0000	0
	b4	00000	0
	b5	000000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11101	-3
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	01101	13

Pattern #2		binary	decimal
input signals	a0	0111	7
	a1	11111	31
	a2	010011	19
	a3	1010	-6
	a4	10010	-14
	a5	110101	-11
	b0	0000	0
	b1	00011	3
	b2	101111	47
	b3	1111	-1
	b4	10011	-13
	b5	100101	-27
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11101	-3
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	01101	13

Pattern #3		binary	decimal
input signals	a0	1001	9
	a1	10011	19
	a2	110111	55
	a3	1010	-6
	a4	00010	2
	a5	110101	-11
	b0	0000	0
	b1	11000	24
	b2	000000	0
	b3	0100	4
	b4	00000	0
	b5	000111	7
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11101	-3
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	01101	13

Pattern #4		binary	decimal
input signals	a0	1001	9
	a1	11111	31
	a2	110111	55
	a3	0101	5
	a4	11101	-3
	a5	000010	2
	b0	0000	0
	b1	00000	0
	b2	000000	0
	b3	0001	1
	b4	10000	-16
	b5	000010	2
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11101	-3
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	01101	13

Pattern #5		binary	decimal
input signals	a0	1101	13
	a1	11111	31
	a2	000101	5
	a3	1111	-1
	a4	11001	-7
	a5	111111	-1
	b0	0000	0
	b1	11111	31
	b2	000010	2
	b3	0110	6
	b4	11000	-8
	b5	011011	27
{icarus,modelsim,xsim,yosim}.quartus	y9	0000	0
{icarus,modelsim,xsim,yosim}.quartus	y16	11101	-3
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y9	1111	-1
	y16	01101	13
{icarus,modelsim,xsim,yosim}.xst	y9	1111	-1
{icarus,modelsim,xsim,yosim}.xst	y16	11101	-3

Pattern #6		binary	decimal
input signals	a0	1111	15
	a1	00000	0
	a2	000000	0
	a3	1111	-1
	a4	10111	-9
	a5	001111	15
	b0	0001	1
	b1	10111	23
	b2	000000	0
	b3	0011	3
	b4	00001	1
	b5	111111	-1
{icarus,modelsim,xsim,yosim}.quartus	y9	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y9	1111	-1

Pattern #7		binary	decimal
input signals	a0	1111	15
	a1	10000	16
	a2	000100	4
	a3	1010	-6
	a4	10001	-15
	a5	000001	1
	b0	1111	15
	b1	00000	0
	b2	000000	0
	b3	0010	2
	b4	00001	1
	b5	000110	6
{icarus,modelsim,xsim,yosim}.quartus	y9	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y9	1111	-1

Pattern #8		binary	decimal
input signals	a0	1111	15
	a1	11101	29
	a2	000100	4
	a3	0001	1
	a4	11010	-6
	a5	000111	7
	b0	0000	0
	b1	00000	0
	b2	110111	55
	b3	1010	-6
	b4	10000	-16
	b5	110011	-13
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y16	11101	-3
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y16	01101	13

Report on expression_00002:

This report is part of the following lists: all noerror

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	PASS	FAIL	996bd2de	996bd2de	996bd2de	996bd2de
quartus	FAIL	PASS	FAIL	FAIL	996bd2de	996bd2de	996bd2de	996bd2de
xst	PASS	FAIL	PASS	FAIL	996bd2de	996bd2de	996bd2de	996bd2de
yosys	FAIL	FAIL	FAIL	PASS	996bd2de	996bd2de	996bd2de	996bd2de
rtl	PASS	PASS	PASS	PASS	996bd2de	996bd2de	996bd2de	996bd2de

module expression_00002(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  input [3:0] a0;
  input [4:0] a1;
  input [5:0] a2;
  input signed [3:0] a3;
  input signed [4:0] a4;
  input signed [5:0] a5;

  input [3:0] b0;
  input [4:0] b1;
  input [5:0] b2;
  input signed [3:0] b3;
  input signed [4:0] b4;
  input signed [5:0] b5;

  wire [3:0] y0;
  wire [4:0] y1;
  wire [5:0] y2;
  wire signed [3:0] y3;
  wire signed [4:0] y4;
  wire signed [5:0] y5;
  wire [3:0] y6;
  wire [4:0] y7;
  wire [5:0] y8;
  wire signed [3:0] y9;
  wire signed [4:0] y10;
  wire signed [5:0] y11;
  wire [3:0] y12;
  wire [4:0] y13;
  wire [5:0] y14;
  wire signed [3:0] y15;
  wire signed [4:0] y16;
  wire signed [5:0] y17;

  output [89:0] y;
  assign y = {y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17};

  localparam [3:0] p0 = ((&((-2'sd0)&(-4'sd4)))>>>({(2'd3)}&((2'd3)||(-4'sd1))));
  localparam [4:0] p1 = (~{4{(5'sd15)}});
  localparam [5:0] p2 = (&{3{{((5'd26)==(3'd0)),(4'd6),(~^(3'd3))}}});
  localparam signed [3:0] p3 = (4'd2);
  localparam signed [4:0] p4 = (+(3'sd3));
  localparam signed [5:0] p5 = (~^(((2'd0)^~(4'd2))^(|(|(2'sd1)))));
  localparam [3:0] p6 = (2'd2);
  localparam [4:0] p7 = ({((-2'sd1)==(5'sd7))}-{(2'sd1),(5'sd3)});
  localparam [5:0] p8 = (-(5'd18));
  localparam signed [3:0] p9 = ((6'd2 ** (4'd3))<((2'sd1)^~(3'sd1)));
  localparam signed [4:0] p10 = ((((5'd7)+(-5'sd14))-((-5'sd13)+(3'd4)))|(((-4'sd2)?(-4'sd6):(4'sd6))===((-5'sd14)-(5'sd0)
    )));
  localparam signed [5:0] p11 = (((-3'sd0)?(-5'sd12):(5'd3))!=((4'd6)?(-4'sd5):(5'sd15)));
  localparam [3:0] p12 = (!{1{(4'd0)}});
  localparam [4:0] p13 = {({1{((5'd25)<(4'd11))}}?(((4'sd5)?(5'd2):(-5'sd9))>>>{(3'sd0),(-2'sd1),(5'sd3)}):{4{(-4'sd1)}})
    };
  localparam [5:0] p14 = ({2{{((3'sd1)==(4'd11))}}}^~({3{(3'd4)}}<((-4'sd0)<=(-2'sd0))));
  localparam signed [3:0] p15 = ({(4'd2),(-3'sd2),(2'd0)}?(!(3'd4)):((2'd0)?(-3'sd0):(3'd7)));
  localparam signed [4:0] p16 = ({((-2'sd0)<(-4'sd0)),(-(4'sd4)),((2'sd1)^(-4'sd5))}<{(~&(-5'sd12)),{(3'd2),(2'd3),(3'd0)
    }});
  localparam signed [5:0] p17 = (4'd6);

  assign y0 = (~&(!(!(~|(!(-{(|a2),{a4,b5}}))))));
  assign y1 = (a4&&a4);
  assign y2 = ((4'd8)>>>($unsigned(((b5==b4)/b2))!=($unsigned((b0!==b0))/a5)));
  assign y3 = ((p15?a1:a1)?(p17?b3:p9):(p17?p7:p16));
  assign y4 = ((p5?b5:b0)?{a3}:(p1>>p15));
  assign y5 = (+(a0!==a0));
  assign y6 = {1{{2{b0}}}};
  assign y7 = (((5'd11)===(&(b0<<<a3)))^{4{(p16?a2:a0)}});
  assign y8 = ((((~&$signed((+a1)))!==$signed((^(+b5)))))!==(^(&(~^($signed((b1<a2))>>(b0<<b0))))));
  assign y9 = (3'sd3);
  assign y10 = ((~^(^(a2<<a3)))-((b0<<a4)/b1));
  assign y11 = (5'd8);
  assign y12 = {p3,p7};
  assign y13 = (({4{b5}}===$unsigned(a0))^~({1{p17}}=={3{p11}}));
  assign y14 = (3'sd0);
  assign y15 = ((!{3{$unsigned((a1^b4))}})^{(4'd2 ** (2'd2)),((~^a5)<=(5'd4))});
  assign y16 = (+(|((-$signed((-5'sd11))))));
  assign y17 = (!{1{(((2'd0)&&(6'd2 ** p0))>>({4{a5}}!=(6'd2 ** b2)))}});
endmodule

module expression_00002_tb;
  reg [3:0] a0;
  reg [4:0] a1;
  reg [5:0] a2;
  reg signed [3:0] a3;
  reg signed [4:0] a4;
  reg signed [5:0] a5;
  reg [3:0] b0;
  reg [4:0] b1;
  reg [5:0] b2;
  reg signed [3:0] b3;
  reg signed [4:0] b4;
  reg signed [5:0] b5;
  wire [89:0] y;
  expression_00002 uut (a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  task test_pattern;
    input [5:0] index;
    input [59:0] pattern;
    begin
      { a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5 } <= pattern; #1;
      $display("++RPT++ %d %b %b %b %b %b %b %b %b %b %b %b %b %b", index,
                    a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
    end
  endtask
  initial begin
    test_pattern(  0, 60'b0 );
    test_pattern(  1, ~60'b0 );
    test_pattern(  2, 60'b000001110110001000011011000000110010000000001110011100111100 );
    test_pattern(  3, 60'b000011011000010000100010000000010100100100000001110001000100 );
    test_pattern(  4, 60'b000011101111101101100001000000101010110000000111111101111000 );
    test_pattern(  5, 60'b000011111110010001001010000000011001111011011000101110111000 );
    test_pattern(  6, 60'b000100000101101000001010000000000001000000001100101000001000 );
    test_pattern(  7, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern(  8, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern(  9, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 10, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 11, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 12, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 13, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 14, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 15, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 16, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 17, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 18, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 19, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 20, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 21, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 22, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 23, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 24, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 25, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 26, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 27, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 28, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 29, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 30, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 31, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 32, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 33, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 34, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 35, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
    test_pattern( 36, 160'hf89c00873ac97f5c07321170b5f4ba8f76d7fbf9 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a0	0000	0
	a1	00000	0
	a2	000000	0
	a3	0000	0
	a4	00000	0
	a5	000000	0
	b0	0000	0
	b1	00000	0
	b2	000000	0
	b3	0000	0
	b4	00000	0
	b5	000000	0
{icarus,modelsim,xsim,yosim}.quartus	y2	000100	4
{icarus,modelsim,xsim,yosim}.quartus	y10	00010	2
{icarus,modelsim,xsim,yosim}.rtl	y2	xxxxxx	X
{icarus,modelsim,xsim,yosim}.rtl	y10	xxxxx	X
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y2	001000	8
	y10	00010	2

Pattern #2		binary	decimal
input signals	a0	0000	0
	a1	01110	14
	a2	110001	49
	a3	0000	0
	a4	11011	-5
	a5	000000	0
	b0	1100	12
	b1	10000	16
	b2	000001	1
	b3	1100	-4
	b4	11100	-4
	b5	111100	-4
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys	y2	000100	4
{icarus,modelsim,xsim,yosim}.rtl	y2	xxxxxx	X
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.xst	y2	001000	8

Pattern #3		binary	decimal
input signals	a0	0000	0
	a1	11011	27
	a2	000010	2
	a3	0001	1
	a4	00010	2
	a5	000000	0
	b0	0101	5
	b1	00100	4
	b2	100000	32
	b3	0011	3
	b4	10001	-15
	b5	000100	4
{icarus,modelsim,xsim,yosim}.quartus	y2	001000	8
{icarus,modelsim,xsim,yosim}.rtl	y2	xxxxxx	X
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y2	000100	4

Pattern #4		binary	decimal
input signals	a0	0000	0
	a1	11101	29
	a2	111101	61
	a3	1011	-5
	a4	00001	1
	a5	000000	0
	b0	1010	10
	b1	10110	22
	b2	000000	0
	b3	1111	-1
	b4	11101	-3
	b5	111000	-8
{icarus,modelsim,xsim,yosim}.quartus	y2	000100	4
{icarus,modelsim,xsim,yosim}.rtl	y2	xxxxxx	X
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y2	001000	8

Pattern #5		binary	decimal
input signals	a0	0000	0
	a1	11111	31
	a2	110010	50
	a3	0010	2
	a4	01010	10
	a5	000000	0
	b0	0110	6
	b1	01111	15
	b2	011011	27
	b3	0001	1
	b4	01110	14
	b5	111000	-8
{icarus,modelsim,xsim,yosim}.quartus	y2	001000	8
{icarus,modelsim,xsim,yosim}.rtl	y2	xxxxxx	X
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y2	000100	4

Pattern #6		binary	decimal
input signals	a0	0001	1
	a1	00000	0
	a2	101101	45
	a3	0000	0
	a4	01010	10
	a5	000000	0
	b0	0000	0
	b1	01000	8
	b2	000001	1
	b3	1001	-7
	b4	01000	8
	b5	001000	8
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys	y2	000100	4
{icarus,modelsim,xsim,yosim}.rtl	y2	xxxxxx	X
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.xst	y2	001000	8

Report on expression_00003:

This report is part of the following lists: all quartus vivado

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	FAIL	5969d3c1	5969d3c1	5969d3c1	5969d3c1
quartus	FAIL	PASS	FAIL	FAIL	92d5d8de	92d5d8de	92d5d8de	92d5d8de
xst	FAIL	FAIL	PASS	PASS	177382dd	177382dd	177382dd	177382dd
yosys	FAIL	FAIL	PASS	PASS	177382dd	177382dd	177382dd	177382dd
rtl	FAIL	FAIL	PASS	PASS	177382dd	177382dd	177382dd	177382dd

module expression_00003(a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  input [3:0] a0;
  input [4:0] a1;
  input [5:0] a2;
  input signed [3:0] a3;
  input signed [4:0] a4;
  input signed [5:0] a5;

  input [3:0] b0;
  input [4:0] b1;
  input [5:0] b2;
  input signed [3:0] b3;
  input signed [4:0] b4;
  input signed [5:0] b5;

  wire [3:0] y0;
  wire [4:0] y1;
  wire [5:0] y2;
  wire signed [3:0] y3;
  wire signed [4:0] y4;
  wire signed [5:0] y5;
  wire [3:0] y6;
  wire [4:0] y7;
  wire [5:0] y8;
  wire signed [3:0] y9;
  wire signed [4:0] y10;
  wire signed [5:0] y11;
  wire [3:0] y12;
  wire [4:0] y13;
  wire [5:0] y14;
  wire signed [3:0] y15;
  wire signed [4:0] y16;
  wire signed [5:0] y17;

  output [89:0] y;
  assign y = {y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17};

  localparam [3:0] p0 = (!(((4'd1)===(5'sd11))!==((5'd15)?(-5'sd12):(2'd3))));
  localparam [4:0] p1 = ({{(-4'sd3),(-3'sd0),(-2'sd1)},(&(4'd12))}>>(((2'sd0)<<(2'd1))<<<(&(3'd1))));
  localparam [5:0] p2 = ({2{(-3'sd1)}}!={3{(-2'sd1)}});
  localparam signed [3:0] p3 = (~|{3{{3{(-4'sd5)}}}});
  localparam signed [4:0] p4 = ((((-3'sd0)<<(-2'sd1))<<(2'd1))!==(+(2'd2)));
  localparam signed [5:0] p5 = ((((5'd16)?(5'sd5):(3'd0))^(~|(&(2'd0))))>>(3'd5));
  localparam [3:0] p6 = {1{(((4'd6)?(4'd9):(5'sd2))?{((5'd0)?(3'd7):(2'd0))}:({(-3'sd1),(-5'sd14)}>>((-2'sd0)<(5'd20))))
    }};
  localparam [4:0] p7 = {1{(((4'd15)>>(-4'sd5))-{1{(3'd3)}})}};
  localparam [5:0] p8 = (-(((5'd21)?(4'sd5):(4'd4))^((3'd5)?(2'sd1):(2'd1))));
  localparam signed [3:0] p9 = ((&(+((-3'sd3)||(-3'sd2))))?(-2'sd0):((5'd25)?(-2'sd1):(3'd4)));
  localparam signed [4:0] p10 = (((3'sd2)^(5'sd1))!={(-4'sd5)});
  localparam signed [5:0] p11 = (((4'sd6)?(-3'sd3):(3'sd1))?((4'sd1)!==(-5'sd14)):(-((2'sd0)?(5'd12):(2'd2))));
  localparam [3:0] p12 = (5'sd11);
  localparam [4:0] p13 = (~^(-(~|{2{((2'sd0)>>(4'd11))}})));
  localparam [5:0] p14 = ((2'd2)?(2'd3):(-3'sd0));
  localparam signed [3:0] p15 = (6'd2 ** {3{(5'd10)}});
  localparam signed [4:0] p16 = (4'd10);
  localparam signed [5:0] p17 = {((((3'd1)==(5'sd7))!=={4{(4'd7)}})?(-{3{(-3'sd3)}}):(((4'd7)==(3'd6))||((5'd1)&&(5'sd7)))
    )};

  assign y0 = {{((p8?p17:p8)&$signed(p0)),(4'd9)},(((p8)^~(4'd12))>>>(!(p6?p0:p8)))};
  assign y1 = (~{4{{{p17,p6}}}});
  assign y2 = {1{(-(|({4{p15}}!=(p9?p8:p8))))}};
  assign y3 = {(b0?b4:b4)};
  assign y4 = {3{(&{4{p11}})}};
  assign y5 = (4'd0);
  assign y6 = {(+(b0?b2:p0))};
  assign y7 = (|((+$signed($signed((!(&b5)))))));
  assign y8 = ((4'sd4)>>((-3'sd3)!==(a4===a3)));
  assign y9 = (((6'd2 ** b1)?(p11?p0:a5):{b2,p14,p8})|(|(~|{p12,p7,p16})));
  assign y10 = ({1{{2{(b0^~a1)}}}}<({3{b3}}&$signed({a5})));
  assign y11 = (5'd17);
  assign y12 = {4{b1}};
  assign y13 = ({(a2&&p1),$signed({p9,a5,p8})}<(3'sd2));
  assign y14 = (~&a4);
  assign y15 = (-(~^(~^(!{(~^(+(^(~|(~((a0<=b0)|{b3}))))))}))));
  assign y16 = ((b5>>>b4)?(3'd4):(4'd14));
  assign y17 = (6'd2 ** {3{p7}});
endmodule

module expression_00003_tb;
  reg [3:0] a0;
  reg [4:0] a1;
  reg [5:0] a2;
  reg signed [3:0] a3;
  reg signed [4:0] a4;
  reg signed [5:0] a5;
  reg [3:0] b0;
  reg [4:0] b1;
  reg [5:0] b2;
  reg signed [3:0] b3;
  reg signed [4:0] b4;
  reg signed [5:0] b5;
  wire [89:0] y;
  expression_00003 uut (a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
  task test_pattern;
    input [5:0] index;
    input [59:0] pattern;
    begin
      { a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5 } <= pattern; #1;
      $display("++RPT++ %d %b %b %b %b %b %b %b %b %b %b %b %b %b", index,
                    a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, b4, b5, y);
    end
  endtask
  initial begin
    test_pattern(  0, 60'b0 );
    test_pattern(  1, ~60'b0 );
    test_pattern(  2, 60'b100101110000000000001111111111100100001000100111101111111111 );
    test_pattern(  3, 60'b101110010000000000001000100010000000010001111110000101111110 );
    test_pattern(  4, 60'b110110000000000011001001000011111100010001110110011111100011 );
    test_pattern(  5, 60'b110111101000000000011111100001101000101000000111100000000000 );
    test_pattern(  6, 60'b110111110010000000011111000101000100101001111101101000010010 );
    test_pattern(  7, 60'b111011100000000000000101101010010011100001010011000001000010 );
    test_pattern(  8, 60'b111110101000000000011011001100110100010000100111000001111110 );
    test_pattern(  9, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 10, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 11, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 12, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 13, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 14, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 15, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 16, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 17, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 18, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 19, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 20, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 21, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 22, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 23, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 24, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 25, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 26, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 27, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 28, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 29, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 30, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 31, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 32, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 33, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 34, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 35, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 36, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 37, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
    test_pattern( 38, 160'h0039ce0a44678ea554722377e7d713256818f9f9 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a0	0000	0
	a1	00000	0
	a2	000000	0
	a3	0000	0
	a4	00000	0
	a5	000000	0
	b0	0000	0
	b1	00000	0
	b2	000000	0
	b3	0000	0
	b4	00000	0
	b5	000000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y6	0000	0
	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y6	0001	1
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #1		binary	decimal
input signals	a0	1111	15
	a1	11111	31
	a2	111111	63
	a3	1111	-1
	a4	11111	-1
	a5	111111	-1
	b0	1111	15
	b1	11111	31
	b2	111111	63
	b3	1111	-1
	b4	11111	-1
	b5	111111	-1
{icarus,modelsim,xsim,yosim}.quartus	y10	00001	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y10	00000	0

Pattern #2		binary	decimal
input signals	a0	1001	9
	a1	01110	14
	a2	000000	0
	a3	0000	0
	a4	01111	15
	a5	111111	-1
	b0	1001	9
	b1	00001	1
	b2	000100	4
	b3	1111	-1
	b4	01111	15
	b5	111111	-1
{icarus,modelsim,xsim,yosim}.quartus	y9	0000	0
{icarus,modelsim,xsim,yosim}.quartus	y10	00001	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
	y10	00000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1
{icarus,modelsim,xsim,yosim}.vivado	y10	00000	0

Pattern #3		binary	decimal
input signals	a0	1011	11
	a1	10010	18
	a2	000000	0
	a3	0000	0
	a4	01000	8
	a5	100010	-30
	b0	0000	0
	b1	00010	2
	b2	001111	15
	b3	1100	-4
	b4	00101	5
	b5	111110	-2
{icarus,modelsim,xsim,yosim}.quartus	y6	0000	0
	y9	0000	0
	y10	00001	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y6	0000	0
	y9	0000	0
	y10	00000	0
{icarus,modelsim,xsim,yosim}.vivado	y6	0001	1
	y9	0001	1
	y10	00000	0

Pattern #4		binary	decimal
input signals	a0	1101	13
	a1	10000	16
	a2	000000	0
	a3	0110	6
	a4	01001	9
	a5	000011	3
	b0	1111	15
	b1	00010	2
	b2	001110	14
	b3	1100	-4
	b4	11111	-1
	b5	100011	-29
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #5		binary	decimal
input signals	a0	1101	13
	a1	11101	29
	a2	000000	0
	a3	0000	0
	a4	11111	-1
	a5	100001	-31
	b0	1010	10
	b1	00101	5
	b2	000000	0
	b3	1111	-1
	b4	00000	0
	b5	000000	0
{icarus,modelsim,xsim,yosim}.quartus	y9	0000	0
{icarus,modelsim,xsim,yosim}.quartus	y10	00001	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
	y10	00000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1
{icarus,modelsim,xsim,yosim}.vivado	y10	00000	0

Pattern #6		binary	decimal
input signals	a0	1101	13
	a1	11110	30
	a2	010000	16
	a3	0000	0
	a4	11111	-1
	a5	000101	5
	b0	0001	1
	b1	00101	5
	b2	001111	15
	b3	1011	-5
	b4	01000	8
	b5	010010	18
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #7		binary	decimal
input signals	a0	1110	14
	a1	11100	28
	a2	000000	0
	a3	0000	0
	a4	00101	5
	a5	101010	-22
	b0	0100	4
	b1	11100	28
	b2	001010	10
	b3	0110	6
	b4	00001	1
	b5	000010	2
{icarus,modelsim,xsim,yosim}.quartus	y10	00001	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y10	00000	0

Pattern #8		binary	decimal
input signals	a0	1111	15
	a1	10101	21
	a2	000000	0
	a3	0000	0
	a4	11011	-5
	a5	001100	12
	b0	1101	13
	b1	00010	2
	b2	000100	4
	b3	1110	-2
	b4	00001	1
	b5	111110	-2
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #9		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #10		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #11		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #12		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #13		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #14		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #15		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #16		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #17		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #18		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #19		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #20		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #21		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #22		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #23		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #24		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #25		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #26		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #27		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #28		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #29		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #30		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #31		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #32		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #33		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #34		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #35		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #36		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #37		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Pattern #38		binary	decimal
input signals	a0	0111	7
	a1	11010	26
	a2	111000	56
	a3	1001	-7
	a4	10010	-14
	a5	010101	21
	b0	1010	10
	b1	00000	0
	b2	110001	49
	b3	1111	-1
	b4	00111	7
	b5	111001	-7
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y9	0000	0
{icarus,modelsim,xsim,yosim}.vivado	y9	0001	1

Report on issue_000:

This report is part of the following lists: all xst

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	FAIL	PASS	9a7d565c	9a7d565c	9a7d565c	9a7d565c
quartus	PASS	PASS	FAIL	PASS	9a7d565c	9a7d565c	9a7d565c	9a7d565c
xst	FAIL	FAIL	PASS	FAIL	5b2bd700	5b2bd700	5b2bd700	5b2bd700
yosys	PASS	PASS	FAIL	PASS	9a7d565c	9a7d565c	9a7d565c	9a7d565c
rtl	PASS	PASS	FAIL	PASS	9a7d565c	9a7d565c	9a7d565c	9a7d565c

module issue_000(a, y);
  // http://forums.xilinx.com/t5/Synthesis/XST-14-7-sign-handling-bug-in-N-Verilog-operator/td-p/401399
  input signed [1:0] a;
  wire [4:0] y0;
  wire [4:0] y1;
  output [9:0] y;
  assign y = {y0,y1};
  // concatenate and replicate operators do not preserve signedness.
  // the MSB of of y0 and y1 must be constant zero.
  assign y0 = {a,a};
  assign y1 = {2{a}};
endmodule

module issue_000_tb;
  reg signed [1:0] a;
  wire [9:0] y;
  issue_000 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [1:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 2'b0 );
    test_pattern(  1, ~2'b0 );
    test_pattern(  2, 2'b10 );
    test_pattern(  3, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern(  4, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern(  5, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern(  6, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern(  7, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern(  8, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern(  9, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 10, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 11, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 12, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 13, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 14, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 15, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 16, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 17, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 18, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 19, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 20, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 21, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 22, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 23, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 24, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 25, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 26, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 27, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 28, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 29, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 30, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 31, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
    test_pattern( 32, 160'h080d9dd8359e89237e313341de70ba6f033cd173 );
  end
endmodule

Pattern #1		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #2		binary	decimal
input signals	a	10	-2
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01010	10
{icarus,modelsim,xsim,yosim}.xst	y1	11010	26

Pattern #3		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #4		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #5		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #6		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #7		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #8		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #9		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #10		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #11		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #12		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #13		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #14		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #15		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #16		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #17		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #18		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #19		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #20		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #21		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #22		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #23		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #24		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #25		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #26		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #27		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #28		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #29		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #30		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #31		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Pattern #32		binary	decimal
input signals	a	11	-1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y1	01111	15
{icarus,modelsim,xsim,yosim}.xst	y1	11111	31

Report on issue_001:

This report is part of the following lists: all quartus xst

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	PASS	254f878b	254f878b	254f878b	254f878b
quartus	FAIL	PASS	PASS	FAIL	f360c652	f360c652	f360c652	f360c652
xst	FAIL	PASS	PASS	FAIL	f360c652	f360c652	f360c652	f360c652
yosys	PASS	FAIL	FAIL	PASS	254f878b	254f878b	254f878b	254f878b
rtl	PASS	FAIL	FAIL	PASS	254f878b	254f878b	254f878b	254f878b

module issue_001(a, b, y);
  // http://forums.xilinx.com/t5/Synthesis/Bug-in-XST-handling-of-constant-first-argument-in-Verilog/td-p/401407
  // Altera Service Request # 11021734
  input [2:0] a;
  input [3:0] b;
  output [0:0] y;
  // the ?: must evaluate to the max width of both cases,
  // even if we can be sure that always the smaller case gets selected
  assign y = &( 1 ? a : b );
endmodule

module issue_001_tb;
  reg [2:0] a;
  reg [3:0] b;
  wire [0:0] y;
  issue_001 uut (a, b, y);
  task test_pattern;
    input [5:0] index;
    input [6:0] pattern;
    begin
      { a, b } <= pattern; #1;
      $display("++RPT++ %d %b %b %b", index, a, b, y);
    end
  endtask
  initial begin
    test_pattern(  0, 7'b0 );
    test_pattern(  1, ~7'b0 );
    test_pattern(  2, 7'b1110000 );
    test_pattern(  3, 7'b1110111 );
    test_pattern(  4, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern(  5, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern(  6, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern(  7, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern(  8, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern(  9, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 10, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 11, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 12, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 13, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 14, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 15, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 16, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 17, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 18, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 19, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 20, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 21, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 22, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 23, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 24, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 25, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 26, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 27, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 28, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 29, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 30, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 31, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 32, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
    test_pattern( 33, 160'h08dda8e9ab82279593487f8a543d704a73a7e52f );
  end
endmodule

Pattern #1		binary	decimal
input signals	a	111	7
input signals	b	1111	15
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	1	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y	0	0

Pattern #2		binary	decimal
input signals	a	111	7
input signals	b	0000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	1	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y	0	0

Pattern #3		binary	decimal
input signals	a	111	7
input signals	b	0111	7
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	1	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.vivado	y	0	0

Report on issue_002:

This report is part of the following lists: all quartus

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	PASS	PASS	f25e857c	f25e857c	f25e857c	f25e857c
quartus	FAIL	PASS	FAIL	FAIL	96689711	96689711	96689711	96689711
xst	PASS	FAIL	PASS	PASS	f25e857c	f25e857c	f25e857c	f25e857c
yosys	PASS	FAIL	PASS	PASS	f25e857c	f25e857c	f25e857c	f25e857c
rtl	PASS	FAIL	PASS	PASS	f25e857c	f25e857c	f25e857c	f25e857c

module issue_002(a, b, y);
  input [1:0] a;
  input [2:0] b;
  output [0:0] y;
  // the width of $signed(a) is self-determined. so it must return a 2-bit
  // value that is then zero-extended to three bits because the comparison
  // with b is done in an unsigned context (b is unsigned).
  assign y = $signed(a) == b;
endmodule

module issue_002_tb;
  reg [1:0] a;
  reg [2:0] b;
  wire [0:0] y;
  issue_002 uut (a, b, y);
  task test_pattern;
    input [5:0] index;
    input [4:0] pattern;
    begin
      { a, b } <= pattern; #1;
      $display("++RPT++ %d %b %b %b", index, a, b, y);
    end
  endtask
  initial begin
    test_pattern(  0, 5'b0 );
    test_pattern(  1, ~5'b0 );
    test_pattern(  2, 5'b10010 );
    test_pattern(  3, 5'b10110 );
    test_pattern(  4, 5'b11011 );
    test_pattern(  5, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern(  6, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern(  7, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern(  8, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern(  9, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 10, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 11, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 12, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 13, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 14, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 15, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 16, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 17, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 18, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 19, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 20, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 21, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 22, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 23, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 24, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 25, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 26, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 27, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 28, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 29, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 30, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 31, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 32, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 33, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
    test_pattern( 34, 160'h708930f421a984a1380108594a2dd992af34c3a1 );
  end
endmodule

Pattern #1		binary	decimal
input signals	a	11	3
input signals	b	111	7
{icarus,modelsim,xsim,yosim}.quartus	y	1	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	0	0

Pattern #2		binary	decimal
input signals	a	10	2
input signals	b	010	2
{icarus,modelsim,xsim,yosim}.quartus	y	0	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1	1

Pattern #3		binary	decimal
input signals	a	10	2
input signals	b	110	6
{icarus,modelsim,xsim,yosim}.quartus	y	1	1
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	0	0

Pattern #4		binary	decimal
input signals	a	11	3
input signals	b	011	3
{icarus,modelsim,xsim,yosim}.quartus	y	0	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1	1

Report on issue_003:

This report is part of the following lists: all quartus

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	PASS	PASS	bdfd534a	bdfd534a	bdfd534a	bdfd534a
quartus	FAIL	PASS	FAIL	FAIL	a47af875	a47af875	a47af875	a47af875
xst	PASS	FAIL	PASS	PASS	bdfd534a	bdfd534a	bdfd534a	bdfd534a
yosys	PASS	FAIL	PASS	PASS	bdfd534a	bdfd534a	bdfd534a	bdfd534a
rtl	PASS	FAIL	PASS	PASS	bdfd534a	bdfd534a	bdfd534a	bdfd534a

module issue_003(a, y);
  input signed [3:0] a;
  output [4:0] y;
  // the right hand side of a shift operation must always be treated as an unsigned number
  assign y = a << -2'sd1;
endmodule

module issue_003_tb;
  reg signed [3:0] a;
  wire [4:0] y;
  issue_003 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [3:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 4'b0 );
    test_pattern(  1, ~4'b0 );
    test_pattern(  2, 4'b0001 );
    test_pattern(  3, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern(  4, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern(  5, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern(  6, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern(  7, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern(  8, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern(  9, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 10, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 11, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 12, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 13, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 14, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 15, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 16, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 17, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 18, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 19, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 20, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 21, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 22, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 23, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 24, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 25, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 26, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 27, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 28, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 29, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 30, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 31, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
    test_pattern( 32, 160'h178a2fbd51d9531d11f4d8315376e05336851666 );
  end
endmodule

Pattern #1		binary	decimal
input signals	a	1111	-1
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	11000	24

Pattern #2		binary	decimal
input signals	a	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	01000	8

Pattern #3		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #4		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #5		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #6		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #7		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #8		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #9		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #10		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #11		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #12		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #13		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #14		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #15		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #16		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #17		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #18		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #19		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #20		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #21		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #22		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #23		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #24		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #25		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #26		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #27		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #28		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #29		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #30		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #31		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Pattern #32		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y	00000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	10000	16

Report on issue_004:

This report is part of the following lists: all vivado

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	FAIL	1b31cbdb	1b31cbdb	1b31cbdb	1b31cbdb
quartus	FAIL	PASS	PASS	PASS	add46300	add46300	add46300	add46300
xst	FAIL	PASS	PASS	PASS	add46300	add46300	add46300	add46300
yosys	FAIL	PASS	PASS	PASS	add46300	add46300	add46300	add46300
rtl	FAIL	PASS	PASS	PASS	add46300	add46300	add46300	add46300

module issue_004(a, b, y);
  // http://forums.xilinx.com/t5/Synthesis/Strange-output-const-zero-bug-with-Vivado-gt-gt-gt-signedness/td-p/401411
  input [0:0] a;
  input [0:0] b;
  output signed [3:0] y;
  // for some reason vivado thinks this is constant 0.
  // this is obviously not true for a=1 and b=0.
  assign y = $signed(a >>> b);
endmodule

module issue_004_tb;
  reg [0:0] a;
  reg [0:0] b;
  wire signed [3:0] y;
  issue_004 uut (a, b, y);
  task test_pattern;
    input [5:0] index;
    input [1:0] pattern;
    begin
      { a, b } <= pattern; #1;
      $display("++RPT++ %d %b %b %b", index, a, b, y);
    end
  endtask
  initial begin
    test_pattern(  0, 2'b0 );
    test_pattern(  1, ~2'b0 );
    test_pattern(  2, 2'b10 );
    test_pattern(  3, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern(  4, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern(  5, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern(  6, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern(  7, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern(  8, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern(  9, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 10, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 11, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 12, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 13, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 14, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 15, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 16, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 17, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 18, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 19, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 20, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 21, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 22, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 23, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 24, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 25, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 26, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 27, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 28, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 29, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 30, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 31, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
    test_pattern( 32, 160'h2aafb54a9ecb525128d4ec239ef294e2d4e5e033 );
  end
endmodule

Pattern #2		binary	decimal
input signals	a	1	1
input signals	b	0	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst	y	1111	-1
{icarus,modelsim,xsim,yosim}.vivado	y	0000	0

Report on issue_005:

This report is part of the following lists: all noerror

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	FAIL	0f10f226	0f10f226	0f10f226	0f10f226
quartus	PASS	PASS	PASS	FAIL	0f10f226	0f10f226	0f10f226	0f10f226
xst	PASS	PASS	PASS	FAIL	0f10f226	0f10f226	0f10f226	0f10f226
yosys	FAIL	FAIL	FAIL	PASS	0f10f226	0f10f226	0f10f226	0f10f226
rtl	PASS	PASS	PASS	PASS	0f10f226	0f10f226	0f10f226	0f10f226

module issue_005(a, y);
  input signed [2:0] a;
  wire [2:0] y0;
  wire [2:0] y1;
  wire [2:0] y2;
  wire [2:0] y3;
  wire [2:0] y4;
  wire [2:0] y5;
  wire [2:0] y6;
  wire [2:0] y7;
  output [23:0] y;
  assign y = {y0,y1,y2,y3,y4,y5,y6,y7};
  // a couple of test cases for width-extending when $signed() and $unsigned() is used. 
  // the tricky part is to know when the result is 3'bxxx and when it is 3'b00x for a=0.
  assign y0 = $signed(|a);
  assign y1 = $unsigned(|a);
  assign y2 = $signed(|(a/a));
  assign y3 = $unsigned(|(a/a));
  assign y4 = $signed((|a)/(|a));
  assign y5 = $unsigned((|a)/(|a));
  assign y6 = |(a/a);
  assign y7 = (|a)/(|a);
endmodule

module issue_005_tb;
  reg signed [2:0] a;
  wire [23:0] y;
  issue_005 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [2:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 3'b0 );
    test_pattern(  1, ~3'b0 );
    test_pattern(  2, 3'b000 );
    test_pattern(  3, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern(  4, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern(  5, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern(  6, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern(  7, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern(  8, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern(  9, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 10, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 11, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 12, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 13, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 14, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 15, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 16, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 17, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 18, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 19, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 20, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 21, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 22, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 23, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 24, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 25, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 26, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 27, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 28, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 29, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 30, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 31, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
    test_pattern( 32, 160'h2b4c5b03eaf4c7da1495c9f2e3ab603ca5ff1705 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y2	111	7
	y3	001	1
	y4	111	7
	y5	001	1
	y6	001	1
	y7	001	1
{icarus,modelsim,xsim,yosim}.rtl	y2	xxx	X
	y3	00x	X
	y4	xxx	X
	y5	00x	X
	y6	00x	X
	y7	xxx	X
{icarus,modelsim,xsim,yosim}.yosys	y2	111	7
	y3	001	1
	y4	111	7
	y5	001	1
	y6	001	1
	y7	111	7

Pattern #2		binary	decimal
input signals	a	000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y2	111	7
	y3	001	1
	y4	111	7
	y5	001	1
	y6	001	1
	y7	001	1
{icarus,modelsim,xsim,yosim}.rtl	y2	xxx	X
	y3	00x	X
	y4	xxx	X
	y5	00x	X
	y6	00x	X
	y7	xxx	X
{icarus,modelsim,xsim,yosim}.yosys	y2	111	7
	y3	001	1
	y4	111	7
	y5	001	1
	y6	001	1
	y7	111	7

Report on issue_006:

This report is part of the following lists: all noerror

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	PASS	7df333f5	7df333f5	7df333f5	7df333f5
quartus	PASS	PASS	PASS	PASS	7df333f5	7df333f5	7df333f5	7df333f5
xst	PASS	PASS	PASS	PASS	7df333f5	7df333f5	7df333f5	7df333f5
yosys	PASS	PASS	PASS	PASS	7df333f5	7df333f5	7df333f5	7df333f5
rtl	PASS	PASS	PASS	PASS	7df333f5	7df333f5	7df333f5	7df333f5

module issue_006(a, y);
  input [4:0] a;
  output [4:0] y;
  // icarus verilog has a bug (git 336b299) that prevents it from
  // evaluating ^~ in parameters. This is just a quick test of all
  // verilog expressions in localparams to catch such bugs.
  localparam [4:0] pb00 = 5'd00 +   5'd3;
  localparam [4:0] pb01 = 5'd01 -   5'd3;
  localparam [4:0] pb02 = 5'd02 *   5'd3;
  localparam [4:0] pb03 = 5'd03 /   5'd3;
  localparam [4:0] pb04 = 5'd04 %   5'd3;
  localparam [4:0] pb05 = 5'd05 **  5'd3;
  localparam [4:0] pb06 = 5'd06 >   5'd3;
  localparam [4:0] pb07 = 5'd07 >=  5'd3;
  localparam [4:0] pb08 = 5'd08 <   5'd3;
  localparam [4:0] pb09 = 5'd09 <=  5'd3;
  localparam [4:0] pb10 = 5'd10 &&  5'd3;
  localparam [4:0] pb11 = 5'd11 ||  5'd3;
  localparam [4:0] pb12 = 5'd12 ==  5'd3;
  localparam [4:0] pb13 = 5'd13 !=  5'd3;
  localparam [4:0] pb14 = 5'd14 === 5'd3;
  localparam [4:0] pb15 = 5'd15 !== 5'd3;
  localparam [4:0] pb16 = 5'd16 &   5'd3;
  localparam [4:0] pb17 = 5'd17 |   5'd3;
  localparam [4:0] pb18 = 5'd18 ^   5'd3;
  localparam [4:0] pb19 = 5'd19 ^~  5'd3;
  localparam [4:0] pb20 = 5'd20 <<  5'd3;
  localparam [4:0] pb21 = 5'd21 >>  5'd3;
  localparam [4:0] pb22 = 5'd22 <<< 5'd3;
  localparam [4:0] pb23 = 5'd23 >>> 5'd3;
  localparam [4:0] pu00 = +  5'd00;
  localparam [4:0] pu01 = -  5'd01;
  localparam [4:0] pu02 = !  5'd02;
  localparam [4:0] pu03 = ~  5'd03;
  localparam [4:0] pu04 = &  5'd04;
  localparam [4:0] pu05 = ~& 5'd05;
  localparam [4:0] pu06 = |  5'd06;
  localparam [4:0] pu07 = ~| 5'd07;
  localparam [4:0] pu08 = ^  5'd08;
  localparam [4:0] pu09 = ~^ 5'd09;
  localparam [4:0] pter = 1 ? 2 : 3;
  assign y = pb00 ^ pb01 ^ pb02 ^ pb03 ^ pb04 ^ pb05 ^ pb06 ^ pb07 ^ pb08 ^
             pb09 ^ pb10 ^ pb11 ^ pb12 ^ pb13 ^ pb14 ^ pb15 ^ pb16 ^ pb17 ^
             pb18 ^ pb19 ^ pb20 ^ pb21 ^ pb22 ^ pb23 ^ pu00 ^ pu01 ^ pu02 ^
             pu03 ^ pu04 ^ pu05 ^ pu06 ^ pu07 ^ pu08 ^ pu09 ^ pter ^ a;
endmodule

module issue_006_tb;
  reg [4:0] a;
  wire [4:0] y;
  issue_006 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [4:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 5'b0 );
    test_pattern(  1, ~5'b0 );
    test_pattern(  2, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern(  3, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern(  4, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern(  5, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern(  6, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern(  7, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern(  8, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern(  9, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 10, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 11, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 12, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 13, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 14, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 15, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 16, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 17, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 18, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 19, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 20, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 21, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 22, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 23, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 24, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 25, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 26, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 27, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 28, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 29, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 30, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
    test_pattern( 31, 160'h4ea8242bb18312ae5b6b7f44cea521546c869cdb );
  end
endmodule

Report on issue_007:

This report is part of the following lists: all noerror

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	FAIL	b06e05f5	b06e05f5	b06e05f5	b06e05f5
quartus	FAIL	PASS	PASS	PASS	b06e05f5	b06e05f5	b06e05f5	b06e05f5
xst	FAIL	PASS	PASS	PASS	b06e05f5	b06e05f5	b06e05f5	b06e05f5
yosys	FAIL	PASS	PASS	PASS	b06e05f5	b06e05f5	b06e05f5	b06e05f5
rtl	PASS	PASS	PASS	PASS	b06e05f5	b06e05f5	b06e05f5	b06e05f5

module issue_007(a, y);
  input [3:0] a;
  wire [3:0] y0;
  wire [3:0] y1;
  wire [3:0] y2;
  wire [3:0] y3;
  output [15:0] y;
  assign y = {y0,y1,y2,y3};
  // constant evaluation of width-extension with undefs
  localparam [1:0] p0 = |(1/0);
  localparam [1:0] p1 = (|1)/(|0);
  assign y0 = p0;         // 4'b000x
  assign y1 = p1;         // 4'b00xx
  assign y2 = |(1/0);     // 4'b000x
  assign y3 = (|1)/(|0);  // 4'bxxxx
endmodule

module issue_007_tb;
  reg [3:0] a;
  wire [15:0] y;
  issue_007 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [3:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 4'b0 );
    test_pattern(  1, ~4'b0 );
    test_pattern(  2, 4'b0000 );
    test_pattern(  3, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern(  4, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern(  5, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern(  6, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern(  7, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern(  8, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern(  9, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 10, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 11, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 12, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 13, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 14, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 15, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 16, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 17, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 18, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 19, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 20, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 21, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 22, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 23, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 24, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 25, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 26, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 27, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 28, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 29, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 30, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 31, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
    test_pattern( 32, 160'h165f32543217b12fc05810c766a25130d6a0e575 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #1		binary	decimal
input signals	a	1111	15
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #2		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #3		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #4		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #5		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #6		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #7		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #8		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #9		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #10		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #11		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #12		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #13		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #14		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #15		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #16		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #17		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #18		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #19		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #20		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #21		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #22		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #23		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #24		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #25		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #26		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #27		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #28		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #29		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #30		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #31		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Pattern #32		binary	decimal
input signals	a	0101	5
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	000x	X
	y1	00xx	X
	y2	000x	X
	y3	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0001	1
	y1	0000	0
	y2	0001	1
	y3	0000	0

Report on issue_008:

This report is part of the following lists: all quartus xsim

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	PASS	PASS	12b2a10c	02a263ed	02a263ed	02a263ed
quartus	FAIL	PASS	FAIL	FAIL	a7c4cc1b	3e6afa3d	3e6afa3d	3e6afa3d
xst	PASS	FAIL	PASS	PASS	12b2a10c	02a263ed	02a263ed	02a263ed
yosys	PASS	FAIL	PASS	PASS	02a263ed	02a263ed	02a263ed	02a263ed
rtl	PASS	FAIL	PASS	PASS	12b2a10c	02a263ed	02a263ed	02a263ed

module issue_008(a, y);
  input [1:0] a;
  output [167:0] y;

  wire [7:0] y0;
  wire [7:0] y1;
  wire [7:0] y2;
  wire [7:0] y3;
  wire [7:0] y4;
  wire [7:0] y5;
  wire [7:0] y6;
  wire [7:0] y7;
  wire [7:0] y8;
  wire [7:0] y9;
  wire [7:0] y10;
  wire [7:0] y11;
  wire [7:0] y12;
  wire [7:0] y13;
  wire [7:0] y14;
  wire [7:0] y15;
  wire [7:0] y16;
  wire [7:0] y17;
  wire [7:0] y18;
  wire [7:0] y19;
  wire [7:0] y20;
  assign y = {y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17,y18,y19,y20};

  // constant evaluation of power operator (signed ** signed)
  localparam [7:0] ss0  = +8'sd0 ** -8'sd1;
  localparam [7:0] ss1  = +8'sd0 ** +8'sd1;
  localparam [7:0] ss2  = -8'sd2 ** -8'sd2;
  localparam [7:0] ss3  = -8'sd1 ** -8'sd2;
  localparam [7:0] ss4  = +8'sd1 ** -8'sd2;
  localparam [7:0] ss5  = +8'sd2 ** -8'sd2;
  localparam [7:0] ss6  = -8'sd2 ** -8'sd3;
  localparam [7:0] ss7  = -8'sd1 ** -8'sd3;
  localparam [7:0] ss8  = +8'sd1 ** -8'sd3;
  localparam [7:0] ss9  = +8'sd2 ** -8'sd3;
  localparam [7:0] ss10 = +8'sd3 ** +8'sd2;
  localparam [7:0] ss11 = -8'sd1 ** +8'sd1;
  localparam [7:0] ss12 = -8'sd1 ** +8'sd3;
  localparam [7:0] ss13 = -8'sd2 ** +8'sd1;
  localparam [7:0] ss14 = -8'sd2 ** +8'sd3;
  localparam [7:0] ss15 = -8'sd3 ** +8'sd3;
  localparam [7:0] ss16 = -8'sd2 ** +8'sd0;
  localparam [7:0] ss17 = -8'sd1 ** +8'sd0;
  localparam [7:0] ss18 = +8'sd0 ** +8'sd0;
  localparam [7:0] ss19 = +8'sd1 ** +8'sd0;
  localparam [7:0] ss20 = +8'sd2 ** +8'sd0;

  // constant evaluation of power operator (signed ** unsigned)
  localparam [7:0] su0  = +8'sd0 ** -8'd1;
  localparam [7:0] su1  = +8'sd0 ** +8'd1;
  localparam [7:0] su2  = -8'sd2 ** -8'd2;
  localparam [7:0] su3  = -8'sd1 ** -8'd2;
  localparam [7:0] su4  = +8'sd1 ** -8'd2;
  localparam [7:0] su5  = +8'sd2 ** -8'd2;
  localparam [7:0] su6  = -8'sd2 ** -8'd3;
  localparam [7:0] su7  = -8'sd1 ** -8'd3;
  localparam [7:0] su8  = +8'sd1 ** -8'd3;
  localparam [7:0] su9  = +8'sd2 ** -8'd3;
  localparam [7:0] su10 = +8'sd3 ** +8'd2;
  localparam [7:0] su11 = -8'sd1 ** +8'd1;
  localparam [7:0] su12 = -8'sd1 ** +8'd3;
  localparam [7:0] su13 = -8'sd2 ** +8'd1;
  localparam [7:0] su14 = -8'sd2 ** +8'd3;
  localparam [7:0] su15 = -8'sd3 ** +8'd3;
  localparam [7:0] su16 = -8'sd2 ** +8'd0;
  localparam [7:0] su17 = -8'sd1 ** +8'd0;
  localparam [7:0] su18 = +8'sd0 ** +8'd0;
  localparam [7:0] su19 = +8'sd1 ** +8'd0;
  localparam [7:0] su20 = +8'sd2 ** +8'd0;

  // constant evaluation of power operator (unsigned ** signed)
  localparam [7:0] us0  = +8'd0 ** -8'sd1;
  localparam [7:0] us1  = +8'd0 ** +8'sd1;
  localparam [7:0] us2  = -8'd2 ** -8'sd2;
  localparam [7:0] us3  = -8'd1 ** -8'sd2;
  localparam [7:0] us4  = +8'd1 ** -8'sd2;
  localparam [7:0] us5  = +8'd2 ** -8'sd2;
  localparam [7:0] us6  = -8'd2 ** -8'sd3;
  localparam [7:0] us7  = -8'd1 ** -8'sd3;
  localparam [7:0] us8  = +8'd1 ** -8'sd3;
  localparam [7:0] us9  = +8'd2 ** -8'sd3;
  localparam [7:0] us10 = +8'd3 ** +8'sd2;
  localparam [7:0] us11 = -8'd1 ** +8'sd1;
  localparam [7:0] us12 = -8'd1 ** +8'sd3;
  localparam [7:0] us13 = -8'd2 ** +8'sd1;
  localparam [7:0] us14 = -8'd2 ** +8'sd3;
  localparam [7:0] us15 = -8'd3 ** +8'sd3;
  localparam [7:0] us16 = -8'd2 ** +8'sd0;
  localparam [7:0] us17 = -8'd1 ** +8'sd0;
  localparam [7:0] us18 = +8'd0 ** +8'sd0;
  localparam [7:0] us19 = +8'd1 ** +8'sd0;
  localparam [7:0] us20 = +8'd2 ** +8'sd0;

  // constant evaluation of power operator (unsigned ** unsigned)
  localparam [7:0] uu0  = +8'd0 ** -8'd1;
  localparam [7:0] uu1  = +8'd0 ** +8'd1;
  localparam [7:0] uu2  = -8'd2 ** -8'd2;
  localparam [7:0] uu3  = -8'd1 ** -8'd2;
  localparam [7:0] uu4  = +8'd1 ** -8'd2;
  localparam [7:0] uu5  = +8'd2 ** -8'd2;
  localparam [7:0] uu6  = -8'd2 ** -8'd3;
  localparam [7:0] uu7  = -8'd1 ** -8'd3;
  localparam [7:0] uu8  = +8'd1 ** -8'd3;
  localparam [7:0] uu9  = +8'd2 ** -8'd3;
  localparam [7:0] uu10 = +8'd3 ** +8'd2;
  localparam [7:0] uu11 = -8'd1 ** +8'd1;
  localparam [7:0] uu12 = -8'd1 ** +8'd3;
  localparam [7:0] uu13 = -8'd2 ** +8'd1;
  localparam [7:0] uu14 = -8'd2 ** +8'd3;
  localparam [7:0] uu15 = -8'd3 ** +8'd3;
  localparam [7:0] uu16 = -8'd2 ** +8'd0;
  localparam [7:0] uu17 = -8'd1 ** +8'd0;
  localparam [7:0] uu18 = +8'd0 ** +8'd0;
  localparam [7:0] uu19 = +8'd1 ** +8'd0;
  localparam [7:0] uu20 = +8'd2 ** +8'd0;

  assign y0  = a == 0 ? ss0  : a == 1 ? su0  : a == 2 ? us0  : uu0;
  assign y1  = a == 0 ? ss1  : a == 1 ? su1  : a == 2 ? us1  : uu1;
  assign y2  = a == 0 ? ss2  : a == 1 ? su2  : a == 2 ? us2  : uu2;
  assign y3  = a == 0 ? ss3  : a == 1 ? su3  : a == 2 ? us3  : uu3;
  assign y4  = a == 0 ? ss4  : a == 1 ? su4  : a == 2 ? us4  : uu4;
  assign y5  = a == 0 ? ss5  : a == 1 ? su5  : a == 2 ? us5  : uu5;
  assign y6  = a == 0 ? ss6  : a == 1 ? su6  : a == 2 ? us6  : uu6;
  assign y7  = a == 0 ? ss7  : a == 1 ? su7  : a == 2 ? us7  : uu7;
  assign y8  = a == 0 ? ss8  : a == 1 ? su8  : a == 2 ? us8  : uu8;
  assign y9  = a == 0 ? ss9  : a == 1 ? su9  : a == 2 ? us9  : uu9;
  assign y10 = a == 0 ? ss10 : a == 1 ? su10 : a == 2 ? us10 : uu10;
  assign y11 = a == 0 ? ss11 : a == 1 ? su11 : a == 2 ? us11 : uu11;
  assign y12 = a == 0 ? ss12 : a == 1 ? su12 : a == 2 ? us12 : uu12;
  assign y13 = a == 0 ? ss13 : a == 1 ? su13 : a == 2 ? us13 : uu13;
  assign y14 = a == 0 ? ss14 : a == 1 ? su14 : a == 2 ? us14 : uu14;
  assign y15 = a == 0 ? ss15 : a == 1 ? su15 : a == 2 ? us15 : uu15;
  assign y16 = a == 0 ? ss16 : a == 1 ? su16 : a == 2 ? us16 : uu16;
  assign y17 = a == 0 ? ss17 : a == 1 ? su17 : a == 2 ? us17 : uu17;
  assign y18 = a == 0 ? ss18 : a == 1 ? su18 : a == 2 ? us18 : uu18;
  assign y19 = a == 0 ? ss19 : a == 1 ? su19 : a == 2 ? us19 : uu19;
  assign y20 = a == 0 ? ss20 : a == 1 ? su20 : a == 2 ? us20 : uu20;
endmodule

module issue_008_tb;
  reg [1:0] a;
  wire [167:0] y;
  issue_008 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [1:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 2'b0 );
    test_pattern(  1, ~2'b0 );
    test_pattern(  2, 2'b10 );
    test_pattern(  3, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern(  4, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern(  5, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern(  6, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern(  7, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern(  8, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern(  9, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 10, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 11, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 12, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 13, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 14, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 15, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 16, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 17, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 18, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 19, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 20, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 21, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 22, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 23, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 24, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 25, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 26, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 27, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 28, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 29, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 30, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 31, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
    test_pattern( 32, 160'h6cf642365196f4ef3674258fca8d96d134d91655 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X

Pattern #2		binary	decimal
input signals	a	10	2
{icarus,modelsim,xsim,yosim}.quartus	y0	00000000	0
	y3	00000001	1
	y7	11111111	255
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y3	00000000	0
	y7	00000000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y3	00000000	0
	y7	00000000	0

Report on issue_009:

This report is part of the following lists: all quartus vivado

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	FAIL	c6be5886	c6be5886	c6be5886	c6be5886
quartus	FAIL	PASS	FAIL	FAIL	dc4c9c98	dc4c9c98	dc4c9c98	dc4c9c98
xst	FAIL	FAIL	PASS	FAIL	284820c8	284820c8	284820c8	284820c8
yosys	FAIL	FAIL	FAIL	PASS	284820c8	284820c8	284820c8	284820c8
rtl	FAIL	FAIL	PASS	PASS	284820c8	284820c8	284820c8	284820c8

module issue_009(a, y);
  input [2:0] a;
  output [75:0] y;

  wire [3:0] y0;
  wire [3:0] y1;
  wire [3:0] y2;
  wire [3:0] y3;
  wire [3:0] y4;
  wire [3:0] y5;
  wire [3:0] y6;
  wire [3:0] y7;
  wire [3:0] y8;
  wire [3:0] y9;
  wire [3:0] y10;
  wire [3:0] y11;
  wire [3:0] y12;
  wire [3:0] y13;
  wire [3:0] y14;
  wire [3:0] y15;
  wire [3:0] y16;
  wire [3:0] y17;
  wire [3:0] y18;

  assign y = {y0,y1,y2,y3,y4,y5,y6,y7,y8,y9,y10,y11,y12,y13,y14,y15,y16,y17,y18};

  // various tests for handling bit-extension of and operations with undef values
  // e.g. bitwise operations must 0-extend their arguments (even with undef msb)
  assign y0  = a +  1'bx;
  assign y1  = a -  1'bx;
  assign y2  = a *  1'bx;
  assign y3  = a /  1'bx;
  assign y4  = a %  1'bx;
  assign y5  = a >  1'bx;
  assign y6  = a >= 1'bx;
  assign y7  = a <  1'bx;
  assign y8  = a <= 1'bx;
  assign y9  = a && 1'bx;
  assign y10 = a || 1'bx;
  assign y11 = a == 1'bx;
  assign y12 = a != 1'bx;
  assign y13 = a &  1'bx;
  assign y14 = a |  1'bx;
  assign y15 = a ^  1'bx;
  assign y16 = a ^~ 1'bx;
  assign y17 = + 1'bx;
  assign y18 = - 1'bx;
endmodule

module issue_009_tb;
  reg [2:0] a;
  wire [75:0] y;
  issue_009 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [2:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 3'b0 );
    test_pattern(  1, ~3'b0 );
    test_pattern(  2, 3'b000 );
    test_pattern(  3, 3'b001 );
    test_pattern(  4, 3'b010 );
    test_pattern(  5, 3'b101 );
    test_pattern(  6, 3'b110 );
    test_pattern(  7, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern(  8, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern(  9, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 10, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 11, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 12, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 13, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 14, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 15, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 16, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 17, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 18, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 19, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 20, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 21, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 22, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 23, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 24, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 25, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 26, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 27, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 28, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 29, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 30, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 31, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 32, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 33, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 34, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 35, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
    test_pattern( 36, 160'h7bb5c3cc23d6bf20e0ec253b5b619b0b00f07273 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	000	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y10	0001	1
	y11	0000	0
	y12	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y10	000x	X
	y11	000x	X
	y12	000x	X
	y14	000x	X
	y15	000x	X
	y16	111x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	1111	15
	y2	0000	0
	y3	0011	3
	y4	0000	0
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y10	0001	1
	y11	0010	2
	y12	0010	2
	y14	0001	1
	y15	0000	0
	y16	1110	14
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y10	0001	1
	y11	0001	1
	y12	0000	0
	y14	0000	0
	y15	0000	0
	y16	1111	15
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	0000	0
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y10	0001	1
	y11	0000	0
	y12	0001	1
	y14	0001	1
	y15	000x	X
	y16	111x	X
	y17	000x	X
	y18	xxxx	X

Pattern #1		binary	decimal
input signals	a	111	7
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0111	7
	y15	011x	X
	y16	100x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	1001	9
	y1	0110	6
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0111	7
	y15	0110	6
	y16	1000	8
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0111	7
	y15	0111	7
	y16	1000	8
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0111	7
	y15	011x	X
	y16	100x	X
	y17	000x	X
	y18	xxxx	X

Pattern #2		binary	decimal
input signals	a	000	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y10	0001	1
	y11	0000	0
	y12	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y10	000x	X
	y11	000x	X
	y12	000x	X
	y14	000x	X
	y15	000x	X
	y16	111x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	1111	15
	y2	0000	0
	y3	0011	3
	y4	0000	0
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y10	0001	1
	y11	0010	2
	y12	0010	2
	y14	0001	1
	y15	0000	0
	y16	1110	14
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y10	0001	1
	y11	0001	1
	y12	0000	0
	y14	0000	0
	y15	0000	0
	y16	1111	15
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	0000	0
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y10	0001	1
	y11	0000	0
	y12	0001	1
	y14	0001	1
	y15	000x	X
	y16	111x	X
	y17	000x	X
	y18	xxxx	X

Pattern #3		binary	decimal
input signals	a	001	1
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	000x	X
	y12	000x	X
	y13	000x	X
	y14	0001	1
	y15	000x	X
	y16	111x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0011	3
	y1	0000	0
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0001	1
	y15	0000	0
	y16	1110	14
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0001	1
	y12	0000	0
	y13	0000	0
	y14	0001	1
	y15	0001	1
	y16	1110	14
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0001	1
	y15	000x	X
	y16	111x	X
	y17	000x	X
	y18	xxxx	X

Pattern #4		binary	decimal
input signals	a	010	2
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y14	001x	X
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0100	4
	y1	0001	1
	y2	0000	0
	y3	0011	3
	y4	0000	0
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y14	0010	2
	y15	0010	2
	y16	1101	13
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxx0	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #5		binary	decimal
input signals	a	101	5
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0101	5
	y15	010x	X
	y16	101x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0111	7
	y1	0100	4
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0101	5
	y15	0100	4
	y16	1010	10
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0101	5
	y15	0101	5
	y16	1010	10
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0101	5
	y15	010x	X
	y16	101x	X
	y17	000x	X
	y18	xxxx	X

Pattern #6		binary	decimal
input signals	a	110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y14	011x	X
	y15	011x	X
	y16	100x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	1000	8
	y1	0101	5
	y2	0000	0
	y3	0011	3
	y4	0000	0
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y14	0111	7
	y15	0110	6
	y16	1000	8
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y14	0110	6
	y15	0110	6
	y16	1001	9
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxx0	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y14	0111	7
	y15	011x	X
	y16	100x	X
	y17	000x	X
	y18	xxxx	X

Pattern #7		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #8		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #9		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #10		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #11		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #12		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #13		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #14		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #15		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #16		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #17		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #18		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #19		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #20		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #21		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #22		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #23		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #24		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #25		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #26		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #27		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #28		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #29		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #30		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #31		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #32		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #33		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #34		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #35		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Pattern #36		binary	decimal
input signals	a	011	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0000	0
	y13	0000	0
	y14	1111	15
	y15	0000	0
	y16	0000	0
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	xxxx	X
	y4	xxxx	X
	y5	000x	X
	y6	000x	X
	y7	000x	X
	y8	000x	X
	y9	000x	X
	y11	0000	0
	y12	0001	1
	y13	000x	X
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0101	5
	y1	0010	2
	y2	0000	0
	y3	0011	3
	y4	0001	1
	y5	0010	2
	y6	0010	2
	y7	0010	2
	y8	0010	2
	y9	0001	1
	y11	0010	2
	y12	0010	2
	y13	0000	0
	y14	0011	3
	y15	0010	2
	y16	1100	12
	y17	0000	0
	y18	1111	15
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
	y6	0000	0
	y7	0000	0
	y8	0000	0
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	0011	3
	y16	1100	12
	y17	0000	0
	y18	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	xxxx	X
	y1	xxxx	X
	y2	xxxx	X
	y3	0001	1
	y4	xxxx	X
	y5	0001	1
	y6	0001	1
	y7	0001	1
	y8	0001	1
	y9	0000	0
	y11	0000	0
	y12	0001	1
	y13	0000	0
	y14	0011	3
	y15	001x	X
	y16	110x	X
	y17	000x	X
	y18	xxxx	X

Report on issue_010:

This report is part of the following lists: all vivado

Synthesis of issue_010 using vivado failed!

	quartus	xst	yosys	xsim	modelsim	icarus	yosim
quartus	PASS	PASS	PASS	028481dc	028481dc	028481dc	028481dc
xst	PASS	PASS	PASS	028481dc	028481dc	028481dc	028481dc
yosys	PASS	PASS	PASS	028481dc	028481dc	028481dc	028481dc
rtl	PASS	PASS	PASS	028481dc	028481dc	028481dc	028481dc

module issue_010(a, b, y);
  // http://forums.xilinx.com/t5/Synthesis/Vivado-creates-netlist-with-inputs-shorted-together/td-p/397161
  input [5:0] a;
  input [3:0] b;

  // I have no clue why but Vivado 2013.4 generates a netlist containing:
  //
  //   assign \<const0>  = a[3];
  //   assign \<const0>  = a[2];
  //   assign \<const0>  = a[1];
  //   assign \<const0>  = b[3];
  //   assign \<const0>  = b[2];
  //   assign \<const0>  = b[1];
  //   assign \<const0>  = b[0];
  //
  //   IBUF IBUF
  //         (.I(\<const0> ),
  //          .O(xlnx_opt_));
  //
  // (when synthesized with (* use_dsp48 = "no" *) set on the module)

  wire [80:0] y0;
  wire [4:0] y1;
  wire [3:0] y2;

  output [89:0] y;
  assign y = {y0,y1,y2};

  assign y0  = 0;
  assign y1  = {4{{3{b}}}};
  assign y2  = 4'b1000 * a;
endmodule

module issue_010_tb;
  reg [5:0] a;
  reg [3:0] b;
  wire [89:0] y;
  issue_010 uut (a, b, y);
  task test_pattern;
    input [5:0] index;
    input [9:0] pattern;
    begin
      { a, b } <= pattern; #1;
      $display("++RPT++ %d %b %b %b", index, a, b, y);
    end
  endtask
  initial begin
    test_pattern(  0, 10'b0 );
    test_pattern(  1, ~10'b0 );
    test_pattern(  2, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern(  3, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern(  4, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern(  5, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern(  6, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern(  7, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern(  8, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern(  9, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 10, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 11, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 12, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 13, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 14, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 15, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 16, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 17, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 18, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 19, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 20, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 21, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 22, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 23, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 24, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 25, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 26, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 27, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 28, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 29, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 30, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
    test_pattern( 31, 160'hab280d2cf714c6dbe6bdff23b9c16102a0bca109 );
  end
endmodule

Report on issue_011:

This report is part of the following lists: all noerror

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	PASS	8bc7c46a	8bc7c46a	8bc7c46a	8bc7c46a
quartus	PASS	PASS	PASS	PASS	8bc7c46a	8bc7c46a	8bc7c46a	8bc7c46a
xst	PASS	PASS	PASS	PASS	8bc7c46a	8bc7c46a	8bc7c46a	8bc7c46a
yosys	PASS	PASS	PASS	PASS	8bc7c46a	8bc7c46a	8bc7c46a	8bc7c46a
rtl	PASS	PASS	PASS	PASS	8bc7c46a	8bc7c46a	8bc7c46a	8bc7c46a

module issue_011(a, y);
  // https://github.com/steveicarus/iverilog/issues/6
  input [0:0] a;
  output [0:0] y;
  // icarus verilog vpp (fixed in git d1c9dd5) asserts on this expression
  //   Internal error: Input vector expected width=1, got bit=2'b00, base=0, vwid=2
  assign y  = |(-a);
endmodule

module issue_011_tb;
  reg [0:0] a;
  wire [0:0] y;
  issue_011 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [0:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 1'b0 );
    test_pattern(  1, ~1'b0 );
    test_pattern(  2, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern(  3, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern(  4, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern(  5, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern(  6, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern(  7, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern(  8, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern(  9, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 10, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 11, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 12, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 13, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 14, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 15, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 16, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 17, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 18, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 19, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 20, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 21, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 22, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 23, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 24, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 25, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 26, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 27, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 28, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 29, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 30, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
    test_pattern( 31, 160'h418e97341e997af14178d69c13bf67b29b4d854f );
  end
endmodule

Report on issue_012:

This report is part of the following lists: all icarus

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	FAIL	b9d03fc2	b9d03fc2	c57130c8	b9d03fc2
quartus	PASS	PASS	PASS	FAIL	b9d03fc2	b9d03fc2	c57130c8	b9d03fc2
xst	PASS	PASS	PASS	FAIL	b9d03fc2	b9d03fc2	c57130c8	b9d03fc2
yosys	FAIL	FAIL	FAIL	PASS	b9d03fc2	b9d03fc2	d18ab38f	b9d03fc2
rtl	PASS	PASS	PASS	PASS	b9d03fc2	b9d03fc2	ace4c37f	b9d03fc2

module issue_012(a, y);
  // https://github.com/steveicarus/iverilog/issues/7
  input [3:0] a;
  output [3:0] y;
  // icarus verilog (git d1c9dd5) does not correctly propagate undef thru power
  // operator (y should be 4'bx when a is zero, but iverilog returns 4'd1).
  assign y = 4'd2 ** (4'd1/a);
endmodule

module issue_012_tb;
  reg [3:0] a;
  wire [3:0] y;
  issue_012 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [3:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 4'b0 );
    test_pattern(  1, ~4'b0 );
    test_pattern(  2, 4'b0000 );
    test_pattern(  3, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern(  4, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern(  5, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern(  6, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern(  7, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern(  8, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern(  9, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 10, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 11, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 12, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 13, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 14, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 15, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 16, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 17, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 18, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 19, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 20, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 21, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 22, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 23, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 24, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 25, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 26, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 27, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 28, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 29, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 30, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 31, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
    test_pattern( 32, 160'hf148df36016b8235ab08b1dc22629591aa05e809 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	0010	2
icarus.rtl	y	0001	1
{icarus,modelsim,xsim,yosim}.yosys	y	0000	0
{modelsim,xsim,yosim}.rtl	y	xxxx	X

Pattern #2		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	0010	2
icarus.rtl	y	0001	1
{icarus,modelsim,xsim,yosim}.yosys	y	0000	0
{modelsim,xsim,yosim}.rtl	y	xxxx	X

Report on issue_013:

This report is part of the following lists: all icarus

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	PASS	ef061334	ef061334	ef061334	ef061334
quartus	PASS	PASS	PASS	PASS	ef061334	ef061334	ef061334	ef061334
xst	PASS	PASS	PASS	PASS	ef061334	ef061334	ef061334	ef061334
yosys	PASS	PASS	PASS	PASS	ef061334	ef061334	ef061334	ef061334
rtl	PASS	PASS	PASS	PASS	ef061334	ef061334	1942741a	ef061334

module issue_013(a, y);
  // https://github.com/steveicarus/iverilog/issues/8
  input signed [3:0] a;
  output [1:0] y;
  // icarus verilog (git d1c9dd5) evaluates bit-wise operations of signed values
  // to unsigned values when the arguments are constant. Thus "a = 0" yields
  // "y[0] = 0" in icarus verilog, even though it should be "y[1] = 1 (see
  // sec. 5.5.1 of IEEE Std 1365-2005). bitwise operations of variables or
  // variables with constants are implemented correctly. So y[1] always shows
  // the right value.
  assign y[0] = a > (4'sb1010 | 4'sd0);
  assign y[1] = (a | 4'sd0) > 4'sb1010;
endmodule

module issue_013_tb;
  reg signed [3:0] a;
  wire [1:0] y;
  issue_013 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [3:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 4'b0 );
    test_pattern(  1, ~4'b0 );
    test_pattern(  2, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern(  3, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern(  4, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern(  5, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern(  6, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern(  7, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern(  8, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern(  9, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 10, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 11, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 12, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 13, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 14, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 15, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 16, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 17, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 18, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 19, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 20, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 21, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 22, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 23, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 24, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 25, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 26, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 27, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 28, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 29, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 30, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
    test_pattern( 31, 160'h1527af755afcb15644ff66e7de3ec53231f20330 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #2		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #3		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #4		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #5		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #6		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #7		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #8		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #9		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #10		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #11		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #12		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #13		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #14		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #15		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #16		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #17		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #18		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #19		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #20		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #21		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #22		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #23		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #24		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #25		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #26		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #27		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #28		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #29		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #30		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Pattern #31		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {modelsim,xsim,yosim}.rtl	y	11	3
icarus.rtl	y	10	2

Report on issue_014:

This report is part of the following lists: all vivado

Synthesis of issue_014 using vivado failed!

	quartus	xst	yosys	xsim	modelsim	icarus	yosim
quartus	PASS	PASS	FAIL	74aaf9e4	74aaf9e4	74aaf9e4	74aaf9e4
xst	PASS	PASS	FAIL	74aaf9e4	74aaf9e4	74aaf9e4	74aaf9e4
yosys	FAIL	FAIL	PASS	74aaf9e4	74aaf9e4	74aaf9e4	74aaf9e4
rtl	PASS	PASS	PASS	74aaf9e4	74aaf9e4	74aaf9e4	74aaf9e4

module issue_014(a, b, y);
  // http://forums.xilinx.com/t5/Synthesis/Vivado-GDpGen-implementDivMod-DFNode-bool-Assertion-TBD-failed/td-p/401721
  input [1:0] a;
  input [2:0] b;
  output [3:0] y;
  // Vivado 2013.4 asserts on this test case:
  // vivado: /.../gencore/dp/GDpGenDivMod.cc:324: void GDpGen::implementDivMod(DFNode*, bool): Assertion `TBD' failed.
  assign y = $signed(a / b);
endmodule

module issue_014_tb;
  reg [1:0] a;
  reg [2:0] b;
  wire [3:0] y;
  issue_014 uut (a, b, y);
  task test_pattern;
    input [5:0] index;
    input [4:0] pattern;
    begin
      { a, b } <= pattern; #1;
      $display("++RPT++ %d %b %b %b", index, a, b, y);
    end
  endtask
  initial begin
    test_pattern(  0, 5'b0 );
    test_pattern(  1, ~5'b0 );
    test_pattern(  2, 5'b00000 );
    test_pattern(  3, 5'b01000 );
    test_pattern(  4, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern(  5, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern(  6, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern(  7, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern(  8, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern(  9, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 10, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 11, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 12, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 13, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 14, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 15, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 16, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 17, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 18, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 19, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 20, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 21, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 22, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 23, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 24, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 25, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 26, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 27, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 28, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 29, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 30, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 31, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 32, 160'h6f961d821818c9209b501a78325c5a5278302991 );
    test_pattern( 33, 160'h6f961d821818c9209b501a78325c5a5278302991 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	00	0
input signals	b	000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	0011	3
{icarus,modelsim,xsim,yosim}.rtl	y	xxxx	X
{icarus,modelsim,xsim,yosim}.yosys	y	1111	15

Pattern #2		binary	decimal
input signals	a	00	0
input signals	b	000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	0011	3
{icarus,modelsim,xsim,yosim}.rtl	y	xxxx	X
{icarus,modelsim,xsim,yosim}.yosys	y	1111	15

Pattern #3		binary	decimal
input signals	a	01	1
input signals	b	000	0
{icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst	y	0011	3
{icarus,modelsim,xsim,yosim}.rtl	y	xxxx	X
{icarus,modelsim,xsim,yosim}.yosys	y	1111	15

Report on issue_015:

This report is part of the following lists: all vivado

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	FAIL	FAIL	2c0b5c56	2c0b5c56	2c0b5c56	2c0b5c56
quartus	FAIL	PASS	FAIL	FAIL	eef939f3	eef939f3	eef939f3	eef939f3
xst	FAIL	FAIL	PASS	FAIL	eef939f3	eef939f3	eef939f3	eef939f3
yosys	FAIL	FAIL	FAIL	PASS	eef939f3	eef939f3	eef939f3	eef939f3
rtl	FAIL	PASS	PASS	PASS	eef939f3	eef939f3	eef939f3	eef939f3

module issue_015(a, y);
  // http://forums.xilinx.com/t5/Synthesis/Vivado-bug-in-undef-handling-for-relational-operators/td-p/403469
  input [3:0] a;
  output [23:0] y;

  wire [3:0] y0;
  wire [3:0] y1;
  wire [3:0] y2;
  wire [3:0] y3;
  wire [3:0] y4;
  wire [3:0] y5;

  assign y = {y0,y1,y2,y3,y4,y5};

  // All this cases should evaluate to 4'b000x (regardless of the value of 'a').
  // But Vivado 2013.4 returns 4'b0010 instead.
  assign y0 = a >  4'bx;
  assign y1 = a >= 4'bx;
  assign y2 = a <  4'bx;
  assign y3 = a <= 4'bx;
  assign y4 = a == 4'bx;
  assign y5 = a != 4'bx;
endmodule

module issue_015_tb;
  reg [3:0] a;
  wire [23:0] y;
  issue_015 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [3:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 4'b0 );
    test_pattern(  1, ~4'b0 );
    test_pattern(  2, 4'b0000 );
    test_pattern(  3, 4'b1101 );
    test_pattern(  4, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern(  5, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern(  6, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern(  7, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern(  8, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern(  9, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 10, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 11, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 12, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 13, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 14, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 15, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 16, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 17, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 18, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 19, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 20, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 21, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 22, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 23, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 24, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 25, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 26, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 27, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 28, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 29, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 30, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 31, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 32, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
    test_pattern( 33, 160'hee9f419a2e9a83aa5d577b3e619cf51377948946 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #1		binary	decimal
input signals	a	1111	15
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #2		binary	decimal
input signals	a	0000	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #3		binary	decimal
input signals	a	1101	13
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #4		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #5		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #6		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #7		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #8		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #9		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #10		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #11		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #12		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #13		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #14		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #15		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #16		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #17		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #18		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #19		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #20		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #21		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #22		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #23		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #24		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #25		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #26		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #27		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #28		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #29		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #30		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #31		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #32		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Pattern #33		binary	decimal
input signals	a	0110	6
{icarus,modelsim,xsim,yosim}.quartus	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0000	0
	y5	0000	0
{icarus,modelsim,xsim,yosim}.rtl	y0	000x	X
	y1	000x	X
	y2	000x	X
	y3	000x	X
	y4	000x	X
	y5	000x	X
{icarus,modelsim,xsim,yosim}.vivado	y0	0010	2
	y1	0010	2
	y2	0010	2
	y3	0010	2
	y4	0010	2
	y5	0010	2
{icarus,modelsim,xsim,yosim}.xst	y0	0000	0
	y1	0000	0
	y2	0000	0
	y3	0000	0
	y4	0001	1
	y5	0000	0
{icarus,modelsim,xsim,yosim}.yosys	y0	0001	1
	y1	0001	1
	y2	0001	1
	y3	0001	1
	y4	000x	X
	y5	000x	X

Report on issue_016:

This report is part of the following lists: all quartus

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	FAIL	PASS	PASS	478e76ec	478e76ec	478e76ec	478e76ec
quartus	FAIL	PASS	FAIL	FAIL	5253e007	5253e007	5253e007	5253e007
xst	PASS	FAIL	PASS	PASS	478e76ec	478e76ec	478e76ec	478e76ec
yosys	PASS	FAIL	PASS	PASS	478e76ec	478e76ec	478e76ec	478e76ec
rtl	PASS	FAIL	PASS	PASS	478e76ec	478e76ec	478e76ec	478e76ec

module issue_016(a, y);
  input [1:0] a;
  output [7:0] y;

  wire [3:0] y0;
  wire [3:0] y1;
  assign y = {y0,y1};

  // this should return zero (see table 5-5 of IEEE Std 1364-2005)
  // but it returns different values in quartus 13.1
  assign y0  = -4'd1 ** -4'sd2;
  assign y1  = -4'd1 ** -4'sd3;
endmodule

module issue_016_tb;
  reg [1:0] a;
  wire [7:0] y;
  issue_016 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [1:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 2'b0 );
    test_pattern(  1, ~2'b0 );
    test_pattern(  2, 2'b00 );
    test_pattern(  3, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern(  4, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern(  5, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern(  6, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern(  7, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern(  8, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern(  9, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 10, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 11, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 12, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 13, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 14, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 15, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 16, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 17, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 18, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 19, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 20, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 21, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 22, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 23, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 24, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 25, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 26, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 27, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 28, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 29, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 30, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 31, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
    test_pattern( 32, 160'haa350e84434c8f8e35d39df3966f6f25d1291ddc );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #1		binary	decimal
input signals	a	11	3
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #2		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #3		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #4		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #5		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #6		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #7		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #8		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #9		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #10		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #11		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #12		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #13		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #14		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #15		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #16		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #17		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #18		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #19		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #20		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #21		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #22		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #23		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #24		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #25		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #26		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #27		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #28		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #29		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #30		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #31		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Pattern #32		binary	decimal
input signals	a	00	0
{icarus,modelsim,xsim,yosim}.quartus	y0	0001	1
{icarus,modelsim,xsim,yosim}.quartus	y1	1111	15
{icarus,modelsim,xsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	0000	0
	y1	0000	0

Report on issue_017:

This report is part of the following lists: all xsim

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	PASS	467b2f18	467b2f18	467b2f18	467b2f18
quartus	PASS	PASS	PASS	PASS	467b2f18	467b2f18	467b2f18	467b2f18
xst	PASS	PASS	PASS	PASS	467b2f18	467b2f18	467b2f18	467b2f18
yosys	PASS	PASS	PASS	PASS	467b2f18	467b2f18	467b2f18	467b2f18
rtl	PASS	PASS	PASS	PASS	37537009	467b2f18	467b2f18	467b2f18

module issue_017(ctrl, y);
  input [1:0] ctrl;
  output [5:0] y;

  wire [2:0] y0;
  wire [2:0] y1;
  assign y = {y0,y1};

  // this should return 3'b001 but isim 14.7 returns 3'b000
  assign y0 = &($signed(2'b11));
  assign y1 = &($unsigned(2'b11));
endmodule

module issue_017_tb;
  reg [1:0] ctrl;
  wire [5:0] y;
  issue_017 uut (ctrl, y);
  task test_pattern;
    input [5:0] index;
    input [1:0] pattern;
    begin
      { ctrl } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, ctrl, y);
    end
  endtask
  initial begin
    test_pattern(  0, 2'b0 );
    test_pattern(  1, ~2'b0 );
    test_pattern(  2, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern(  3, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern(  4, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern(  5, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern(  6, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern(  7, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern(  8, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern(  9, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 10, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 11, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 12, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 13, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 14, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 15, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 16, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 17, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 18, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 19, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 20, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 21, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 22, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 23, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 24, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 25, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 26, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 27, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 28, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 29, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 30, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
    test_pattern( 31, 160'h35e94f183a0e07a41dcdb1203b4f1dc2022377b3 );
  end
endmodule

Pattern #0		binary	decimal
input signals	ctrl	00	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #1		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #2		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #3		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #4		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #5		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #6		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #7		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #8		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #9		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #10		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #11		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #12		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #13		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #14		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #15		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #16		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #17		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #18		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #19		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #20		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #21		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #22		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #23		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #24		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #25		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #26		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #27		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #28		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #29		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #30		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Pattern #31		binary	decimal
input signals	ctrl	11	3
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y0	001	1
	y1	001	1
xsim.rtl	y0	000	0
xsim.rtl	y1	000	0

Report on issue_018:

This report is part of the following lists: all noerror

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
quartus	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
xst	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
yosys	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
rtl	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1

module issue_018(a, y);
  input [3:0] a;
  output [3:0] y;

  // in a localparam, like a wire, the width of the param should be
  // use to extend the expression. so this should be equal to ~4'b0001.
  // but isim 14.1 does not do this correctly.
  localparam [3:0] p = ~1'b1;
  assign y = p;
endmodule

module issue_018_tb;
  reg [3:0] a;
  wire [3:0] y;
  issue_018 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [3:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 4'b0 );
    test_pattern(  1, ~4'b0 );
    test_pattern(  2, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern(  3, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern(  4, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern(  5, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern(  6, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern(  7, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern(  8, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern(  9, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 10, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 11, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 12, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 13, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 14, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 15, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 16, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 17, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 18, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 19, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 20, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 21, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 22, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 23, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 24, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 25, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 26, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 27, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 28, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 29, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 30, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
    test_pattern( 31, 160'hd31c3a6ec7acbd5c055b7012d54ce066d97864d4 );
  end
endmodule

Report on issue_019:

This report is part of the following lists: all xsim

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	PASS	36213476	dd4d6b25	dd4d6b25	dd4d6b25
quartus	PASS	PASS	PASS	PASS	36213476	dd4d6b25	dd4d6b25	dd4d6b25
xst	PASS	PASS	PASS	PASS	36213476	dd4d6b25	dd4d6b25	dd4d6b25
yosys	PASS	PASS	PASS	PASS	dd4d6b25	dd4d6b25	dd4d6b25	dd4d6b25
rtl	PASS	PASS	PASS	PASS	36213476	dd4d6b25	dd4d6b25	dd4d6b25

module issue_019(a, y);
  input [0:0] a;
  output [15:0] y;

  wire [7:0] y0;
  wire [7:0] y1;
  assign y = {y0,y1};

  // according to table 5-6 of IEEE Std 1364-2005, the following expressions
  // should return 8'bx, but instead with ISIM 14.7 and XSIM 2013.4 they return 8'b0 instead.
  assign y0  = 8'sd0 ** -8'sd1;
  assign y1  = 8'd 0 ** -8'sd1;
endmodule

module issue_019_tb;
  reg [0:0] a;
  wire [15:0] y;
  issue_019 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [0:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 1'b0 );
    test_pattern(  1, ~1'b0 );
    test_pattern(  2, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern(  3, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern(  4, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern(  5, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern(  6, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern(  7, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern(  8, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern(  9, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 10, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 11, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 12, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 13, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 14, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 15, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 16, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 17, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 18, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 19, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 20, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 21, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 22, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 23, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 24, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 25, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 26, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 27, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 28, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 29, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 30, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
    test_pattern( 31, 160'hfcb2f412ee134a067daea4121e131caffb5f475f );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	0	0
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #1		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #2		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #3		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #4		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #5		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #6		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #7		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #8		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #9		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #10		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #11		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #12		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #13		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #14		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #15		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #16		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #17		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #18		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #19		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #20		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #21		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #22		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #23		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #24		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #25		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #26		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #27		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #28		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #29		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #30		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Pattern #31		binary	decimal
input signals	a	1	1
{icarus,modelsim,xsim,yosim}.vivado, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.xst, {xsim}.rtl	y0	00000000	0
	y1	00000000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.yosys	y0	xxxxxxxx	X
	y1	xxxxxxxx	X

Report on issue_020:

This report is part of the following lists: all xsim

	vivado	quartus	xst	yosys	xsim	modelsim	icarus	yosim
vivado	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
quartus	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
xst	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
yosys	PASS	PASS	PASS	PASS	12ab37a1	12ab37a1	12ab37a1	12ab37a1
rtl	PASS	PASS	PASS	PASS	716dcabf	12ab37a1	12ab37a1	12ab37a1

module issue_020(a, y);
  input [3:0] a;
  output [3:0] y;

  // xsim 2013.4 fails to recognize this as a signed expression and returns 4'b0110 instead of 4'b1110.
  localparam [3:0] p15 = 3'sb100 >>> 2'b01;
  assign y = p15;
endmodule

module issue_020_tb;
  reg [3:0] a;
  wire [3:0] y;
  issue_020 uut (a, y);
  task test_pattern;
    input [5:0] index;
    input [3:0] pattern;
    begin
      { a } <= pattern; #1;
      $display("++RPT++ %d %b %b", index, a, y);
    end
  endtask
  initial begin
    test_pattern(  0, 4'b0 );
    test_pattern(  1, ~4'b0 );
    test_pattern(  2, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern(  3, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern(  4, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern(  5, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern(  6, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern(  7, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern(  8, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern(  9, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 10, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 11, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 12, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 13, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 14, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 15, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 16, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 17, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 18, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 19, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 20, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 21, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 22, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 23, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 24, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 25, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 26, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 27, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 28, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 29, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 30, 160'hb178e87646de4a710c7496b163171a17690cf632 );
    test_pattern( 31, 160'hb178e87646de4a710c7496b163171a17690cf632 );
  end
endmodule

Pattern #0		binary	decimal
input signals	a	0000	0
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #1		binary	decimal
input signals	a	1111	15
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #2		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #3		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #4		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #5		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #6		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #7		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #8		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #9		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #10		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #11		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #12		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #13		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #14		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #15		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #16		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #17		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #18		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #19		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #20		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #21		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #22		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #23		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #24		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #25		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #26		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #27		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #28		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #29		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #30		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

Pattern #31		binary	decimal
input signals	a	0010	2
{icarus,modelsim,yosim}.rtl, {icarus,modelsim,xsim,yosim}.quartus, {icarus,modelsim,xsim,yosim}.yosys, {icarus,modelsim,xsim,yosim}.xst, {icarus,modelsim,xsim,yosim}.vivado	y	1110	14
xsim.rtl	y	0110	6

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