PIC_T_DUMMY_VIQ Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
V
V
 
 
 
 
V
V
V
V
 
 
 
A
I
V
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
V
V
 
 
 
 
V
V
 
 
 
 
 
 
 
 
 
 
R
I
 
 
 
 
 
V
 
 
 
 
 
 
V
V
V
V
L
L
I
V
V
V
 
 
 
 
 
A
 
 
 
 
 
 
V
V
 
 
 
 
V
V
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
D
D
M
D
 
 
G
E
E
E
 
 
G
E
E
E
 
 
D
D
M
D
 
 
 
 
 
 

Mux driving JINCK0

Source F2B16
G_JPCLKT00 -
JPADDI0 -
S1_JINECK0 -
DLLDEL0 1

Mux driving JINCK1

Source F4B4
G_JPCLKT01 -
JPADDI1 -
S1_JINECK1 -
DLLDEL1 1

Mux driving S1_ECLKI0

Source F3B44 F4B44 F5B44
S1_JECLKBRG0 1 - -
S1_JECLKCIB0 - 1 -
S1_JPLLCLKOP0 1 1 -
S1_JPLLCLKOP1 - - 1
S1_JPLLCLKOS0 1 - 1
S1_JPLLCLKOS1 - 1 1
S1_JINECK0 1 1 1

Mux driving S1_ECLKI1

Source F3B45 F4B45 F5B45
S1_JECLKBRG1 1 - -
S1_JECLKCIB1 - 1 -
S1_JPLLCLKOP0 1 1 -
S1_JPLLCLKOP1 - - 1
S1_JPLLCLKOS0 1 - 1
S1_JPLLCLKOS1 - 1 1
S1_JINECK1 1 1 1

Configuration word TDLLDEL0.DEL_VAL

Default value: 7'b0000000

TDLLDEL0.DEL_VAL[0]F5B15
TDLLDEL0.DEL_VAL[1]F4B15
TDLLDEL0.DEL_VAL[2]F3B15
TDLLDEL0.DEL_VAL[3]F2B15
TDLLDEL0.DEL_VAL[4]F5B16
TDLLDEL0.DEL_VAL[5]F4B16
TDLLDEL0.DEL_VAL[6]F3B16

Configuration word TDLLDEL1.DEL_VAL

Default value: 7'b0000000

TDLLDEL1.DEL_VAL[0]F3B2
TDLLDEL1.DEL_VAL[1]F2B2
TDLLDEL1.DEL_VAL[2]F5B3
TDLLDEL1.DEL_VAL[3]F4B3
TDLLDEL1.DEL_VAL[4]F3B3
TDLLDEL1.DEL_VAL[5]F2B3
TDLLDEL1.DEL_VAL[6]F5B4

Configuration Setting BANK.DIFF_REF

Default value: OFF

Value F0B13
OFF 0
ON 1

Configuration Setting BANK.INRD

Default value: OFF

Value F1B13
OFF 0
ON 1

Configuration Setting BANK.LVDSO

Value F0B16 F0B19 F0B20 F1B16 F1B19 F1B20
OFF 0 1 1 0 1 1
ON 1 0 0 1 0 0

Configuration Setting BANK.VCCIO

Default value: NONE

Value F0B10 F0B11 F0B19 F0B20 F1B10 F1B11 F1B19 F1B20
NONE 0 0 0 0 0 0 0 0
1.2 1 1 1 1 1 1 1 1
1.5 1 0 1 1 0 1 1 1
1.8 1 0 1 1 0 0 1 1
2.5 0 0 1 1 0 0 1 1
3.3 0 0 1 1 0 0 1 1

Configuration Setting BANK.VREF

Default value: OFF

Value F1B14
OFF 0
ON 1

Configuration Setting TCLKDIV0.DIV

Value F2B43 F3B43 F5B43
2.0 1 0 0
3.5 0 1 0
4.0 0 0 1

Configuration Setting TCLKDIV0.GSR

Default value: ENABLED

Value F2B44
DISABLED 1
ENABLED 0

Configuration Setting TCLKDIV1.DIV

Value F2B46 F3B46 F5B46
2.0 0 1 0
3.5 1 0 0
4.0 0 0 1

Configuration Setting TCLKDIV1.GSR

Default value: ENABLED

Value F2B45
DISABLED 1
ENABLED 0

Configuration Setting TDLLDEL0.DEL_ADJ

Default value: PLUS

Value F5B17
MINUS 1
PLUS 0

Configuration Setting TDLLDEL1.DEL_ADJ

Default value: PLUS

Value F3B4
MINUS 1
PLUS 0

Configuration Setting TECLKSYNC0.MODE

Default value: NONE

Value F4B43
NONE -
ECLKSYNCA 1

Configuration Setting TECLKSYNC1.MODE

Default value: NONE

Value F4B46
NONE -
ECLKSYNCA 1

Fixed Connections

SourceSink
S1_JECLKO0_ECLKSYNC→ S1_CLKI0_CLKDIV
S1_JECLKO1_ECLKSYNC→ S1_CLKI1_CLKDIV
CLKO0_DLLDEL→ DLLDEL0
CLKO1_DLLDEL→ DLLDEL1
S1_ECLKI0→ S1_ECLKI0_ECLKSYNC
S1_ECLKI1→ S1_ECLKI1_ECLKSYNC
S1_JCDIV10_CLKDIV→ G_JTCDIV10
S1_JCDIV11_CLKDIV→ G_JTCDIV11
S1_JCDIVX0_CLKDIV→ G_JTCDIVX0
S1_JCDIVX1_CLKDIV→ G_JTCDIVX1
S1_JECLKO0_ECLKSYNC→ G_TECLK0
S1_JECLKO1_ECLKSYNC→ G_TECLK1
S1_JA0→ S1_JALIGNWD0_CLKDIV
S1_JA1→ S1_JALIGNWD1_CLKDIV
4300D_S1E13_JDQSDEL_DQSDLL→ JDQSDEL0_DLLDEL
9400D_S1E21_JDQSDEL_DQSDLL→ JDQSDEL0_DLLDEL
4300D_S1E13_JDQSDEL_DQSDLL→ JDQSDEL1_DLLDEL
9400D_S1E21_JDQSDEL_DQSDLL→ JDQSDEL1_DLLDEL
S1_JCLK2→ S1_JECLKCIB0
S1_JCLK3→ S1_JECLKCIB1
S1_ECLKI0_ECLKSYNC→ S1_JECLKO0_ECLKSYNC
S1_ECLKI1_ECLKSYNC→ S1_JECLKO1_ECLKSYNC
S1_JCDIVX0_CLKDIV→ S1_JF0
S1_JCDIV10_CLKDIV→ S1_JF1
S1_JCDIVX1_CLKDIV→ S1_JF2
S1_JCDIV11_CLKDIV→ S1_JF3
JINCK0→ S1_JINECK0
JINCK1→ S1_JINECK1
4300D_S1W14_JCLKOP_PLL→ S1_JPLLCLKOP0
9400D_S1W23_JCLKOP_PLL→ S1_JPLLCLKOP0
4300D_S1E15_JCLKOP_PLL→ S1_JPLLCLKOP1
9400D_S1E23_JCLKOP_PLL→ S1_JPLLCLKOP1
4300D_S1W14_JCLKOS_PLL→ S1_JPLLCLKOS0
9400D_S1W23_JCLKOS_PLL→ S1_JPLLCLKOS0
4300D_S1E15_JCLKOS_PLL→ S1_JPLLCLKOS1
9400D_S1E23_JCLKOS_PLL→ S1_JPLLCLKOS1
S1_JECLKO0_ECLKSYNC→ S1_JQ4
S1_JECLKO1_ECLKSYNC→ S1_JQ5
S1_JA2→ S1_JRST0_CLKDIV
S1_JA3→ S1_JRST1_CLKDIV
S1_JC5→ S1_JSTOP0_ECLKSYNC
S1_JD5→ S1_JSTOP1_ECLKSYNC