PIC_B0 Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
R
R
M
T
T
 
 
O
R
T
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T
 
 
 
T
T
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T
T
Q
 
 
 
T
T
 
 
 
 
T
T
 
 
 
T
O
O
 
 
 
 
O
O
 
 
 
 
O
O
 
 
 
T
O
O
R
R
M
R
O
O
 
 
 
O
O
O
 
 
V
V
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P
 
V
V
V
P
P
T
 
 
 
D
D
 
T
O
 
D
D
Q
O
L
 
O
O
R
S
C
 
O
O
 
V
T
V
D
D
L
V
V
V
D
D
C
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P
P
V
I
V
C
P
P
I
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V
P
P
G
 
C
C
P
P
 
L
 
C
S
S
S
C
S
C
S
S
L
C
G
O
 
 
 
E
O
O
 
 
L
C
O
M
 
 
E
M
L
L
 
 
 
L
O
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H
H
 
T
Q
I
H
H
G
 
T
C
D
D
M
O
L
 
D
D
I
 
R
T
D
T
G
L
C
C
D
T
T
O
V
O
C
C
S
C
R
T
C
C
L
V
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V
 
 
 
R
R
M
 
 
L
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C
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V
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Mux driving DIA_BIOLOGIC

Source F0B8
JDIA 1

Mux driving DIB_IOLOGIC

Source F0B20
JDIB 1

Mux driving DIC_BSIOLOGIC

Source F3B44
JDIC 1

Mux driving DID_IOLOGIC

Source F2B35
JDID 1

Mux driving ECLKA

Source F1B31
G_BECLK0 -
G_BECLK1 1

Mux driving ECLKC

Source F0B33
G_BECLK0 -
G_BECLK1 1

Mux driving JDIA

Source F0B8
JPADDIA_PIO -
INDDA_BIOLOGIC 1

Mux driving JDIB

Source F0B20
JPADDIB_PIO -
INDDB_IOLOGIC 1

Mux driving JDIC

Source F3B44
JPADDIC_PIO -
INDDC_BSIOLOGIC 1

Mux driving JDID

Source F2B35
JPADDID_PIO -
INDDD_IOLOGIC 1

Mux driving N1_JQ0

Source F0B8
JDIA 1

Mux driving N1_JQ1

Source F0B20
JDIB 1

Mux driving N1_JQ2

Source F3B44
JDIC 1

Mux driving N1_JQ3

Source F2B35
JDID 1

Configuration word IOLOGICA.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICA.DELAY.DEL_VALUE[0]F3B23
IOLOGICA.DELAY.DEL_VALUE[1]F2B23
IOLOGICA.DELAY.DEL_VALUE[2]F1B23
IOLOGICA.DELAY.DEL_VALUE[3]F1B24
IOLOGICA.DELAY.DEL_VALUE[4]F0B25

Configuration word IOLOGICB.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICB.DELAY.DEL_VALUE[0]F2B16
IOLOGICB.DELAY.DEL_VALUE[1]F3B16
IOLOGICB.DELAY.DEL_VALUE[2]F3B17
IOLOGICB.DELAY.DEL_VALUE[3]F2B17
IOLOGICB.DELAY.DEL_VALUE[4]F1B17

Configuration word IOLOGICC.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICC.DELAY.DEL_VALUE[0]F1B22
IOLOGICC.DELAY.DEL_VALUE[1]F3B22
IOLOGICC.DELAY.DEL_VALUE[2]F2B25
IOLOGICC.DELAY.DEL_VALUE[3]F3B26
IOLOGICC.DELAY.DEL_VALUE[4]F1B26

Configuration word IOLOGICD.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICD.DELAY.DEL_VALUE[0]F1B46
IOLOGICD.DELAY.DEL_VALUE[1]F3B42
IOLOGICD.DELAY.DEL_VALUE[2]F0B46
IOLOGICD.DELAY.DEL_VALUE[3]F1B42
IOLOGICD.DELAY.DEL_VALUE[4]F2B40

Configuration Setting IOLOGICA.CEIMUX

Default value: CEMUX

Value F2B27
CEMUX -
1 1

Configuration Setting IOLOGICA.CEOMUX

Default value: CEMUX

Value F1B29
CEMUX -
1 1

Configuration Setting IOLOGICA.CLKIMUX

Default value: 0

Value F1B32
0 -
CLK 1
INV 1

Configuration Setting IOLOGICA.CLKOMUX

Default value: 0

Value F3B27
0 -
CLK 1
INV 1

Configuration Setting IOLOGICA.FF.INREGMODE

Default value: FF

Value F0B26
FF -
LATCH 1

Configuration Setting IOLOGICA.FF.REGSET

Default value: RESET

Value F3B3
RESET -
SET 1

Configuration Setting IOLOGICA.GSR

Default value: ENABLED

Value F0B27
DISABLED 1
ENABLED -

Configuration Setting IOLOGICA.IDDR4.LVDS71

Default value: NONE

Value F2B33 F3B33
NONE - -
NO - 1
YES 1 -

Configuration Setting IOLOGICA.LSRIMUX

Default value: 0

Value F0B32
0 -
LSRMUX 1

Configuration Setting IOLOGICA.LSRMUX

Default value: LSR

Value F0B30
INV 1
LSR -

Configuration Setting IOLOGICA.LSROMUX

Default value: 0

Value F3B34
0 -
LSRMUX 1

Configuration Setting IOLOGICA.MODE

Default value: IDDR4

Value F1B33 F3B2
NONE - -
IDDR_ODDR - 1
IREG_OREG - -
IDDR2 1 -
IDDR4 - -

Configuration Setting IOLOGICA.OUTREG.OUTREGMODE

Default value: FF

Value F2B32
FF -
LATCH 1

Configuration Setting IOLOGICA.OUTREG.REGSET

Default value: RESET

Value F2B2
RESET -
SET 1

Configuration Setting IOLOGICA.SRMODE

Default value: ASYNC

Value F0B29
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICA.TSMUX

Default value: TS

Value F3B10
INV 1
TS -

Configuration Setting IOLOGICA.TSREG.OUTREGMODE

Default value: FF

Value F2B34
FF -
LATCH 1

Configuration Setting IOLOGICA.TSREG.REGSET

Default value: RESET

Value F1B2
RESET -
SET 1

Configuration Setting IOLOGICB.CEIMUX

Default value: CEMUX

Value F2B39
CEMUX -
1 1

Configuration Setting IOLOGICB.CEOMUX

Default value: CEMUX

Value F1B41
CEMUX -
1 1

Configuration Setting IOLOGICB.CLKIMUX

Default value: 0

Value F1B44
0 -
CLK 1
INV 1

Configuration Setting IOLOGICB.CLKOMUX

Default value: 0

Value F3B39
0 -
CLK 1
INV 1

Configuration Setting IOLOGICB.FF.INREGMODE

Default value: FF

Value F0B38
FF -
LATCH 1

Configuration Setting IOLOGICB.FF.REGSET

Default value: RESET

Value F3B14
RESET -
SET 1

Configuration Setting IOLOGICB.GSR

Default value: ENABLED

Value F0B39
DISABLED 1
ENABLED -

Configuration Setting IOLOGICB.LSRIMUX

Default value: 0

Value F0B44
0 -
LSRMUX 1

Configuration Setting IOLOGICB.LSRMUX

Default value: LSR

Value F0B42
INV 1
LSR -

Configuration Setting IOLOGICB.LSROMUX

Default value: 0

Value F3B46
0 -
LSRMUX 1

Configuration Setting IOLOGICB.MODE

Default value: IREG_OREG

Value F2B14
NONE -
IDDR_ODDR 1
IREG_OREG -

Configuration Setting IOLOGICB.OUTREG.OUTREGMODE

Default value: FF

Value F2B44
FF -
LATCH 1

Configuration Setting IOLOGICB.OUTREG.REGSET

Default value: RESET

Value F1B14
RESET -
SET 1

Configuration Setting IOLOGICB.SRMODE

Default value: ASYNC

Value F0B41
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICB.TSMUX

Default value: TS

Value F2B22
INV 1
TS -

Configuration Setting IOLOGICB.TSREG.OUTREGMODE

Default value: FF

Value F2B46
FF -
LATCH 1

Configuration Setting IOLOGICB.TSREG.REGSET

Default value: RESET

Value F0B14
RESET -
SET 1

Configuration Setting IOLOGICC.CEIMUX

Default value: CEMUX

Value F3B28
CEMUX -
1 1

Configuration Setting IOLOGICC.CEOMUX

Default value: CEMUX

Value F3B29
CEMUX -
1 1

Configuration Setting IOLOGICC.CLKIMUX

Default value: 0

Value F0B45
0 -
CLK 1
INV 1

Configuration Setting IOLOGICC.CLKOMUX

Default value: 0

Value F0B24
0 -
CLK 1
INV 1

Configuration Setting IOLOGICC.FF.INREGMODE

Default value: FF

Value F1B25
FF -
LATCH 1

Configuration Setting IOLOGICC.FF.REGSET

Default value: RESET

Value F2B42
RESET -
SET 1

Configuration Setting IOLOGICC.GSR

Default value: ENABLED

Value F0B36
DISABLED 1
ENABLED -

Configuration Setting IOLOGICC.LSRIMUX

Default value: 0

Value F1B34
0 -
LSRMUX 1

Configuration Setting IOLOGICC.LSRMUX

Default value: LSR

Value F1B28
INV 1
LSR -

Configuration Setting IOLOGICC.LSROMUX

Default value: 0

Value F2B20
0 -
LSRMUX 1

Configuration Setting IOLOGICC.MODE

Default value: IREG_OREG

Value F3B32 F3B43
NONE - -
IDDR_ODDR - 1
IREG_OREG - -
IDDR2 1 -

Configuration Setting IOLOGICC.OUTREG.OUTREGMODE

Default value: FF

Value F2B31
FF -
LATCH 1

Configuration Setting IOLOGICC.OUTREG.REGSET

Default value: RESET

Value F2B41
RESET -
SET 1

Configuration Setting IOLOGICC.SRMODE

Default value: ASYNC

Value F2B29
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICC.TSMUX

Default value: TS

Value F3B38
INV 1
TS -

Configuration Setting IOLOGICC.TSREG.OUTREGMODE

Default value: FF

Value F1B20
FF -
LATCH 1

Configuration Setting IOLOGICC.TSREG.REGSET

Default value: RESET

Value F2B38
RESET -
SET 1

Configuration Setting IOLOGICD.CEIMUX

Default value: CEMUX

Value F1B30
CEMUX -
1 1

Configuration Setting IOLOGICD.CEOMUX

Default value: CEMUX

Value F3B25
CEMUX -
1 1

Configuration Setting IOLOGICD.CLKIMUX

Default value: 0

Value F3B36
0 -
CLK 1
INV 1

Configuration Setting IOLOGICD.CLKOMUX

Default value: 0

Value F2B21
0 -
CLK 1
INV 1

Configuration Setting IOLOGICD.FF.INREGMODE

Default value: FF

Value F3B35
FF -
LATCH 1

Configuration Setting IOLOGICD.FF.REGSET

Default value: RESET

Value F1B43
RESET -
SET 1

Configuration Setting IOLOGICD.GSR

Default value: ENABLED

Value F2B30
DISABLED 1
ENABLED -

Configuration Setting IOLOGICD.LSRIMUX

Default value: 0

Value F2B37
0 -
LSRMUX 1

Configuration Setting IOLOGICD.LSRMUX

Default value: LSR

Value F0B23
INV 1
LSR -

Configuration Setting IOLOGICD.LSROMUX

Default value: 0

Value F1B39
0 -
LSRMUX 1

Configuration Setting IOLOGICD.MODE

Default value: IREG_OREG

Value F0B37
NONE -
IDDR_ODDR 1
IREG_OREG -

Configuration Setting IOLOGICD.OUTREG.OUTREGMODE

Default value: FF

Value F3B30
FF -
LATCH 1

Configuration Setting IOLOGICD.OUTREG.REGSET

Default value: RESET

Value F0B21
RESET -
SET 1

Configuration Setting IOLOGICD.SRMODE

Default value: ASYNC

Value F1B21
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICD.TSMUX

Default value: TS

Value F1B45
INV 1
TS -

Configuration Setting IOLOGICD.TSREG.OUTREGMODE

Default value: FF

Value F3B31
FF -
LATCH 1

Configuration Setting IOLOGICD.TSREG.REGSET

Default value: RESET

Value F2B43
RESET -
SET 1

Configuration Setting PIOA.BASE_TYPE

Default value: NONE

Value F0B6 F3B13 F4B2 F4B6 F4B8 F4B10 F4B12 F4B14 F4B18 F4B20 F4B22 F4B24 F4B36 F4B38 F4B40 F5B6 F5B10 F5B12 F5B14 F5B18 F5B20 F5B22 F5B24 F5B40
NONE - - - - - - - - - - - - - - - - - - - - - - - -
BIDIR_MIPI 1 1 1 - - 1 1 1 1 1 1 1 - - 1 1 1 1 1 1 1 1 1 -
INPUT_MIPI - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
OUTPUT_MIPI 1 - - - - - - - - - - 1 - - - - - - - - - - 1 -
BIDIR_LVCMOS12 1 - - 1 1 1 - 1 1 - 1 - 1 - 1 - - - - - - - - -
INPUT_LVCMOS12 - - - 1 1 - 1 - - 1 - - 1 - 1 - - - - - - - - -
OUTPUT_LVCMOS12 1 - - - - 1 - 1 1 - 1 - 1 - - - - - - - - - - -
BIDIR_LVCMOS15 1 - - 1 1 1 1 1 - - 1 - 1 - 1 - - - - - - - - -
INPUT_LVCMOS15 - - - 1 1 - 1 - - 1 - - 1 - 1 - - - - - - - - -
OUTPUT_LVCMOS15 1 - - - - 1 1 1 - - 1 - 1 - - - - - - - - - - -
BIDIR_LVCMOS18 1 - - - - 1 - - 1 1 1 - 1 - 1 - - - - - - - - -
BIDIR_LVCMOS18D 1 1 1 - - 1 - - 1 1 1 1 1 - 1 1 1 - - 1 1 1 1 1
INPUT_LVCMOS18 - - - - - - 1 - - 1 - - 1 - 1 - - - - - - - - -
INPUT_LVCMOS18D - - 1 - - - 1 - - 1 - 1 1 - 1 1 - 1 - - 1 - 1 1
OUTPUT_LVCMOS18 1 - - - - 1 - - 1 1 1 - 1 - - - - - - - - - - -
OUTPUT_LVCMOS18D 1 1 - 1 - 1 - - 1 1 1 1 1 - - 1 1 - - 1 1 1 1 -
BIDIR_LVCMOS25 1 - - - - - - - - - - - - 1 1 - - - - - - - - -
BIDIR_LVCMOS25D 1 1 1 - - - - - - - - 1 - - 1 1 - - - - - - 1 1
INPUT_BLVDS25 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
INPUT_LVCMOS25 - - - - - - 1 - - 1 - - - 1 1 - - - - - - - - -
INPUT_LVCMOS25D - - 1 - - - 1 - - 1 - 1 - - 1 1 - 1 - - 1 - 1 1
INPUT_LVDS25 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
INPUT_MLVDS25 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
OUTPUT_BLVDS25E 1 1 - 1 - 1 1 1 1 1 1 1 - - - 1 1 1 1 1 1 1 1 -
OUTPUT_LVCMOS25 1 - - - - - - - - - - - - - - - - - - - - - - -
OUTPUT_LVCMOS25D 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
OUTPUT_LVDS25E 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
OUTPUT_MLVDS25E 1 1 - 1 - 1 1 1 1 1 1 1 - - - 1 1 1 1 1 1 1 1 -
BIDIR_LVCMOS33 1 - - - - - - - - - - - - 1 1 - - - - - - - - -
BIDIR_LVCMOS33D 1 1 1 - - - - - - - - 1 - - 1 1 - - - - - - 1 1
BIDIR_LVTTL33 1 - - - - - - - - - - - - 1 1 - - - - - - - - -
BIDIR_LVTTL33D 1 1 1 - - - - - - - - 1 - - 1 1 - - - - - - 1 1
INPUT_LVCMOS33 - - - - - - 1 - - 1 - - - 1 1 - - - - - - - - -
INPUT_LVCMOS33D - - 1 - - - 1 - - 1 - 1 - - 1 1 - 1 - - 1 - 1 1
INPUT_LVPECL33 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
INPUT_LVTTL33 - - - - - - 1 - - 1 - - - 1 1 - - - - - - - - -
INPUT_LVTTL33D - - 1 - - - 1 - - 1 - 1 - - 1 1 - 1 - - 1 - 1 1
OUTPUT_LVCMOS33 1 - - - - - - - - - - - - - - - - - - - - - - -
OUTPUT_LVCMOS33D 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
OUTPUT_LVPECL33E 1 1 - 1 - 1 1 1 1 1 1 1 - - - 1 1 1 1 1 1 1 1 -
OUTPUT_LVTTL33 1 - - - - - - - - - - - - - - - - - - - - - - -
OUTPUT_LVTTL33D 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
BIDIR_LVCMOS10R25 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS10R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
BIDIR_LVCMOS10R33 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS10R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
BIDIR_LVCMOS12R25 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS12R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
BIDIR_LVCMOS12R33 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS12R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS15R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS15R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS18R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS18R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS25R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -

Configuration Setting PIOA.CLAMP

Default value: OFF

Value F4B40
OFF 0
ON 1

Configuration Setting PIOA.DATAMUX_ODDR

Default value: PADDO

Value F2B3
IOLDO 1
PADDO -

Configuration Setting PIOA.DATAMUX_OREG

Default value: PADDO

Value F1B7
IOLDO 1
PADDO -

Configuration Setting PIOA.DIFFRESISTOR

Default value: OFF

Value F4B38 F5B38
OFF 0 0
100 1 1

Configuration Setting PIOA.DRIVE

Default value: 8

Value F4B10 F4B12 F4B14 F4B18 F4B20 F4B22 F4B36
2 0 0 0 0 0 0 1
4 1 1 0 1 1 0 0
6 1 0 1 1 0 1 1
8 0 0 0 0 0 0 0
12 1 0 0 1 0 0 0
16 1 1 1 1 1 1 0

Configuration Setting PIOA.HYSTERESIS

Default value: SMALL

Value F4B34
LARGE 1
SMALL 0

Configuration Setting PIOA.OPENDRAIN

Default value: OFF

Value F4B10 F4B12 F4B14 F4B20 F4B24
OFF 0 0 0 0 0
ON 1 1 1 1 1

Configuration Setting PIOA.PGMUX

Default value: INBUF

Value F4B26
INBUF -
PGBUF 1

Configuration Setting PIOA.PULLMODE

Default value: DOWN

Value F4B16 F4B24
NONE 0 1
DOWN 0 0
KEEPER 1 0
UP 1 1
I3C 0 0

Configuration Setting PIOA.SLEWRATE

Default value: SLOW

Value F4B28
FAST 1
SLOW 0

Configuration Setting PIOA.TRIMUX_TSREG

Default value: PADDT

Value F0B7
IOLTO 1
PADDT -

Configuration Setting PIOB.BASE_TYPE

Default value: NONE

Value F0B18 F5B2 F5B6 F5B8 F5B10 F5B12 F5B14 F5B18 F5B20 F5B22 F5B24 F5B36 F5B38 F5B40
NONE - - - - - - - - - - - - - -
BIDIR_LVCMOS12 1 - 1 1 1 - 1 1 - 1 - 1 - 1
INPUT_LVCMOS12 - - 1 1 - 1 - - 1 - - 1 - 1
OUTPUT_LVCMOS12 1 - - - 1 - 1 1 - 1 - 1 - -
BIDIR_LVCMOS15 1 - 1 1 1 1 1 - - 1 - 1 - 1
INPUT_LVCMOS15 - - 1 1 - 1 - - 1 - - 1 - 1
OUTPUT_LVCMOS15 1 - - - 1 1 1 - - 1 - 1 - -
BIDIR_LVCMOS18 1 - - - 1 - - 1 1 1 - 1 - 1
INPUT_LVCMOS18 - - - - - 1 - - 1 - - 1 - 1
OUTPUT_LVCMOS18 1 - - - 1 - - 1 1 1 - 1 - -
BIDIR_LVCMOS25 1 - - - - - - - - - - - 1 1
INPUT_LVCMOS25 - - - - - 1 - - 1 - - - 1 1
OUTPUT_LVCMOS25 1 - - - - - - - - - - - - -
BIDIR_LVCMOS33 1 - - - - - - - - - - - 1 1
BIDIR_LVTTL33 1 - - - - - - - - - - - 1 1
INPUT_LVCMOS33 - - - - - 1 - - 1 - - - 1 1
INPUT_LVTTL33 - - - - - 1 - - 1 - - - 1 1
OUTPUT_LVCMOS33 1 - - - - - - - - - - - - -
OUTPUT_LVTTL33 1 - - - - - - - - - - - - -
BIDIR_LVCMOS10R25 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS10R25 - 1 1 - - 1 - - 1 - - - - 1
BIDIR_LVCMOS10R33 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS10R33 - 1 1 - - 1 - - 1 - - - - 1
BIDIR_LVCMOS12R25 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS12R25 - 1 1 - - 1 - - 1 - - - - 1
BIDIR_LVCMOS12R33 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS12R33 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS15R25 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS15R33 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS18R25 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS18R33 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS25R33 - 1 1 - - 1 - - 1 - - - - 1

Configuration Setting PIOB.CLAMP

Default value: OFF

Value F5B40
OFF 0
ON 1

Configuration Setting PIOB.DATAMUX_ODDR

Default value: PADDO

Value F3B15
IOLDO 1
PADDO -

Configuration Setting PIOB.DATAMUX_OREG

Default value: PADDO

Value F2B19
IOLDO 1
PADDO -

Configuration Setting PIOB.DRIVE

Default value: 8

Value F5B10 F5B12 F5B14 F5B18 F5B20 F5B22 F5B36
2 0 0 0 0 0 0 1
4 1 1 0 1 1 0 0
6 1 0 1 1 0 1 1
8 0 0 0 0 0 0 0
12 1 0 0 1 0 0 0
16 1 1 1 1 1 1 0

Configuration Setting PIOB.HYSTERESIS

Default value: SMALL

Value F5B34
LARGE 1
SMALL 0

Configuration Setting PIOB.OPENDRAIN

Default value: OFF

Value F5B10 F5B12 F5B14 F5B20 F5B24
OFF 0 0 0 0 0
ON 1 1 1 1 1

Configuration Setting PIOB.PGMUX

Default value: INBUF

Value F5B26
INBUF -
PGBUF 1

Configuration Setting PIOB.PULLMODE

Default value: DOWN

Value F5B16 F5B24
NONE 0 1
DOWN 0 0
KEEPER 1 0
UP 1 1
I3C 0 0

Configuration Setting PIOB.SLEWRATE

Default value: SLOW

Value F5B28
FAST 1
SLOW 0

Configuration Setting PIOB.TRIMUX_TSREG

Default value: PADDT

Value F1B19
IOLTO 1
PADDT -

Configuration Setting PIOC.BASE_TYPE

Default value: NONE

Value F2B36 F2B45 F4B3 F4B7 F4B9 F4B11 F4B13 F4B15 F4B19 F4B21 F4B23 F4B25 F4B37 F4B39 F4B41 F5B7 F5B11 F5B13 F5B15 F5B19 F5B21 F5B23 F5B25 F5B41
NONE - - - - - - - - - - - - - - - - - - - - - - - -
BIDIR_MIPI 1 1 1 - - 1 1 1 1 1 1 1 - - 1 1 1 1 1 1 1 1 1 -
INPUT_MIPI - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
OUTPUT_MIPI 1 - - - - - - - - - - 1 - - - - - - - - - - 1 -
BIDIR_LVCMOS12 1 - - 1 1 1 - 1 1 - 1 - 1 - 1 - - - - - - - - -
INPUT_LVCMOS12 - - - 1 1 - 1 - - 1 - - 1 - 1 - - - - - - - - -
OUTPUT_LVCMOS12 1 - - - - 1 - 1 1 - 1 - 1 - - - - - - - - - - -
BIDIR_LVCMOS15 1 - - 1 1 1 1 1 - - 1 - 1 - 1 - - - - - - - - -
INPUT_LVCMOS15 - - - 1 1 - 1 - - 1 - - 1 - 1 - - - - - - - - -
OUTPUT_LVCMOS15 1 - - - - 1 1 1 - - 1 - 1 - - - - - - - - - - -
BIDIR_LVCMOS18 1 - - - - 1 - - 1 1 1 - 1 - 1 - - - - - - - - -
BIDIR_LVCMOS18D 1 1 1 - - 1 - - 1 1 1 1 1 - 1 1 1 - - 1 1 1 1 1
INPUT_LVCMOS18 - - - - - - 1 - - 1 - - 1 - 1 - - - - - - - - -
INPUT_LVCMOS18D - - 1 - - - 1 - - 1 - 1 1 - 1 1 - 1 - - 1 - 1 1
OUTPUT_LVCMOS18 1 - - - - 1 - - 1 1 1 - 1 - - - - - - - - - - -
OUTPUT_LVCMOS18D 1 1 - 1 - 1 - - 1 1 1 1 1 - - 1 1 - - 1 1 1 1 -
BIDIR_LVCMOS25 1 - - - - - - - - - - - - 1 1 - - - - - - - - -
BIDIR_LVCMOS25D 1 1 1 - - - - - - - - 1 - - 1 1 - - - - - - 1 1
INPUT_BLVDS25 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
INPUT_LVCMOS25 - - - - - - 1 - - 1 - - - 1 1 - - - - - - - - -
INPUT_LVCMOS25D - - 1 - - - 1 - - 1 - 1 - - 1 1 - 1 - - 1 - 1 1
INPUT_LVDS25 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
INPUT_MLVDS25 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
OUTPUT_BLVDS25E 1 1 - 1 - 1 1 1 1 1 1 1 - - - 1 1 1 1 1 1 1 1 -
OUTPUT_LVCMOS25 1 - - - - - - - - - - - - - - - - - - - - - - -
OUTPUT_LVCMOS25D 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
OUTPUT_LVDS25E 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
OUTPUT_MLVDS25E 1 1 - 1 - 1 1 1 1 1 1 1 - - - 1 1 1 1 1 1 1 1 -
BIDIR_LVCMOS33 1 - - - - - - - - - - - - 1 1 - - - - - - - - -
BIDIR_LVCMOS33D 1 1 1 - - - - - - - - 1 - - 1 1 - - - - - - 1 1
BIDIR_LVTTL33 1 - - - - - - - - - - - - 1 1 - - - - - - - - -
BIDIR_LVTTL33D 1 1 1 - - - - - - - - 1 - - 1 1 - - - - - - 1 1
INPUT_LVCMOS33 - - - - - - 1 - - 1 - - - 1 1 - - - - - - - - -
INPUT_LVCMOS33D - - 1 - - - 1 - - 1 - 1 - - 1 1 - 1 - - 1 - 1 1
INPUT_LVPECL33 - - 1 - - - 1 - - 1 - 1 - - - 1 - 1 - - 1 - 1 -
INPUT_LVTTL33 - - - - - - 1 - - 1 - - - 1 1 - - - - - - - - -
INPUT_LVTTL33D - - 1 - - - 1 - - 1 - 1 - - 1 1 - 1 - - 1 - 1 1
OUTPUT_LVCMOS33 1 - - - - - - - - - - - - - - - - - - - - - - -
OUTPUT_LVCMOS33D 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
OUTPUT_LVPECL33E 1 1 - 1 - 1 1 1 1 1 1 1 - - - 1 1 1 1 1 1 1 1 -
OUTPUT_LVTTL33 1 - - - - - - - - - - - - - - - - - - - - - - -
OUTPUT_LVTTL33D 1 1 - 1 - - - - - - - 1 - - - 1 - - - - - - 1 -
BIDIR_LVCMOS10R25 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS10R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
BIDIR_LVCMOS10R33 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS10R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
BIDIR_LVCMOS12R25 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS12R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
BIDIR_LVCMOS12R33 1 - 1 1 - - - - - 1 - 1 - - - - - - - - - - - -
INPUT_LVCMOS12R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS15R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS15R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS18R25 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS18R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -
INPUT_LVCMOS25R33 - - 1 1 - - 1 - - 1 - - - - 1 - - - - - - - - -

Configuration Setting PIOC.CLAMP

Default value: OFF

Value F4B41
OFF 0
ON 1

Configuration Setting PIOC.DATAMUX_ODDR

Default value: PADDO

Value F3B40
IOLDO 1
PADDO -

Configuration Setting PIOC.DATAMUX_OREG

Default value: PADDO

Value F1B40
IOLDO 1
PADDO -

Configuration Setting PIOC.DIFFRESISTOR

Default value: OFF

Value F4B39 F5B39
OFF 0 0
100 1 1

Configuration Setting PIOC.DRIVE

Default value: 8

Value F4B11 F4B13 F4B15 F4B19 F4B21 F4B23 F4B37
2 0 0 0 0 0 0 1
4 1 1 0 1 1 0 0
6 1 0 1 1 0 1 1
8 0 0 0 0 0 0 0
12 1 0 0 1 0 0 0
16 1 1 1 1 1 1 0

Configuration Setting PIOC.HYSTERESIS

Default value: SMALL

Value F4B35
LARGE 1
SMALL 0

Configuration Setting PIOC.OPENDRAIN

Default value: OFF

Value F4B11 F4B13 F4B15 F4B21 F4B25
OFF 0 0 0 0 0
ON 1 1 1 1 1

Configuration Setting PIOC.PGMUX

Default value: INBUF

Value F4B27
INBUF -
PGBUF 1

Configuration Setting PIOC.PULLMODE

Default value: DOWN

Value F4B17 F4B25
NONE 0 1
DOWN 0 0
KEEPER 1 0
UP 1 1
I3C 0 0

Configuration Setting PIOC.SLEWRATE

Default value: SLOW

Value F4B29
FAST 1
SLOW 0

Configuration Setting PIOC.TRIMUX_TSREG

Default value: PADDT

Value F0B40
IOLTO 1
PADDT -

Configuration Setting PIOD.BASE_TYPE

Default value: NONE

Value F1B35 F5B3 F5B7 F5B9 F5B11 F5B13 F5B15 F5B19 F5B21 F5B23 F5B25 F5B37 F5B39 F5B41
NONE - - - - - - - - - - - - - -
BIDIR_LVCMOS12 1 - 1 1 1 - 1 1 - 1 - 1 - 1
INPUT_LVCMOS12 - - 1 1 - 1 - - 1 - - 1 - 1
OUTPUT_LVCMOS12 1 - - - 1 - 1 1 - 1 - 1 - -
BIDIR_LVCMOS15 1 - 1 1 1 1 1 - - 1 - 1 - 1
INPUT_LVCMOS15 - - 1 1 - 1 - - 1 - - 1 - 1
OUTPUT_LVCMOS15 1 - - - 1 1 1 - - 1 - 1 - -
BIDIR_LVCMOS18 1 - - - 1 - - 1 1 1 - 1 - 1
INPUT_LVCMOS18 - - - - - 1 - - 1 - - 1 - 1
OUTPUT_LVCMOS18 1 - - - 1 - - 1 1 1 - 1 - -
BIDIR_LVCMOS25 1 - - - - - - - - - - - 1 1
INPUT_LVCMOS25 - - - - - 1 - - 1 - - - 1 1
OUTPUT_LVCMOS25 1 - - - - - - - - - - - - -
BIDIR_LVCMOS33 1 - - - - - - - - - - - 1 1
BIDIR_LVTTL33 1 - - - - - - - - - - - 1 1
INPUT_LVCMOS33 - - - - - 1 - - 1 - - - 1 1
INPUT_LVTTL33 - - - - - 1 - - 1 - - - 1 1
OUTPUT_LVCMOS33 1 - - - - - - - - - - - - -
OUTPUT_LVTTL33 1 - - - - - - - - - - - - -
BIDIR_LVCMOS10R25 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS10R25 - 1 1 - - 1 - - 1 - - - - 1
BIDIR_LVCMOS10R33 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS10R33 - 1 1 - - 1 - - 1 - - - - 1
BIDIR_LVCMOS12R25 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS12R25 - 1 1 - - 1 - - 1 - - - - 1
BIDIR_LVCMOS12R33 1 1 1 - - - - - 1 - 1 - - -
INPUT_LVCMOS12R33 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS15R25 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS15R33 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS18R25 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS18R33 - 1 1 - - 1 - - 1 - - - - 1
INPUT_LVCMOS25R33 - 1 1 - - 1 - - 1 - - - - 1

Configuration Setting PIOD.CLAMP

Default value: OFF

Value F5B41
OFF 0
ON 1

Configuration Setting PIOD.DATAMUX_ODDR

Default value: PADDO

Value F1B37
IOLDO 1
PADDO -

Configuration Setting PIOD.DATAMUX_OREG

Default value: PADDO

Value F3B45
IOLDO 1
PADDO -

Configuration Setting PIOD.DRIVE

Default value: 8

Value F5B11 F5B13 F5B15 F5B19 F5B21 F5B23 F5B37
2 0 0 0 0 0 0 1
4 1 1 0 1 1 0 0
6 1 0 1 1 0 1 1
8 0 0 0 0 0 0 0
12 1 0 0 1 0 0 0
16 1 1 1 1 1 1 0

Configuration Setting PIOD.HYSTERESIS

Default value: SMALL

Value F5B35
LARGE 1
SMALL 0

Configuration Setting PIOD.OPENDRAIN

Default value: OFF

Value F5B11 F5B13 F5B15 F5B21 F5B25
OFF 0 0 0 0 0
ON 1 1 1 1 1

Configuration Setting PIOD.PGMUX

Default value: INBUF

Value F5B27
INBUF -
PGBUF 1

Configuration Setting PIOD.PULLMODE

Default value: DOWN

Value F5B17 F5B25
NONE 0 1
DOWN 0 0
KEEPER 1 0
UP 1 1
I3C 0 0

Configuration Setting PIOD.SLEWRATE

Default value: SLOW

Value F5B29
FAST 1
SLOW 0

Configuration Setting PIOD.TRIMUX_TSREG

Default value: PADDT

Value F3B41
IOLTO 1
PADDT -

Fixed Connections

SourceSink
ECLKA→ ECLKA_BIOLOGIC
ECLKC→ ECLKC_BSIOLOGIC
G_INRD→ G_INRDA_PIO
G_INRD→ G_INRDB_PIO
G_INRD→ G_INRDC_PIO
G_INRD→ G_INRDD_PIO
G_PG→ G_PGA_PIO
G_PG→ G_PGB_PIO
G_PG→ G_PGC_PIO
G_PG→ G_PGD_PIO
IOLDOA_BIOLOGIC→ IOLDOA_PIO
IOLDOB_IOLOGIC→ IOLDOB_PIO
IOLDOC_BSIOLOGIC→ IOLDOC_PIO
IOLDOD_IOLOGIC→ IOLDOD_PIO
IOLTOA_BIOLOGIC→ IOLTOA_PIO
IOLTOB_IOLOGIC→ IOLTOB_PIO
IOLTOC_BSIOLOGIC→ IOLTOC_PIO
IOLTOD_IOLOGIC→ IOLTOD_PIO
N1_JCE0→ JCEA_BIOLOGIC
N1_JCE1→ JCEB_IOLOGIC
N1_JCE2→ JCEC_BSIOLOGIC
N1_JCE3→ JCED_IOLOGIC
N1_JCLK0→ JCLKA_BIOLOGIC
N1_JCLK1→ JCLKB_IOLOGIC
N1_JCLK2→ JCLKC_BSIOLOGIC
N1_JCLK3→ JCLKD_IOLOGIC
N1_JD2→ JDEL0A_BIOLOGIC
N1_JD4→ JDEL0C_BSIOLOGIC
N1_JD3→ JDEL1A_BIOLOGIC
N1_JA5→ JDEL1C_BSIOLOGIC
N1_JA4→ JDEL2A_BIOLOGIC
N1_JB5→ JDEL2C_BSIOLOGIC
N1_JB4→ JDEL3A_BIOLOGIC
N1_JC5→ JDEL3C_BSIOLOGIC
N1_JC4→ JDEL4A_BIOLOGIC
N1_JD5→ JDEL4C_BSIOLOGIC
JINA_BIOLOGIC→ N1_JF0
JRXD1A_BIOLOGIC→ N1_JF0
JRXDA5_BIOLOGIC→ N1_JF0
JINB_IOLOGIC→ N1_JF1
JRXD3A_BIOLOGIC→ N1_JF1
JRXDA7_BIOLOGIC→ N1_JF1
JINC_BSIOLOGIC→ N1_JF2
JIND_IOLOGIC→ N1_JF3
JIPA_BIOLOGIC→ N1_JF4
JRXD0A_BIOLOGIC→ N1_JF4
JRXDA4_BIOLOGIC→ N1_JF4
JIPB_IOLOGIC→ N1_JF5
JRXD2A_BIOLOGIC→ N1_JF5
JRXDA6_BIOLOGIC→ N1_JF5
JIPC_BSIOLOGIC→ N1_JF6
JIPD_IOLOGIC→ N1_JF7
N1_JLSR0→ JLSRA_BIOLOGIC
N1_JLSR1→ JLSRB_IOLOGIC
N1_JLSR2→ JLSRC_BSIOLOGIC
N1_JLSR3→ JLSRD_IOLOGIC
N1_JB0→ JONEGA_BIOLOGIC
N1_JB1→ JONEGB_IOLOGIC
N1_JB2→ JONEGC_BSIOLOGIC
N1_JB3→ JONEGD_IOLOGIC
N1_JA0→ JOPOSA_BIOLOGIC
N1_JA1→ JOPOSB_IOLOGIC
N1_JA2→ JOPOSC_BSIOLOGIC
N1_JA3→ JOPOSD_IOLOGIC
N1_JA0→ JPADDOA
N1_JA1→ JPADDOB
N1_JA2→ JPADDOC
N1_JA3→ JPADDOD
N1_JC0→ JPADDTA
N1_JC1→ JPADDTB
N1_JC2→ JPADDTC
N1_JC3→ JPADDTD
JRXD0C_BSIOLOGIC→ N1_JQ4
JRXDA0_BIOLOGIC→ N1_JQ4
JRXD1C_BSIOLOGIC→ N1_JQ5
JRXDA1_BIOLOGIC→ N1_JQ5
JRXD2C_BSIOLOGIC→ N1_JQ6
JRXDA2_BIOLOGIC→ N1_JQ6
JRXD3C_BSIOLOGIC→ N1_JQ7
JRXDA3_BIOLOGIC→ N1_JQ7
N1_JD0→ JSLIPA_BIOLOGIC
N1_JD1→ JSLIPC_BSIOLOGIC
N1_JC0→ JTSA_BIOLOGIC
N1_JC1→ JTSB_IOLOGIC
N1_JC2→ JTSC_BSIOLOGIC
N1_JC3→ JTSD_IOLOGIC
JPADDIA_PIO→ PADDIA_BIOLOGIC
JPADDIB_PIO→ PADDIB_IOLOGIC
JPADDIC_PIO→ PADDIC_BSIOLOGIC
JPADDID_PIO→ PADDID_IOLOGIC
JPADDOA→ PADDOA_PIO
JPADDOB→ PADDOB_PIO
JPADDOC→ PADDOC_PIO
JPADDOD→ PADDOD_PIO
JPADDTA→ PADDTA_PIO
JPADDTB→ PADDTB_PIO
JPADDTC→ PADDTC_PIO
JPADDTD→ PADDTD_PIO