GPLL_L0 Bit Data













W	C		F	C	D
E	C		F	E	D
	C	D	F	D	D
	C	D	E	D	D
	C	D		D	D
	K	D		D	D
	K	R	P	D	D
	K	R	W	D	D
	R	R		D	D
	R	U		R	D
	R	R	P	D	D
	R	R	E	D	D
	R	R		D	D
	R	R		D	D
	R	C	P	D	D
	P	C		D	D
	T	C		D	C
	T	P	P	E	C
	T	P	A	D	C
	T	P	A	D	C
	T	O	M	D	C
	T	O	M	D	C
	S	D	M	D	C
	S	D	M	D
	A	D	M	D	C
	B	D	M	E	C
	C	D	M	D	C
	D	D	M	D	C
	T	D	D	D	C
	T	R	D	D	C
	T	D	D	D	C
	T	D	P	D	M
	C	D	D	D	C
	C	D	D	E	C
		D	D	F	C
		D	P	F	C
		D	P	F	C
		V	P	S	C
		G	P	F	C
		G	P	F
		G	M	F	C
		I	M	E	C
		F	M	F	C
		T	S	F	C
		R		F	C
		P			C

Mux driving S1E1_CLKFB

Source	F2B26	F2B27	F2B28
S1E1_CLKINTFB	-	-	-
S1E1_JCLKFB0	-	-	-
S1E1_JCLKFB1	1	-	-
S1E1_JCLKFB2	-	1	-
G_TECLK1	1	1	-
S1E1_JCLKFB4	-	-	1
G_TECLK0	1	-	1

Mux driving S1E1_JCLKOP_PLL

Source	F3B18	F3B48
S1E1_CLKI_PLL	1	1

Mux driving S1E1_JCLKOS2_PLL

Source	F3B29	F3B50
S1E1_CLKI_PLL	1	1

Mux driving S1E1_JCLKOS3_PLL

Source	F3B26	F3B51
S1E1_CLKI_PLL	1	1

Mux driving S1E1_JCLKOS_PLL

Source	F3B22	F3B49
S1E1_CLKI_PLL	1	1

Mux driving S1E1_REFCLK0

Source	F2B22	F2B23	F2B24
S1E1_JREFCLK0	-	-	-
S1E1_JREFCLK1_0	1	-	-
S1E1_JREFCLK2_0	-	1	-
S1E1_JREFCLK3	1	1	-
S1E1_JREFCLK4	-	-	1
S1E1_JREFCLK5	1	-	1
S1E1_JREFCLK6	-	1	1
S1E1_JREFCLK7	1	1	1

Mux driving S1E1_REFCLK1

Source	F2B18	F2B19	F2B20
S1E1_JREFCLK0	-	-	-
S1E1_JREFCLK1_1	1	-	-
S1E1_JREFCLK2_1	-	1	-
S1E1_JREFCLK3	1	1	-
S1E1_JREFCLK4	-	-	1
S1E1_JREFCLK5	1	-	1
S1E1_JREFCLK6	-	1	1
S1E1_JREFCLK7	1	1	1

Configuration word CLKFB_DIV

Default value: 7'b0000000

CLKFB_DIV[0]	F2B42
CLKFB_DIV[1]	F2B43
CLKFB_DIV[2]	F2B44
CLKFB_DIV[3]	F2B45
CLKFB_DIV[4]	F2B46
CLKFB_DIV[5]	F2B47
CLKFB_DIV[6]	F2B48

Configuration word CLKI_DIV

Default value: 7'b0000000

CLKI_DIV[0]	F2B34
CLKI_DIV[1]	F2B35
CLKI_DIV[2]	F2B36
CLKI_DIV[3]	F2B37
CLKI_DIV[4]	F2B38
CLKI_DIV[5]	F2B39
CLKI_DIV[6]	F2B40

Configuration word CLKOP_CPHASE

Default value: 7'b0000000

CLKOP_CPHASE[0]	F5B28
CLKOP_CPHASE[1]	F5B29
CLKOP_CPHASE[2]	F5B30
CLKOP_CPHASE[3]	F5B31
CLKOP_CPHASE[4]	F5B32
CLKOP_CPHASE[5]	F5B33
CLKOP_CPHASE[6]	F5B34

Configuration word CLKOP_DIV

Default value: 7'b0000000

CLKOP_DIV[0]	F4B14
CLKOP_DIV[1]	F4B15
CLKOP_DIV[2]	F4B16
CLKOP_DIV[3]	F4B17
CLKOP_DIV[4]	F4B18
CLKOP_DIV[5]	F4B19
CLKOP_DIV[6]	F4B20

Configuration word CLKOP_FPHASE

Default value: 3'b000

CLKOP_FPHASE[0]	F4B46
CLKOP_FPHASE[1]	F4B47
CLKOP_FPHASE[2]	F4B48

Configuration word CLKOS2_CPHASE

Default value: 7'b0000000

CLKOS2_CPHASE[0]	F5B44
CLKOS2_CPHASE[1]	F5B45
CLKOS2_CPHASE[2]	F5B46
CLKOS2_CPHASE[3]	F5B47
CLKOS2_CPHASE[4]	F5B48
CLKOS2_CPHASE[5]	F5B49
CLKOS2_CPHASE[6]	F5B50

Configuration word CLKOS2_DIV

Default value: 7'b0000000

CLKOS2_DIV[0]	F4B30
CLKOS2_DIV[1]	F4B31
CLKOS2_DIV[2]	F4B32
CLKOS2_DIV[3]	F4B33
CLKOS2_DIV[4]	F4B34
CLKOS2_DIV[5]	F4B35
CLKOS2_DIV[6]	F4B36

Configuration word CLKOS2_FPHASE

Default value: 3'b000

CLKOS2_FPHASE[0]	F4B54
CLKOS2_FPHASE[1]	F4B55
CLKOS2_FPHASE[2]	F4B56

Configuration word CLKOS3_CPHASE

Default value: 7'b0000000

CLKOS3_CPHASE[0]	F5B52
CLKOS3_CPHASE[1]	F5B53
CLKOS3_CPHASE[2]	F5B54
CLKOS3_CPHASE[3]	F5B55
CLKOS3_CPHASE[4]	F5B56
CLKOS3_CPHASE[5]	F5B57
CLKOS3_CPHASE[6]	F4B12

Configuration word CLKOS3_DIV

Default value: 7'b0000000

CLKOS3_DIV[0]	F4B38
CLKOS3_DIV[1]	F4B39
CLKOS3_DIV[2]	F4B40
CLKOS3_DIV[3]	F4B41
CLKOS3_DIV[4]	F4B42
CLKOS3_DIV[5]	F4B43
CLKOS3_DIV[6]	F4B44

Configuration word CLKOS3_FPHASE

Default value: 3'b000

CLKOS3_FPHASE[0]	F3B12
CLKOS3_FPHASE[1]	F3B13
CLKOS3_FPHASE[2]	F3B14

Configuration word CLKOS_CPHASE

Default value: 7'b0000000

CLKOS_CPHASE[0]	F5B36
CLKOS_CPHASE[1]	F5B37
CLKOS_CPHASE[2]	F5B38
CLKOS_CPHASE[3]	F5B39
CLKOS_CPHASE[4]	F5B40
CLKOS_CPHASE[5]	F5B41
CLKOS_CPHASE[6]	F5B42

Configuration word CLKOS_DIV

Default value: 7'b0000000

CLKOS_DIV[0]	F4B22
CLKOS_DIV[1]	F4B23
CLKOS_DIV[2]	F4B24
CLKOS_DIV[3]	F4B25
CLKOS_DIV[4]	F4B26
CLKOS_DIV[5]	F4B27
CLKOS_DIV[6]	F4B28

Configuration word CLKOS_FPHASE

Default value: 3'b000

CLKOS_FPHASE[0]	F4B50
CLKOS_FPHASE[1]	F4B51
CLKOS_FPHASE[2]	F4B52

Configuration word FRACN_DIV

Default value: 16'b0000000000000000

FRACN_DIV[0]	F5B12
FRACN_DIV[1]	F5B13
FRACN_DIV[2]	F5B14
FRACN_DIV[3]	F5B15
FRACN_DIV[4]	F5B16
FRACN_DIV[5]	F5B17
FRACN_DIV[6]	F5B18
FRACN_DIV[7]	F5B19
FRACN_DIV[8]	F5B20
FRACN_DIV[9]	F5B21
FRACN_DIV[10]	F5B22
FRACN_DIV[11]	F5B23
FRACN_DIV[12]	F5B24
FRACN_DIV[13]	F5B25
FRACN_DIV[14]	F5B26
FRACN_DIV[15]	F5B27

Configuration word FRACN_ORDER

Default value: 2'b00

FRACN_ORDER[0]	F2B32
FRACN_ORDER[1]	F2B33

Configuration word FREQ_LOCK_ACCURACY

Default value: 2'b00

FREQ_LOCK_ACCURACY[0]	F3B30
FREQ_LOCK_ACCURACY[1]	F3B31

Configuration word GMC_GAIN

Default value: 3'b000

GMC_GAIN[0]	F2B50
GMC_GAIN[1]	F2B51
GMC_GAIN[2]	F2B52

Configuration word GMC_TEST

Default value: 4'b0000

GMC_TEST[0]	F1B40
GMC_TEST[1]	F1B41
GMC_TEST[2]	F1B42
GMC_TEST[3]	F1B43

Configuration word ICP_CURRENT

Default value: 5'b00000

ICP_CURRENT[0]	F1B12
ICP_CURRENT[1]	F1B13
ICP_CURRENT[2]	F1B14
ICP_CURRENT[3]	F1B15
ICP_CURRENT[4]	F1B16

Configuration word KVCO

Default value: 3'b000

KVCO[0]	F1B17
KVCO[1]	F1B18
KVCO[2]	F1B19

Configuration word LPF_CAPACITOR

Default value: 2'b00

LPF_CAPACITOR[0]	F1B44
LPF_CAPACITOR[1]	F1B45

Configuration word LPF_RESISTOR

Default value: 7'b0000000

LPF_RESISTOR[0]	F1B20
LPF_RESISTOR[1]	F1B21
LPF_RESISTOR[2]	F1B22
LPF_RESISTOR[3]	F1B23
LPF_RESISTOR[4]	F1B24
LPF_RESISTOR[5]	F1B25
LPF_RESISTOR[6]	F1B26

Configuration word MFG1_TEST

Default value: 3'b000

MFG1_TEST[0]	F1B28
MFG1_TEST[1]	F1B29
MFG1_TEST[2]	F1B30

Configuration word MFG2_TEST

Default value: 3'b000

MFG2_TEST[0]	F1B31
MFG2_TEST[1]	F1B32
MFG2_TEST[2]	F1B33

Configuration bit MFG_ENABLE_FILTEROPAMP

Default value: 1'b0

MFG_ENABLE_FILTEROPAMP[0]

F2B54

Configuration bit MFG_EN_UP

Default value: 1'b0

MFG_EN_UP[0]

F2B21

Configuration bit MFG_FLOAT_ICP

Default value: 1'b0

MFG_FLOAT_ICP[0]

F2B53

Configuration bit MFG_FORCE_VFILTER

Default value: 1'b0

MFG_FORCE_VFILTER[0]

F2B49

Configuration word MFG_GMCREF_SEL

Default value: 2'b00

MFG_GMCREF_SEL[0]	F1B34
MFG_GMCREF_SEL[1]	F1B35

Configuration bit MFG_GMC_PRESET

Default value: 1'b0

MFG_GMC_PRESET[0]

F1B27

Configuration bit MFG_GMC_RESET

Default value: 1'b0

MFG_GMC_RESET[0]

F2B41

Configuration bit MFG_ICP_TEST

Default value: 1'b0

MFG_ICP_TEST[0]

F2B55

Configuration bit MFG_LF_PRESET

Default value: 1'b0

MFG_LF_PRESET[0]

F2B57

Configuration bit MFG_LF_RESET

Default value: 1'b0

MFG_LF_RESET[0]

F2B56

Configuration bit MFG_LF_RESGRND

Default value: 1'b0

MFG_LF_RESGRND[0]

F2B25

Configuration word PLL_LOCK_MODE

Default value: 3'b000

PLL_LOCK_MODE[0]	F3B52
PLL_LOCK_MODE[1]	F3B53
PLL_LOCK_MODE[2]	F3B54

Configuration word PREDIVIDER_MUXA1

Default value: 2'b00

PREDIVIDER_MUXA1[0]	F3B38
PREDIVIDER_MUXA1[1]	F3B39

Configuration word PREDIVIDER_MUXB1

Default value: 2'b00

PREDIVIDER_MUXB1[0]	F3B36
PREDIVIDER_MUXB1[1]	F3B37

Configuration word PREDIVIDER_MUXC1

Default value: 2'b00

PREDIVIDER_MUXC1[0]	F3B34
PREDIVIDER_MUXC1[1]	F3B35

Configuration word PREDIVIDER_MUXD1

Default value: 2'b00

PREDIVIDER_MUXD1[0]	F3B32
PREDIVIDER_MUXD1[1]	F3B33

Configuration Setting CLKOP_ENABLE

Default value: DISABLED

Value	F3B48
DISABLED	-
ENABLED	1

Configuration Setting CLKOP_TRIM_DELAY

Default value: 0

Value	F2B14	F2B15	F2B16	F2B17	F3B44	F3B45	F3B46
0	0	0	0	0	0	0	0
1	1	1	1	1	1	0	0
2	1	1	1	1	0	1	0
4	1	1	1	1	0	0	1

Configuration Setting CLKOP_TRIM_POL

Default value: FALLING

Value	F3B47
FALLING	0
RISING	1

Configuration Setting CLKOS2_ENABLE

Default value: DISABLED

Value	F3B50
DISABLED	-
ENABLED	1

Configuration Setting CLKOS3_ENABLE

Default value: DISABLED

Value	F3B51
DISABLED	-
ENABLED	1

Configuration Setting CLKOS_ENABLE

Default value: DISABLED

Value	F3B49
DISABLED	-
ENABLED	1

Configuration Setting CLKOS_TRIM_DELAY

Default value: 0

Value	F2B15	F3B40	F3B41	F3B42
0	0	0	0	0
1	1	1	0	0
2	1	0	1	0
4	1	0	0	1

Configuration Setting CLKOS_TRIM_POL

Default value: FALLING

Value	F3B43
FALLING	0
RISING	1

Configuration Setting CLOCK_ENABLE_PORTS

Default value: ENABLED

Value	F3B48	F3B49	F3B50	F3B51
DISABLED	1	1	1	1
ENABLED	-	-	-	-

Configuration Setting DCRST_ENA

Default value: DISABLED

Value	F3B15
DISABLED	0
ENABLED	1

Configuration Setting DDRST_ENA

Default value: DISABLED

Value	F3B23
DISABLED	0
ENABLED	1

Configuration Setting DPHASE_SOURCE

Default value: DISABLED

Value	F3B55
DISABLED	0
ENABLED	1

Configuration Setting FEEDBK_PATH

Default value: USERCLOCK

Value	F2B26	F2B27	F2B29	F2B30	F2B31
CLKOP	-	-	-	-	-
CLKOS	-	-	-	-	-
INT_DIVA	1	1	1	-	-
INT_DIVB	-	1	1	1	-
INT_DIVC	1	-	1	-	1
INT_DIVD	-	-	1	1	1
USERCLOCK	-	-	-	-	-
CLKOS2	-	-	-	-	-
CLKOS3	-	-	-	-	-

Configuration Setting FRACN_ENABLE

Default value: DISABLED

Value	F4B13
DISABLED	-
ENABLED	1

Configuration Setting INTFB_WAKE

Default value: DISABLED

Value	F3B19
DISABLED	0
ENABLED	1

Configuration Setting INT_LOCK_STICKY

Default value: DISABLED

Value	F4B49
DISABLED	0
ENABLED	1

Configuration Setting MODE

Default value: NONE

Value	F5B43
NONE	-
EHXPLLJ	1

Configuration Setting MRST_ENA

Default value: DISABLED

Value	F4B37
DISABLED	0
ENABLED	1

Configuration Setting OUTDIVIDER_MUXA2

Default value: DIVA

Value	F3B18
DIVA	-
REFCLK	1

Configuration Setting OUTDIVIDER_MUXB2

Default value: DIVB

Value	F3B22
DIVB	-
REFCLK	1

Configuration Setting OUTDIVIDER_MUXC2

Default value: DIVC

Value	F3B29
DIVC	-
REFCLK	1

Configuration Setting OUTDIVIDER_MUXD2

Default value: DIVD

Value	F3B26
DIVD	-
REFCLK	1

Configuration Setting PLLRST_ENA

Default value: DISABLED

Value	F4B29
DISABLED	0
ENABLED	1

Configuration Setting PLL_EXPERT

Default value: DISABLED

Value	F0B13
DISABLED	-
ENABLED	1

Configuration Setting PLL_USE_WB

Default value: DISABLED

Value	F0B12
DISABLED	-
ENABLED	1

Configuration Setting REFIN_RESET

Default value: DISABLED

Value	F4B21
DISABLED	0
ENABLED	1

Configuration Setting STDBY_ENABLE

Default value: DISABLED

Value	F4B45
DISABLED	0
ENABLED	1

Configuration Setting SYNC_ENABLE

Default value: DISABLED

Value	F4B53
DISABLED	0
ENABLED	1

Configuration Setting VCO_BYPASS_A0

Default value: ENABLED

Value	F1B36
DISABLED	1
ENABLED	-

Configuration Setting VCO_BYPASS_B0

Default value: ENABLED

Value	F1B37
DISABLED	1
ENABLED	-

Configuration Setting VCO_BYPASS_C0

Default value: ENABLED

Value	F1B38
DISABLED	1
ENABLED	-

Configuration Setting VCO_BYPASS_D0

Default value: ENABLED

Value	F1B39
DISABLED	1
ENABLED	-

Fixed Connections

Source		Sink
S1E1_JCLKOP_PLL	→	1300_S11E12_JA0_CLKFBBUF
S1E1_JCLKOP_PLL	→	1300_S11E12_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	1300_S11E12_JPLLCLKOS0
S1E1_JCLKOP_PLL	→	1300_S1E12_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	1300_S1E12_JPLLCLKOS0
S1E1_JPLLACK_PLL	→	1300_S1E3_JPLL0ACKI_EFB
S1E1_JPLLDATO0_PLL	→	1300_S1E3_JPLL0DATI0_EFB
S1E1_JPLLDATO1_PLL	→	1300_S1E3_JPLL0DATI1_EFB
S1E1_JPLLDATO2_PLL	→	1300_S1E3_JPLL0DATI2_EFB
S1E1_JPLLDATO3_PLL	→	1300_S1E3_JPLL0DATI3_EFB
S1E1_JPLLDATO4_PLL	→	1300_S1E3_JPLL0DATI4_EFB
S1E1_JPLLDATO5_PLL	→	1300_S1E3_JPLL0DATI5_EFB
S1E1_JPLLDATO6_PLL	→	1300_S1E3_JPLL0DATI6_EFB
S1E1_JPLLDATO7_PLL	→	1300_S1E3_JPLL0DATI7_EFB
S1E1_JCLKOP_PLL	→	2100_S14E13_JA0_CLKFBBUF
S1E1_JCLKOP_PLL	→	2100_S14E13_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	2100_S14E13_JPLLCLKOS0
S1E1_JCLKOP_PLL	→	2100_S1E13_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	2100_S1E13_JPLLCLKOS0
S1E1_JPLLACK_PLL	→	2100_S1E3_JPLL0ACKI_EFB
S1E1_JPLLDATO0_PLL	→	2100_S1E3_JPLL0DATI0_EFB
S1E1_JPLLDATO1_PLL	→	2100_S1E3_JPLL0DATI1_EFB
S1E1_JPLLDATO2_PLL	→	2100_S1E3_JPLL0DATI2_EFB
S1E1_JPLLDATO3_PLL	→	2100_S1E3_JPLL0DATI3_EFB
S1E1_JPLLDATO4_PLL	→	2100_S1E3_JPLL0DATI4_EFB
S1E1_JPLLDATO5_PLL	→	2100_S1E3_JPLL0DATI5_EFB
S1E1_JPLLDATO6_PLL	→	2100_S1E3_JPLL0DATI6_EFB
S1E1_JPLLDATO7_PLL	→	2100_S1E3_JPLL0DATI7_EFB
S1E1_JCLKOP_PLL	→	4300_S1E15_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	4300_S1E15_JPLLCLKOS0
S1E1_JPLLACK_PLL	→	4300_S1E3_JPLL0ACKI
S1E1_JPLLDATO0_PLL	→	4300_S1E3_JPLL0DATI0
S1E1_JPLLDATO1_PLL	→	4300_S1E3_JPLL0DATI1
S1E1_JPLLDATO2_PLL	→	4300_S1E3_JPLL0DATI2
S1E1_JPLLDATO3_PLL	→	4300_S1E3_JPLL0DATI3
S1E1_JPLLDATO4_PLL	→	4300_S1E3_JPLL0DATI4
S1E1_JPLLDATO5_PLL	→	4300_S1E3_JPLL0DATI5
S1E1_JPLLDATO6_PLL	→	4300_S1E3_JPLL0DATI6
S1E1_JPLLDATO7_PLL	→	4300_S1E3_JPLL0DATI7
S1E1_JCLKOP_PLL	→	4300_S21E15_JA0_CLKFBBUF
S1E1_JCLKOP_PLL	→	4300_S21E15_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	4300_S21E15_JPLLCLKOS0
S1E1_JCLKOP_PLL	→	6900_S1E18_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	6900_S1E18_JPLLCLKOS0
S1E1_JPLLACK_PLL	→	6900_S1E3_JPLL0ACKI
S1E1_JPLLDATO0_PLL	→	6900_S1E3_JPLL0DATI0
S1E1_JPLLDATO1_PLL	→	6900_S1E3_JPLL0DATI1
S1E1_JPLLDATO2_PLL	→	6900_S1E3_JPLL0DATI2
S1E1_JPLLDATO3_PLL	→	6900_S1E3_JPLL0DATI3
S1E1_JPLLDATO4_PLL	→	6900_S1E3_JPLL0DATI4
S1E1_JPLLDATO5_PLL	→	6900_S1E3_JPLL0DATI5
S1E1_JPLLDATO6_PLL	→	6900_S1E3_JPLL0DATI6
S1E1_JPLLDATO7_PLL	→	6900_S1E3_JPLL0DATI7
S1E1_JCLKOP_PLL	→	6900_S26E18_JA0_CLKFBBUF
S1E1_JCLKOP_PLL	→	6900_S26E18_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	6900_S26E18_JPLLCLKOS0
S1E1_JCLKOP_PLL	→	9400_S1E24_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	9400_S1E24_JPLLCLKOS0
S1E1_JPLLACK_PLL	→	9400_S1E3_JPLL0ACKI
S1E1_JPLLDATO0_PLL	→	9400_S1E3_JPLL0DATI0
S1E1_JPLLDATO1_PLL	→	9400_S1E3_JPLL0DATI1
S1E1_JPLLDATO2_PLL	→	9400_S1E3_JPLL0DATI2
S1E1_JPLLDATO3_PLL	→	9400_S1E3_JPLL0DATI3
S1E1_JPLLDATO4_PLL	→	9400_S1E3_JPLL0DATI4
S1E1_JPLLDATO5_PLL	→	9400_S1E3_JPLL0DATI5
S1E1_JPLLDATO6_PLL	→	9400_S1E3_JPLL0DATI6
S1E1_JPLLDATO7_PLL	→	9400_S1E3_JPLL0DATI7
S1E1_JCLKOP_PLL	→	9400_S30E24_JA0_CLKFBBUF
S1E1_JCLKOP_PLL	→	9400_S30E24_JPLLCLKOP0
S1E1_JCLKOS_PLL	→	9400_S30E24_JPLLCLKOS0
S1E1_REFCLK0	→	S1E1_CLK0_PLLREFCS
S1E1_REFCLK1	→	S1E1_CLK1_PLLREFCS
S1E1_CLKFB	→	S1E1_CLKFB_PLL
S1E1_CLKINTFB_PLL	→	S1E1_CLKINTFB
S1E1_PLLCSOUT_PLLREFCS	→	S1E1_CLKI_PLL
S1E1_JCLKOP_PLL	→	G_JLPLLCLK0
S1E1_JCLKOS_PLL	→	G_JLPLLCLK1
S1E1_JCLKOS2_PLL	→	G_JLPLLCLK2
S1E1_JCLKOS3_PLL	→	G_JLPLLCLK3
S1E1_JCLK1	→	S1E1_JCLKFB1
1300_S11E12_JPLLCLKFB1	→	S1E1_JCLKFB2
2100_S14E13_JPLLCLKFB1	→	S1E1_JCLKFB2
4300_S21E15_JPLLCLKFB1	→	S1E1_JCLKFB2
6900_S26E18_JPLLCLKFB1	→	S1E1_JCLKFB2
9400_S30E24_JPLLCLKFB1	→	S1E1_JCLKFB2
1300_S11E12_JPLLCLKFB0	→	S1E1_JCLKFB4
2100_S14E13_JPLLCLKFB0	→	S1E1_JCLKFB4
4300_S21E15_JPLLCLKFB0	→	S1E1_JCLKFB4
6900_S26E18_JPLLCLKFB0	→	S1E1_JCLKFB4
9400_S30E24_JPLLCLKFB0	→	S1E1_JCLKFB4
S1E1_JD2	→	S1E1_JENCLKOP_PLL
S1E1_JB3	→	S1E1_JENCLKOS2_PLL
S1E1_JC3	→	S1E1_JENCLKOS3_PLL
S1E1_JA3	→	S1E1_JENCLKOS_PLL
S1E1_JCLKOP_PLL	→	S1E1_JF0
S1E1_JCLKOS_PLL	→	S1E1_JF2
S1E1_JCLKOS2_PLL	→	S1E1_JF4
S1E1_JCLKOS3_PLL	→	S1E1_JF6
S1E1_JD3	→	S1E1_JLOADREG_PLL
S1E1_JD4	→	S1E1_JPHASEDIR_PLL
S1E1_JB4	→	S1E1_JPHASESEL0_PLL
S1E1_JA4	→	S1E1_JPHASESEL1_PLL
S1E1_JC4	→	S1E1_JPHASESTEP_PLL
1300_S1E3_JPLLADRO0_EFB	→	S1E1_JPLLADDR0_PLL
2100_S1E3_JPLLADRO0_EFB	→	S1E1_JPLLADDR0_PLL
4300_S1E3_JPLLADRO0_EFB	→	S1E1_JPLLADDR0_PLL
6900_S1E3_JPLLADRO0_EFB	→	S1E1_JPLLADDR0_PLL
9400_S1E3_JPLLADRO0_EFB	→	S1E1_JPLLADDR0_PLL
1300_S1E3_JPLLADRO1_EFB	→	S1E1_JPLLADDR1_PLL
2100_S1E3_JPLLADRO1_EFB	→	S1E1_JPLLADDR1_PLL
4300_S1E3_JPLLADRO1_EFB	→	S1E1_JPLLADDR1_PLL
6900_S1E3_JPLLADRO1_EFB	→	S1E1_JPLLADDR1_PLL
9400_S1E3_JPLLADRO1_EFB	→	S1E1_JPLLADDR1_PLL
1300_S1E3_JPLLADRO2_EFB	→	S1E1_JPLLADDR2_PLL
2100_S1E3_JPLLADRO2_EFB	→	S1E1_JPLLADDR2_PLL
4300_S1E3_JPLLADRO2_EFB	→	S1E1_JPLLADDR2_PLL
6900_S1E3_JPLLADRO2_EFB	→	S1E1_JPLLADDR2_PLL
9400_S1E3_JPLLADRO2_EFB	→	S1E1_JPLLADDR2_PLL
1300_S1E3_JPLLADRO3_EFB	→	S1E1_JPLLADDR3_PLL
2100_S1E3_JPLLADRO3_EFB	→	S1E1_JPLLADDR3_PLL
4300_S1E3_JPLLADRO3_EFB	→	S1E1_JPLLADDR3_PLL
6900_S1E3_JPLLADRO3_EFB	→	S1E1_JPLLADDR3_PLL
9400_S1E3_JPLLADRO3_EFB	→	S1E1_JPLLADDR3_PLL
1300_S1E3_JPLLADRO4_EFB	→	S1E1_JPLLADDR4_PLL
2100_S1E3_JPLLADRO4_EFB	→	S1E1_JPLLADDR4_PLL
4300_S1E3_JPLLADRO4_EFB	→	S1E1_JPLLADDR4_PLL
6900_S1E3_JPLLADRO4_EFB	→	S1E1_JPLLADDR4_PLL
9400_S1E3_JPLLADRO4_EFB	→	S1E1_JPLLADDR4_PLL
1300_S1E3_JPLLCLKO_EFB	→	S1E1_JPLLCLK_PLL
2100_S1E3_JPLLCLKO_EFB	→	S1E1_JPLLCLK_PLL
4300_S1E3_JPLLCLKO_EFB	→	S1E1_JPLLCLK_PLL
6900_S1E3_JPLLCLKO_EFB	→	S1E1_JPLLCLK_PLL
9400_S1E3_JPLLCLKO_EFB	→	S1E1_JPLLCLK_PLL
1300_S1E3_JPLLDATO0_EFB	→	S1E1_JPLLDATI0_PLL
2100_S1E3_JPLLDATO0_EFB	→	S1E1_JPLLDATI0_PLL
4300_S1E3_JPLLDATO0_EFB	→	S1E1_JPLLDATI0_PLL
6900_S1E3_JPLLDATO0_EFB	→	S1E1_JPLLDATI0_PLL
9400_S1E3_JPLLDATO0_EFB	→	S1E1_JPLLDATI0_PLL
1300_S1E3_JPLLDATO1_EFB	→	S1E1_JPLLDATI1_PLL
2100_S1E3_JPLLDATO1_EFB	→	S1E1_JPLLDATI1_PLL
4300_S1E3_JPLLDATO1_EFB	→	S1E1_JPLLDATI1_PLL
6900_S1E3_JPLLDATO1_EFB	→	S1E1_JPLLDATI1_PLL
9400_S1E3_JPLLDATO1_EFB	→	S1E1_JPLLDATI1_PLL
1300_S1E3_JPLLDATO2_EFB	→	S1E1_JPLLDATI2_PLL
2100_S1E3_JPLLDATO2_EFB	→	S1E1_JPLLDATI2_PLL
4300_S1E3_JPLLDATO2_EFB	→	S1E1_JPLLDATI2_PLL
6900_S1E3_JPLLDATO2_EFB	→	S1E1_JPLLDATI2_PLL
9400_S1E3_JPLLDATO2_EFB	→	S1E1_JPLLDATI2_PLL
1300_S1E3_JPLLDATO3_EFB	→	S1E1_JPLLDATI3_PLL
2100_S1E3_JPLLDATO3_EFB	→	S1E1_JPLLDATI3_PLL
4300_S1E3_JPLLDATO3_EFB	→	S1E1_JPLLDATI3_PLL
6900_S1E3_JPLLDATO3_EFB	→	S1E1_JPLLDATI3_PLL
9400_S1E3_JPLLDATO3_EFB	→	S1E1_JPLLDATI3_PLL
1300_S1E3_JPLLDATO4_EFB	→	S1E1_JPLLDATI4_PLL
2100_S1E3_JPLLDATO4_EFB	→	S1E1_JPLLDATI4_PLL
4300_S1E3_JPLLDATO4_EFB	→	S1E1_JPLLDATI4_PLL
6900_S1E3_JPLLDATO4_EFB	→	S1E1_JPLLDATI4_PLL
9400_S1E3_JPLLDATO4_EFB	→	S1E1_JPLLDATI4_PLL
1300_S1E3_JPLLDATO5_EFB	→	S1E1_JPLLDATI5_PLL
2100_S1E3_JPLLDATO5_EFB	→	S1E1_JPLLDATI5_PLL
4300_S1E3_JPLLDATO5_EFB	→	S1E1_JPLLDATI5_PLL
6900_S1E3_JPLLDATO5_EFB	→	S1E1_JPLLDATI5_PLL
9400_S1E3_JPLLDATO5_EFB	→	S1E1_JPLLDATI5_PLL
1300_S1E3_JPLLDATO6_EFB	→	S1E1_JPLLDATI6_PLL
2100_S1E3_JPLLDATO6_EFB	→	S1E1_JPLLDATI6_PLL
4300_S1E3_JPLLDATO6_EFB	→	S1E1_JPLLDATI6_PLL
6900_S1E3_JPLLDATO6_EFB	→	S1E1_JPLLDATI6_PLL
9400_S1E3_JPLLDATO6_EFB	→	S1E1_JPLLDATI6_PLL
1300_S1E3_JPLLDATO7_EFB	→	S1E1_JPLLDATI7_PLL
2100_S1E3_JPLLDATO7_EFB	→	S1E1_JPLLDATI7_PLL
4300_S1E3_JPLLDATO7_EFB	→	S1E1_JPLLDATI7_PLL
6900_S1E3_JPLLDATO7_EFB	→	S1E1_JPLLDATI7_PLL
9400_S1E3_JPLLDATO7_EFB	→	S1E1_JPLLDATI7_PLL
1300_S1E3_JPLLRSTO_EFB	→	S1E1_JPLLRST_PLL
2100_S1E3_JPLLRSTO_EFB	→	S1E1_JPLLRST_PLL
4300_S1E3_JPLLRSTO_EFB	→	S1E1_JPLLRST_PLL
6900_S1E3_JPLLRSTO_EFB	→	S1E1_JPLLRST_PLL
9400_S1E3_JPLLRSTO_EFB	→	S1E1_JPLLRST_PLL
1300_S1E3_JPLL0STBO_EFB	→	S1E1_JPLLSTB_PLL
2100_S1E3_JPLL0STBO_EFB	→	S1E1_JPLLSTB_PLL
4300_S1E3_JPLL0STBOMUX	→	S1E1_JPLLSTB_PLL
6900_S1E3_JPLL0STBOMUX	→	S1E1_JPLLSTB_PLL
9400_S1E3_JPLL0STBOMUX	→	S1E1_JPLLSTB_PLL
S1E1_JC2	→	S1E1_JPLLWAKESYNC_PLL
1300_S1E3_JPLLWEO_EFB	→	S1E1_JPLLWE_PLL
2100_S1E3_JPLLWEO_EFB	→	S1E1_JPLLWE_PLL
4300_S1E3_JPLLWEO_EFB	→	S1E1_JPLLWE_PLL
6900_S1E3_JPLLWEO_EFB	→	S1E1_JPLLWE_PLL
9400_S1E3_JPLLWEO_EFB	→	S1E1_JPLLWE_PLL
S1E1_JREFCLK_PLL	→	S1E1_JQ0
S1E1_JLOCK_PLL	→	S1E1_JQ2
S1E1_JINTLOCK_PLL	→	S1E1_JQ4
S1E1_JDPHSRC_PLL	→	S1E1_JQ6
G_JOSC_OSC	→	S1E1_JREFCLK0
S1E1_JA0	→	S1E1_JREFCLK1_0
S1E2_JA0	→	S1E1_JREFCLK1_1
S1E1_JCLK0	→	S1E1_JREFCLK2_0
S1E2_JCLK0	→	S1E1_JREFCLK2_1
S1E1_CLKI_PLL	→	S1E1_JREFCLK_PLL
S1E1_JD1	→	S1E1_JRESETC_PLL
S1E1_JA2	→	S1E1_JRESETD_PLL
S1E1_JC1	→	S1E1_JRESETM_PLL
S1E1_JB1	→	S1E1_JRST_PLL
S1E1_JB2	→	S1E1_JSEL_PLLREFCS
S1E1_JLSR0	→	S1E1_JSTDBY_PLL
S1E1_CLK0_PLLREFCS	→	S1E1_PLLCSOUT_PLLREFCS













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