MachXO2 Speed Grade -5 Cell Timings

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SLICE

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4518	4518	4518	4518	4518	4518
CLKA	DOA1	4518	4518	4518	4518	4518	4518
CLKA	DOA2	4518	4518	4518	4518	4518	4518
CLKA	DOA3	4518	4518	4518	4518	4518	4518
CLKA	DOA4	4518	4518	4518	4518	4518	4518
CLKA	DOA5	4518	4518	4518	4518	4518	4518
CLKA	DOA6	4518	4518	4518	4518	4518	4518
CLKA	DOA7	4518	4518	4518	4518	4518	4518
CLKA	DOA8	4518	4518	4518	4518	4518	4518
CLKB	DOB0	4739	4739	4739	4739	4739	4739
CLKB	DOB1	4739	4739	4739	4739	4739	4739
CLKB	DOB2	4739	4739	4739	4739	4739	4739
CLKB	DOB3	4739	4739	4739	4739	4739	4739
CLKB	DOB4	4739	4739	4739	4739	4739	4739
CLKB	DOB5	4739	4739	4739	4739	4739	4739
CLKB	DOB6	4739	4739	4739	4739	4739	4739
CLKB	DOB7	4739	4739	4739	4739	4739	4739
CLKB	DOB8	4739	4739	4739	4739	4739	4739

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	77	77	77
ADA1	posedge CLKA	0	0	0	77	77	77
ADA10	posedge CLKA	0	0	0	77	77	77
ADA11	posedge CLKA	0	0	0	77	77	77
ADA12	posedge CLKA	0	0	0	77	77	77
ADA2	posedge CLKA	0	0	0	77	77	77
ADA3	posedge CLKA	0	0	0	77	77	77
ADA4	posedge CLKA	0	0	0	77	77	77
ADA5	posedge CLKA	0	0	0	77	77	77
ADA6	posedge CLKA	0	0	0	77	77	77
ADA7	posedge CLKA	0	0	0	77	77	77
ADA8	posedge CLKA	0	0	0	77	77	77
ADA9	posedge CLKA	0	0	0	77	77	77
ADB0	posedge CLKB	0	0	0	169	169	169
ADB1	posedge CLKB	0	0	0	169	169	169
ADB10	posedge CLKB	0	0	0	169	169	169
ADB11	posedge CLKB	0	0	0	169	169	169
ADB12	posedge CLKB	0	0	0	169	169	169
ADB2	posedge CLKB	0	0	0	169	169	169
ADB3	posedge CLKB	0	0	0	169	169	169
ADB4	posedge CLKB	0	0	0	169	169	169
ADB5	posedge CLKB	0	0	0	169	169	169
ADB6	posedge CLKB	0	0	0	169	169	169
ADB7	posedge CLKB	0	0	0	169	169	169
ADB8	posedge CLKB	0	0	0	169	169	169
ADB9	posedge CLKB	0	0	0	169	169	169
CEA	posedge CLKA	199	199	199	0	0	0
CEB	posedge CLKB	219	219	219	0	0	0
CSA0	posedge CLKA	118	118	118	0	0	0
CSA1	posedge CLKA	118	118	118	0	0	0
CSA2	posedge CLKA	118	118	118	0	0	0
CSB0	posedge CLKB	1	1	1	87	87	87
CSB1	posedge CLKB	1	1	1	87	87	87
CSB2	posedge CLKB	1	1	1	87	87	87
DIA0	posedge CLKA	0	0	0	92	92	92
DIA1	posedge CLKA	0	0	0	92	92	92
DIA2	posedge CLKA	0	0	0	92	92	92
DIA3	posedge CLKA	0	0	0	92	92	92
DIA4	posedge CLKA	0	0	0	92	92	92
DIA5	posedge CLKA	0	0	0	92	92	92
DIA6	posedge CLKA	0	0	0	92	92	92
DIA7	posedge CLKA	0	0	0	92	92	92
DIA8	posedge CLKA	0	0	0	92	92	92
DIB0	posedge CLKB	0	0	0	175	175	175
DIB1	posedge CLKB	0	0	0	175	175	175
DIB2	posedge CLKB	0	0	0	175	175	175
DIB3	posedge CLKB	0	0	0	175	175	175
DIB4	posedge CLKB	0	0	0	175	175	175
DIB5	posedge CLKB	0	0	0	175	175	175
DIB6	posedge CLKB	0	0	0	175	175	175
DIB7	posedge CLKB	0	0	0	175	175	175
DIB8	posedge CLKB	0	0	0	175	175	175
OCEA	posedge CLKA	0	0	0	140	140	140
OCEB	posedge CLKB	0	0	0	166	166	166
RSTA	posedge CLKA	385	385	385	0	0	0
RSTB	posedge CLKB	130	130	130	32	32	32
WEA	posedge CLKA	109	109	109	0	0	0
WEB	posedge CLKB	14	14	14	45	45	45

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3036	3036	3036	165	165	165
negedge CLKB	3036	3036	3036	165	165	165
posedge CLKA	3036	3036	3036	165	165	165
posedge CLKB	3036	3036	3036	165	165	165

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4518	4518	4518	4518	4518	4518
CLKA	DOA1	4518	4518	4518	4518	4518	4518
CLKA	DOA2	4518	4518	4518	4518	4518	4518
CLKA	DOA3	4518	4518	4518	4518	4518	4518
CLKA	DOA4	4518	4518	4518	4518	4518	4518
CLKA	DOA5	4518	4518	4518	4518	4518	4518
CLKA	DOA6	4518	4518	4518	4518	4518	4518
CLKA	DOA7	4518	4518	4518	4518	4518	4518
CLKA	DOA8	4518	4518	4518	4518	4518	4518
CLKB	DOB0	922	922	922	922	922	922
CLKB	DOB1	922	922	922	922	922	922
CLKB	DOB2	922	922	922	922	922	922
CLKB	DOB3	922	922	922	922	922	922
CLKB	DOB4	922	922	922	922	922	922
CLKB	DOB5	922	922	922	922	922	922
CLKB	DOB6	922	922	922	922	922	922
CLKB	DOB7	922	922	922	922	922	922
CLKB	DOB8	922	922	922	922	922	922

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	77	77	77
ADA1	posedge CLKA	0	0	0	77	77	77
ADA10	posedge CLKA	0	0	0	77	77	77
ADA11	posedge CLKA	0	0	0	77	77	77
ADA12	posedge CLKA	0	0	0	77	77	77
ADA2	posedge CLKA	0	0	0	77	77	77
ADA3	posedge CLKA	0	0	0	77	77	77
ADA4	posedge CLKA	0	0	0	77	77	77
ADA5	posedge CLKA	0	0	0	77	77	77
ADA6	posedge CLKA	0	0	0	77	77	77
ADA7	posedge CLKA	0	0	0	77	77	77
ADA8	posedge CLKA	0	0	0	77	77	77
ADA9	posedge CLKA	0	0	0	77	77	77
ADB0	posedge CLKB	0	0	0	169	169	169
ADB1	posedge CLKB	0	0	0	169	169	169
ADB10	posedge CLKB	0	0	0	169	169	169
ADB11	posedge CLKB	0	0	0	169	169	169
ADB12	posedge CLKB	0	0	0	169	169	169
ADB2	posedge CLKB	0	0	0	169	169	169
ADB3	posedge CLKB	0	0	0	169	169	169
ADB4	posedge CLKB	0	0	0	169	169	169
ADB5	posedge CLKB	0	0	0	169	169	169
ADB6	posedge CLKB	0	0	0	169	169	169
ADB7	posedge CLKB	0	0	0	169	169	169
ADB8	posedge CLKB	0	0	0	169	169	169
ADB9	posedge CLKB	0	0	0	169	169	169
CEA	posedge CLKA	199	199	199	0	0	0
CEB	posedge CLKB	219	219	219	0	0	0
CSA0	posedge CLKA	118	118	118	0	0	0
CSA1	posedge CLKA	118	118	118	0	0	0
CSA2	posedge CLKA	118	118	118	0	0	0
CSB0	posedge CLKB	1	1	1	87	87	87
CSB1	posedge CLKB	1	1	1	87	87	87
CSB2	posedge CLKB	1	1	1	87	87	87
DIA0	posedge CLKA	0	0	0	92	92	92
DIA1	posedge CLKA	0	0	0	92	92	92
DIA2	posedge CLKA	0	0	0	92	92	92
DIA3	posedge CLKA	0	0	0	92	92	92
DIA4	posedge CLKA	0	0	0	92	92	92
DIA5	posedge CLKA	0	0	0	92	92	92
DIA6	posedge CLKA	0	0	0	92	92	92
DIA7	posedge CLKA	0	0	0	92	92	92
DIA8	posedge CLKA	0	0	0	92	92	92
DIB0	posedge CLKB	0	0	0	175	175	175
DIB1	posedge CLKB	0	0	0	175	175	175
DIB2	posedge CLKB	0	0	0	175	175	175
DIB3	posedge CLKB	0	0	0	175	175	175
DIB4	posedge CLKB	0	0	0	175	175	175
DIB5	posedge CLKB	0	0	0	175	175	175
DIB6	posedge CLKB	0	0	0	175	175	175
DIB7	posedge CLKB	0	0	0	175	175	175
DIB8	posedge CLKB	0	0	0	175	175	175
OCEA	posedge CLKA	0	0	0	140	140	140
OCEB	posedge CLKB	0	0	0	166	166	166
RSTA	posedge CLKA	385	385	385	0	0	0
RSTB	posedge CLKB	227	227	227	32	32	32
WEA	posedge CLKA	109	109	109	0	0	0
WEB	posedge CLKB	14	14	14	45	45	45

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3036	3036	3036	165	165	165
negedge CLKB	3036	3036	3036	165	165	165
posedge CLKA	3036	3036	3036	165	165	165
posedge CLKB	3036	3036	3036	165	165	165

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	893	893	893	893	893	893
CLKA	DOA1	893	893	893	893	893	893
CLKA	DOA2	893	893	893	893	893	893
CLKA	DOA3	893	893	893	893	893	893
CLKA	DOA4	893	893	893	893	893	893
CLKA	DOA5	893	893	893	893	893	893
CLKA	DOA6	893	893	893	893	893	893
CLKA	DOA7	893	893	893	893	893	893
CLKA	DOA8	893	893	893	893	893	893
CLKB	DOB0	4739	4739	4739	4739	4739	4739
CLKB	DOB1	4739	4739	4739	4739	4739	4739
CLKB	DOB2	4739	4739	4739	4739	4739	4739
CLKB	DOB3	4739	4739	4739	4739	4739	4739
CLKB	DOB4	4739	4739	4739	4739	4739	4739
CLKB	DOB5	4739	4739	4739	4739	4739	4739
CLKB	DOB6	4739	4739	4739	4739	4739	4739
CLKB	DOB7	4739	4739	4739	4739	4739	4739
CLKB	DOB8	4739	4739	4739	4739	4739	4739

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	77	77	77
ADA1	posedge CLKA	0	0	0	77	77	77
ADA10	posedge CLKA	0	0	0	77	77	77
ADA11	posedge CLKA	0	0	0	77	77	77
ADA12	posedge CLKA	0	0	0	77	77	77
ADA2	posedge CLKA	0	0	0	77	77	77
ADA3	posedge CLKA	0	0	0	77	77	77
ADA4	posedge CLKA	0	0	0	77	77	77
ADA5	posedge CLKA	0	0	0	77	77	77
ADA6	posedge CLKA	0	0	0	77	77	77
ADA7	posedge CLKA	0	0	0	77	77	77
ADA8	posedge CLKA	0	0	0	77	77	77
ADA9	posedge CLKA	0	0	0	77	77	77
ADB0	posedge CLKB	0	0	0	169	169	169
ADB1	posedge CLKB	0	0	0	169	169	169
ADB10	posedge CLKB	0	0	0	169	169	169
ADB11	posedge CLKB	0	0	0	169	169	169
ADB12	posedge CLKB	0	0	0	169	169	169
ADB2	posedge CLKB	0	0	0	169	169	169
ADB3	posedge CLKB	0	0	0	169	169	169
ADB4	posedge CLKB	0	0	0	169	169	169
ADB5	posedge CLKB	0	0	0	169	169	169
ADB6	posedge CLKB	0	0	0	169	169	169
ADB7	posedge CLKB	0	0	0	169	169	169
ADB8	posedge CLKB	0	0	0	169	169	169
ADB9	posedge CLKB	0	0	0	169	169	169
CEA	posedge CLKA	199	199	199	0	0	0
CEB	posedge CLKB	219	219	219	0	0	0
CSA0	posedge CLKA	118	118	118	0	0	0
CSA1	posedge CLKA	118	118	118	0	0	0
CSA2	posedge CLKA	118	118	118	0	0	0
CSB0	posedge CLKB	1	1	1	87	87	87
CSB1	posedge CLKB	1	1	1	87	87	87
CSB2	posedge CLKB	1	1	1	87	87	87
DIA0	posedge CLKA	0	0	0	92	92	92
DIA1	posedge CLKA	0	0	0	92	92	92
DIA2	posedge CLKA	0	0	0	92	92	92
DIA3	posedge CLKA	0	0	0	92	92	92
DIA4	posedge CLKA	0	0	0	92	92	92
DIA5	posedge CLKA	0	0	0	92	92	92
DIA6	posedge CLKA	0	0	0	92	92	92
DIA7	posedge CLKA	0	0	0	92	92	92
DIA8	posedge CLKA	0	0	0	92	92	92
DIB0	posedge CLKB	0	0	0	175	175	175
DIB1	posedge CLKB	0	0	0	175	175	175
DIB2	posedge CLKB	0	0	0	175	175	175
DIB3	posedge CLKB	0	0	0	175	175	175
DIB4	posedge CLKB	0	0	0	175	175	175
DIB5	posedge CLKB	0	0	0	175	175	175
DIB6	posedge CLKB	0	0	0	175	175	175
DIB7	posedge CLKB	0	0	0	175	175	175
DIB8	posedge CLKB	0	0	0	175	175	175
OCEA	posedge CLKA	0	0	0	140	140	140
OCEB	posedge CLKB	0	0	0	166	166	166
RSTA	posedge CLKA	385	385	385	0	0	0
RSTB	posedge CLKB	130	130	130	32	32	32
WEA	posedge CLKA	109	109	109	0	0	0
WEB	posedge CLKB	14	14	14	45	45	45

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3036	3036	3036	165	165	165
negedge CLKB	3036	3036	3036	165	165	165
posedge CLKA	3036	3036	3036	165	165	165
posedge CLKB	3036	3036	3036	165	165	165

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	893	893	893	893	893	893
CLKA	DOA1	893	893	893	893	893	893
CLKA	DOA2	893	893	893	893	893	893
CLKA	DOA3	893	893	893	893	893	893
CLKA	DOA4	893	893	893	893	893	893
CLKA	DOA5	893	893	893	893	893	893
CLKA	DOA6	893	893	893	893	893	893
CLKA	DOA7	893	893	893	893	893	893
CLKA	DOA8	893	893	893	893	893	893
CLKB	DOB0	922	922	922	922	922	922
CLKB	DOB1	922	922	922	922	922	922
CLKB	DOB2	922	922	922	922	922	922
CLKB	DOB3	922	922	922	922	922	922
CLKB	DOB4	922	922	922	922	922	922
CLKB	DOB5	922	922	922	922	922	922
CLKB	DOB6	922	922	922	922	922	922
CLKB	DOB7	922	922	922	922	922	922
CLKB	DOB8	922	922	922	922	922	922

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	77	77	77
ADA1	posedge CLKA	0	0	0	77	77	77
ADA10	posedge CLKA	0	0	0	77	77	77
ADA11	posedge CLKA	0	0	0	77	77	77
ADA12	posedge CLKA	0	0	0	77	77	77
ADA2	posedge CLKA	0	0	0	77	77	77
ADA3	posedge CLKA	0	0	0	77	77	77
ADA4	posedge CLKA	0	0	0	77	77	77
ADA5	posedge CLKA	0	0	0	77	77	77
ADA6	posedge CLKA	0	0	0	77	77	77
ADA7	posedge CLKA	0	0	0	77	77	77
ADA8	posedge CLKA	0	0	0	77	77	77
ADA9	posedge CLKA	0	0	0	77	77	77
ADB0	posedge CLKB	0	0	0	169	169	169
ADB1	posedge CLKB	0	0	0	169	169	169
ADB10	posedge CLKB	0	0	0	169	169	169
ADB11	posedge CLKB	0	0	0	169	169	169
ADB12	posedge CLKB	0	0	0	169	169	169
ADB2	posedge CLKB	0	0	0	169	169	169
ADB3	posedge CLKB	0	0	0	169	169	169
ADB4	posedge CLKB	0	0	0	169	169	169
ADB5	posedge CLKB	0	0	0	169	169	169
ADB6	posedge CLKB	0	0	0	169	169	169
ADB7	posedge CLKB	0	0	0	169	169	169
ADB8	posedge CLKB	0	0	0	169	169	169
ADB9	posedge CLKB	0	0	0	169	169	169
CEA	posedge CLKA	199	199	199	0	0	0
CEB	posedge CLKB	219	219	219	0	0	0
CSA0	posedge CLKA	118	118	118	0	0	0
CSA1	posedge CLKA	118	118	118	0	0	0
CSA2	posedge CLKA	118	118	118	0	0	0
CSB0	posedge CLKB	1	1	1	87	87	87
CSB1	posedge CLKB	1	1	1	87	87	87
CSB2	posedge CLKB	1	1	1	87	87	87
DIA0	posedge CLKA	0	0	0	92	92	92
DIA1	posedge CLKA	0	0	0	92	92	92
DIA2	posedge CLKA	0	0	0	92	92	92
DIA3	posedge CLKA	0	0	0	92	92	92
DIA4	posedge CLKA	0	0	0	92	92	92
DIA5	posedge CLKA	0	0	0	92	92	92
DIA6	posedge CLKA	0	0	0	92	92	92
DIA7	posedge CLKA	0	0	0	92	92	92
DIA8	posedge CLKA	0	0	0	92	92	92
DIB0	posedge CLKB	0	0	0	175	175	175
DIB1	posedge CLKB	0	0	0	175	175	175
DIB2	posedge CLKB	0	0	0	175	175	175
DIB3	posedge CLKB	0	0	0	175	175	175
DIB4	posedge CLKB	0	0	0	175	175	175
DIB5	posedge CLKB	0	0	0	175	175	175
DIB6	posedge CLKB	0	0	0	175	175	175
DIB7	posedge CLKB	0	0	0	175	175	175
DIB8	posedge CLKB	0	0	0	175	175	175
OCEA	posedge CLKA	0	0	0	140	140	140
OCEB	posedge CLKB	0	0	0	166	166	166
RSTA	posedge CLKA	385	385	385	0	0	0
RSTB	posedge CLKB	227	227	227	32	32	32
WEA	posedge CLKA	109	109	109	0	0	0
WEB	posedge CLKB	14	14	14	45	45	45

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3036	3036	3036	165	165	165
negedge CLKB	3036	3036	3036	165	165	165
posedge CLKA	3036	3036	3036	165	165	165
posedge CLKB	3036	3036	3036	165	165	165

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4518	4518	4518	4518	4518	4518
CLKA	DOA1	4518	4518	4518	4518	4518	4518
CLKA	DOA2	4518	4518	4518	4518	4518	4518
CLKA	DOA3	4518	4518	4518	4518	4518	4518
CLKA	DOA4	4518	4518	4518	4518	4518	4518
CLKA	DOA5	4518	4518	4518	4518	4518	4518
CLKA	DOA6	4518	4518	4518	4518	4518	4518
CLKA	DOA7	4518	4518	4518	4518	4518	4518
CLKA	DOA8	4518	4518	4518	4518	4518	4518
CLKB	DOB0	4739	4739	4739	4739	4739	4739
CLKB	DOB1	4739	4739	4739	4739	4739	4739
CLKB	DOB2	4739	4739	4739	4739	4739	4739
CLKB	DOB3	4739	4739	4739	4739	4739	4739
CLKB	DOB4	4739	4739	4739	4739	4739	4739
CLKB	DOB5	4739	4739	4739	4739	4739	4739
CLKB	DOB6	4739	4739	4739	4739	4739	4739
CLKB	DOB7	4739	4739	4739	4739	4739	4739
CLKB	DOB8	4739	4739	4739	4739	4739	4739

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	77	77	77
ADA1	posedge CLKA	0	0	0	77	77	77
ADA10	posedge CLKA	0	0	0	77	77	77
ADA11	posedge CLKA	0	0	0	77	77	77
ADA12	posedge CLKA	0	0	0	77	77	77
ADA2	posedge CLKA	0	0	0	77	77	77
ADA3	posedge CLKA	0	0	0	77	77	77
ADA4	posedge CLKA	0	0	0	77	77	77
ADA5	posedge CLKA	0	0	0	77	77	77
ADA6	posedge CLKA	0	0	0	77	77	77
ADA7	posedge CLKA	0	0	0	77	77	77
ADA8	posedge CLKA	0	0	0	77	77	77
ADA9	posedge CLKA	0	0	0	77	77	77
ADB0	posedge CLKB	0	0	0	169	169	169
ADB1	posedge CLKB	0	0	0	169	169	169
ADB10	posedge CLKB	0	0	0	169	169	169
ADB11	posedge CLKB	0	0	0	169	169	169
ADB12	posedge CLKB	0	0	0	169	169	169
ADB2	posedge CLKB	0	0	0	169	169	169
ADB3	posedge CLKB	0	0	0	169	169	169
ADB4	posedge CLKB	0	0	0	169	169	169
ADB5	posedge CLKB	0	0	0	169	169	169
ADB6	posedge CLKB	0	0	0	169	169	169
ADB7	posedge CLKB	0	0	0	169	169	169
ADB8	posedge CLKB	0	0	0	169	169	169
ADB9	posedge CLKB	0	0	0	169	169	169
CEA	posedge CLKA	199	199	199	0	0	0
CEB	posedge CLKB	219	219	219	0	0	0
CSA0	posedge CLKA	118	118	118	0	0	0
CSA1	posedge CLKA	118	118	118	0	0	0
CSA2	posedge CLKA	118	118	118	0	0	0
CSB0	posedge CLKB	1	1	1	87	87	87
CSB1	posedge CLKB	1	1	1	87	87	87
CSB2	posedge CLKB	1	1	1	87	87	87
DIA0	posedge CLKA	0	0	0	92	92	92
DIA1	posedge CLKA	0	0	0	92	92	92
DIA2	posedge CLKA	0	0	0	92	92	92
DIA3	posedge CLKA	0	0	0	92	92	92
DIA4	posedge CLKA	0	0	0	92	92	92
DIA5	posedge CLKA	0	0	0	92	92	92
DIA6	posedge CLKA	0	0	0	92	92	92
DIA7	posedge CLKA	0	0	0	92	92	92
DIA8	posedge CLKA	0	0	0	92	92	92
DIB0	posedge CLKB	0	0	0	175	175	175
DIB1	posedge CLKB	0	0	0	175	175	175
DIB2	posedge CLKB	0	0	0	175	175	175
DIB3	posedge CLKB	0	0	0	175	175	175
DIB4	posedge CLKB	0	0	0	175	175	175
DIB5	posedge CLKB	0	0	0	175	175	175
DIB6	posedge CLKB	0	0	0	175	175	175
DIB7	posedge CLKB	0	0	0	175	175	175
DIB8	posedge CLKB	0	0	0	175	175	175
OCEA	posedge CLKA	0	0	0	140	140	140
OCEB	posedge CLKB	0	0	0	166	166	166
RSTA	posedge CLKA	385	385	385	0	0	0
RSTB	posedge CLKB	130	130	130	32	32	32
WEA	posedge CLKA	109	109	109	0	0	0
WEB	posedge CLKB	14	14	14	45	45	45

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3036	3036	3036	165	165	165
negedge CLKB	3036	3036	3036	165	165	165
posedge CLKA	3036	3036	3036	165	165	165
posedge CLKB	3036	3036	3036	165	165	165

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4518	4518	4518	4518	4518	4518
CLKA	DOA1	4518	4518	4518	4518	4518	4518
CLKA	DOA2	4518	4518	4518	4518	4518	4518
CLKA	DOA3	4518	4518	4518	4518	4518	4518
CLKA	DOA4	4518	4518	4518	4518	4518	4518
CLKA	DOA5	4518	4518	4518	4518	4518	4518
CLKA	DOA6	4518	4518	4518	4518	4518	4518
CLKA	DOA7	4518	4518	4518	4518	4518	4518
CLKA	DOA8	4518	4518	4518	4518	4518	4518
CLKB	DOB0	4739	4739	4739	4739	4739	4739
CLKB	DOB1	4739	4739	4739	4739	4739	4739
CLKB	DOB2	4739	4739	4739	4739	4739	4739
CLKB	DOB3	4739	4739	4739	4739	4739	4739
CLKB	DOB4	4739	4739	4739	4739	4739	4739
CLKB	DOB5	4739	4739	4739	4739	4739	4739
CLKB	DOB6	4739	4739	4739	4739	4739	4739
CLKB	DOB7	4739	4739	4739	4739	4739	4739
CLKB	DOB8	4739	4739	4739	4739	4739	4739

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	77	77	77
ADA1	posedge CLKA	0	0	0	77	77	77
ADA10	posedge CLKA	0	0	0	77	77	77
ADA11	posedge CLKA	0	0	0	77	77	77
ADA12	posedge CLKA	0	0	0	77	77	77
ADA2	posedge CLKA	0	0	0	77	77	77
ADA3	posedge CLKA	0	0	0	77	77	77
ADA4	posedge CLKA	0	0	0	77	77	77
ADA5	posedge CLKA	0	0	0	77	77	77
ADA6	posedge CLKA	0	0	0	77	77	77
ADA7	posedge CLKA	0	0	0	77	77	77
ADA8	posedge CLKA	0	0	0	77	77	77
ADA9	posedge CLKA	0	0	0	77	77	77
ADB0	posedge CLKB	0	0	0	169	169	169
ADB1	posedge CLKB	0	0	0	169	169	169
ADB10	posedge CLKB	0	0	0	169	169	169
ADB11	posedge CLKB	0	0	0	169	169	169
ADB12	posedge CLKB	0	0	0	169	169	169
ADB2	posedge CLKB	0	0	0	169	169	169
ADB3	posedge CLKB	0	0	0	169	169	169
ADB4	posedge CLKB	0	0	0	169	169	169
ADB5	posedge CLKB	0	0	0	169	169	169
ADB6	posedge CLKB	0	0	0	169	169	169
ADB7	posedge CLKB	0	0	0	169	169	169
ADB8	posedge CLKB	0	0	0	169	169	169
ADB9	posedge CLKB	0	0	0	169	169	169
CEA	posedge CLKA	199	199	199	0	0	0
CEB	posedge CLKB	219	219	219	0	0	0
CSA0	posedge CLKA	118	118	118	0	0	0
CSA1	posedge CLKA	118	118	118	0	0	0
CSA2	posedge CLKA	118	118	118	0	0	0
CSB0	posedge CLKB	1	1	1	87	87	87
CSB1	posedge CLKB	1	1	1	87	87	87
CSB2	posedge CLKB	1	1	1	87	87	87
DIA0	posedge CLKA	0	0	0	92	92	92
DIA1	posedge CLKA	0	0	0	92	92	92
DIA2	posedge CLKA	0	0	0	92	92	92
DIA3	posedge CLKA	0	0	0	92	92	92
DIA4	posedge CLKA	0	0	0	92	92	92
DIA5	posedge CLKA	0	0	0	92	92	92
DIA6	posedge CLKA	0	0	0	92	92	92
DIA7	posedge CLKA	0	0	0	92	92	92
DIA8	posedge CLKA	0	0	0	92	92	92
DIB0	posedge CLKB	0	0	0	175	175	175
DIB1	posedge CLKB	0	0	0	175	175	175
DIB2	posedge CLKB	0	0	0	175	175	175
DIB3	posedge CLKB	0	0	0	175	175	175
DIB4	posedge CLKB	0	0	0	175	175	175
DIB5	posedge CLKB	0	0	0	175	175	175
DIB6	posedge CLKB	0	0	0	175	175	175
DIB7	posedge CLKB	0	0	0	175	175	175
DIB8	posedge CLKB	0	0	0	175	175	175
OCEA	posedge CLKA	0	0	0	140	140	140
OCEB	posedge CLKB	0	0	0	166	166	166
RSTA	posedge CLKA	385	385	385	0	0	0
RSTB	posedge CLKB	130	130	130	32	32	32
WEA	posedge CLKA	109	109	109	0	0	0
WEB	posedge CLKB	14	14	14	45	45	45

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3036	3036	3036	165	165	165
negedge CLKB	4623	4623	4623	108	108	108
posedge CLKA	3036	3036	3036	165	165	165
posedge CLKB	4623	4623	4623	108	108	108

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4518	4518	4518	4518	4518	4518
CLKA	DOA1	4518	4518	4518	4518	4518	4518
CLKA	DOA2	4518	4518	4518	4518	4518	4518
CLKA	DOA3	4518	4518	4518	4518	4518	4518
CLKA	DOA4	4518	4518	4518	4518	4518	4518
CLKA	DOA5	4518	4518	4518	4518	4518	4518
CLKA	DOA6	4518	4518	4518	4518	4518	4518
CLKA	DOA7	4518	4518	4518	4518	4518	4518
CLKA	DOA8	4518	4518	4518	4518	4518	4518
CLKB	DOB0	4739	4739	4739	4739	4739	4739
CLKB	DOB1	4739	4739	4739	4739	4739	4739
CLKB	DOB2	4739	4739	4739	4739	4739	4739
CLKB	DOB3	4739	4739	4739	4739	4739	4739
CLKB	DOB4	4739	4739	4739	4739	4739	4739
CLKB	DOB5	4739	4739	4739	4739	4739	4739
CLKB	DOB6	4739	4739	4739	4739	4739	4739
CLKB	DOB7	4739	4739	4739	4739	4739	4739
CLKB	DOB8	4739	4739	4739	4739	4739	4739

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	77	77	77
ADA1	posedge CLKA	0	0	0	77	77	77
ADA10	posedge CLKA	0	0	0	77	77	77
ADA11	posedge CLKA	0	0	0	77	77	77
ADA12	posedge CLKA	0	0	0	77	77	77
ADA2	posedge CLKA	0	0	0	77	77	77
ADA3	posedge CLKA	0	0	0	77	77	77
ADA4	posedge CLKA	0	0	0	77	77	77
ADA5	posedge CLKA	0	0	0	77	77	77
ADA6	posedge CLKA	0	0	0	77	77	77
ADA7	posedge CLKA	0	0	0	77	77	77
ADA8	posedge CLKA	0	0	0	77	77	77
ADA9	posedge CLKA	0	0	0	77	77	77
ADB0	posedge CLKB	0	0	0	169	169	169
ADB1	posedge CLKB	0	0	0	169	169	169
ADB10	posedge CLKB	0	0	0	169	169	169
ADB11	posedge CLKB	0	0	0	169	169	169
ADB12	posedge CLKB	0	0	0	169	169	169
ADB2	posedge CLKB	0	0	0	169	169	169
ADB3	posedge CLKB	0	0	0	169	169	169
ADB4	posedge CLKB	0	0	0	169	169	169
ADB5	posedge CLKB	0	0	0	169	169	169
ADB6	posedge CLKB	0	0	0	169	169	169
ADB7	posedge CLKB	0	0	0	169	169	169
ADB8	posedge CLKB	0	0	0	169	169	169
ADB9	posedge CLKB	0	0	0	169	169	169
CEA	posedge CLKA	199	199	199	0	0	0
CEB	posedge CLKB	219	219	219	0	0	0
CSA0	posedge CLKA	118	118	118	0	0	0
CSA1	posedge CLKA	118	118	118	0	0	0
CSA2	posedge CLKA	118	118	118	0	0	0
CSB0	posedge CLKB	1	1	1	87	87	87
CSB1	posedge CLKB	1	1	1	87	87	87
CSB2	posedge CLKB	1	1	1	87	87	87
DIA0	posedge CLKA	0	0	0	92	92	92
DIA1	posedge CLKA	0	0	0	92	92	92
DIA2	posedge CLKA	0	0	0	92	92	92
DIA3	posedge CLKA	0	0	0	92	92	92
DIA4	posedge CLKA	0	0	0	92	92	92
DIA5	posedge CLKA	0	0	0	92	92	92
DIA6	posedge CLKA	0	0	0	92	92	92
DIA7	posedge CLKA	0	0	0	92	92	92
DIA8	posedge CLKA	0	0	0	92	92	92
DIB0	posedge CLKB	0	0	0	175	175	175
DIB1	posedge CLKB	0	0	0	175	175	175
DIB2	posedge CLKB	0	0	0	175	175	175
DIB3	posedge CLKB	0	0	0	175	175	175
DIB4	posedge CLKB	0	0	0	175	175	175
DIB5	posedge CLKB	0	0	0	175	175	175
DIB6	posedge CLKB	0	0	0	175	175	175
DIB7	posedge CLKB	0	0	0	175	175	175
DIB8	posedge CLKB	0	0	0	175	175	175
OCEA	posedge CLKA	0	0	0	140	140	140
OCEB	posedge CLKB	0	0	0	166	166	166
RSTA	posedge CLKA	385	385	385	0	0	0
RSTB	posedge CLKB	130	130	130	32	32	32
WEA	posedge CLKA	109	109	109	0	0	0
WEB	posedge CLKB	14	14	14	45	45	45

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	3036	3036	3036	165	165	165
negedge CLKB	3036	3036	3036	165	165	165
posedge CLKA	3036	3036	3036	165	165	165
posedge CLKB	3036	3036	3036	165	165	165

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1037	1176	1315	1037	1176	1315
PADDO	PAD	7624	7699	7774	7624	7699	7774
PADDT	PAD	4397	8598	12800	4397	8598	12800

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	5500	5500	5500	91	91	91
posedge PAD	5500	5500	5500	91	91	91

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2298	2340	2383	2298	2340	2383
PADDO	PAD	4875	5041	5207	4875	5041	5207
PADDT	PAD	3221	5476	7732	3221	5476	7732

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1740	1753	1767	1740	1753	1767
PADDO	PAD	3735	3891	4048	3735	3891	4048
PADDT	PAD	2742	4200	5658	2742	4200	5658

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1223	1297	1372	1223	1297	1372
PADDO	PAD	3220	3334	3448	3220	3334	3448
PADDT	PAD	2349	3502	4656	2349	3502	4656

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1007	1069	1132	1007	1069	1132
PADDO	PAD	2611	2704	2797	2611	2704	2797
PADDT	PAD	2387	3283	4180	2387	3283	4180

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1282	1330	1378	1282	1330	1378
PADDO	PAD	3136	3311	3486	3136	3311	3486
PADDT	PAD	3754	4790	5827	3754	4790	5827

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1087	1105	1123	1087	1105	1123
PADDO	PAD	2803	2803	2804	2803	2803	2804
PADDT	PAD	2906	4040	5174	2906	4040	5174

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

SLICE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	324	388	452	324	388	452
A0	F1	635	710	786	635	710	786
A0	FCO	732	818	905	732	818	905
A0	OFX0	447	554	661	447	554	661
A1	F1	324	388	452	324	388	452
A1	FCO	635	710	786	635	710	786
A1	OFX0	447	554	661	447	554	661
B0	F0	324	388	452	324	388	452
B0	F1	635	710	786	635	710	786
B0	FCO	732	818	905	732	818	905
B0	OFX0	447	554	661	447	554	661
B1	F1	324	388	452	324	388	452
B1	FCO	635	710	786	635	710	786
B1	OFX0	447	554	661	447	554	661
C0	F0	324	388	452	324	388	452
C0	F1	635	710	786	635	710	786
C0	FCO	732	818	905	732	818	905
C0	OFX0	447	554	661	447	554	661
C1	F1	324	388	452	324	388	452
C1	FCO	635	710	786	635	710	786
C1	OFX0	447	554	661	447	554	661
CLK	Q0	356	382	409	356	382	409
CLK	Q1	356	382	409	356	382	409
D0	F0	324	388	452	324	388	452
D0	F1	635	710	786	635	710	786
D0	FCO	732	818	905	732	818	905
D0	OFX0	447	554	661	447	554	661
D1	F1	324	388	452	324	388	452
D1	FCO	635	710	786	635	710	786
D1	OFX0	447	554	661	447	554	661
FCI	F0	418	467	517	418	467	517
FCI	F1	459	514	569	459	514	569
FCI	FCO	112	129	146	112	129	146
FXA	OFX1	181	202	223	181	202	223
FXB	OFX1	181	202	223	181	202	223
LSR	Q0	698	779	861	698	779	861
M0	OFX0	285	315	345	285	315	345
M1	OFX1	285	315	345	285	315	345
WCK	F0	960	1097	1234	960	1097	1234
WCK	F1	960	1097	1234	960	1097	1234

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	negedge CLK	218	244	271	0	0	0
CE	posedge CLK	203	226	249	0	0	0
DI0	negedge CLK	117	133	150	0	0	0
DI0	posedge CLK	117	133	150	0	0	0
DI1	posedge CLK	117	133	150	0	0	0
LSR	negedge CLK	213	235	257	0	0	0
LSR	posedge CLK	206	227	248	0	0	0
LSR	posedge CLK	648	648	648	0	0	0
M0	posedge CLK	229	266	303	0	0	0
M1	negedge CLK	229	266	303	0	0	0
M1	posedge CLK	229	266	303	0	0	0
WAD0	posedge WCK	0	0	0	427	451	476
WAD1	posedge WCK	0	0	0	427	451	476
WAD2	posedge WCK	0	0	0	427	451	476
WAD3	posedge WCK	0	0	0	427	451	476
WD0	posedge WCK	0	0	0	432	456	481
WD1	posedge WCK	0	0	0	432	456	481
WRE	posedge WCK	121	137	153	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1125	1125	1125	444	444	444
negedge LSR	3500	3500	3500	143	143	143
negedge WCK	1125	1125	1125	444	444	444
posedge CLK	1125	1125	1125	444	444	444
posedge LSR	3500	3500	3500	143	143	143
posedge WCK	1125	1125	1125	444	444	444

MachXO2 Speed Grade -5 Cell Timings

Contents

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS25

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS33

Propagation Delays

Width Checks

PIO:IOTYPE=LVDS

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_II

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_II

Propagation Delays

Width Checks

SLICE

Propagation Delays

Setup/Hold Checks

Width Checks