MachXO2 Speed Grade -3 Cell Timings

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SLICE

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	7995	7995	7995	7995	7995	7995
CLKA	DOA1	7995	7995	7995	7995	7995	7995
CLKA	DOA2	7995	7995	7995	7995	7995	7995
CLKA	DOA3	7995	7995	7995	7995	7995	7995
CLKA	DOA4	7995	7995	7995	7995	7995	7995
CLKA	DOA5	7995	7995	7995	7995	7995	7995
CLKA	DOA6	7995	7995	7995	7995	7995	7995
CLKA	DOA7	7995	7995	7995	7995	7995	7995
CLKA	DOA8	7995	7995	7995	7995	7995	7995
CLKB	DOB0	8506	8506	8506	8506	8506	8506
CLKB	DOB1	8506	8506	8506	8506	8506	8506
CLKB	DOB2	8506	8506	8506	8506	8506	8506
CLKB	DOB3	8506	8506	8506	8506	8506	8506
CLKB	DOB4	8506	8506	8506	8506	8506	8506
CLKB	DOB5	8506	8506	8506	8506	8506	8506
CLKB	DOB6	8506	8506	8506	8506	8506	8506
CLKB	DOB7	8506	8506	8506	8506	8506	8506
CLKB	DOB8	8506	8506	8506	8506	8506	8506

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	207	207	207
ADA1	posedge CLKA	0	0	0	207	207	207
ADA10	posedge CLKA	0	0	0	207	207	207
ADA11	posedge CLKA	0	0	0	207	207	207
ADA12	posedge CLKA	0	0	0	207	207	207
ADA2	posedge CLKA	0	0	0	207	207	207
ADA3	posedge CLKA	0	0	0	207	207	207
ADA4	posedge CLKA	0	0	0	207	207	207
ADA5	posedge CLKA	0	0	0	207	207	207
ADA6	posedge CLKA	0	0	0	207	207	207
ADA7	posedge CLKA	0	0	0	207	207	207
ADA8	posedge CLKA	0	0	0	207	207	207
ADA9	posedge CLKA	0	0	0	207	207	207
ADB0	posedge CLKB	0	0	0	411	411	411
ADB1	posedge CLKB	0	0	0	411	411	411
ADB10	posedge CLKB	0	0	0	411	411	411
ADB11	posedge CLKB	0	0	0	411	411	411
ADB12	posedge CLKB	0	0	0	411	411	411
ADB2	posedge CLKB	0	0	0	411	411	411
ADB3	posedge CLKB	0	0	0	411	411	411
ADB4	posedge CLKB	0	0	0	411	411	411
ADB5	posedge CLKB	0	0	0	411	411	411
ADB6	posedge CLKB	0	0	0	411	411	411
ADB7	posedge CLKB	0	0	0	411	411	411
ADB8	posedge CLKB	0	0	0	411	411	411
ADB9	posedge CLKB	0	0	0	411	411	411
CEA	posedge CLKA	133	133	133	0	0	0
CEB	posedge CLKB	100	100	100	0	0	0
CSA0	posedge CLKA	297	297	297	0	0	0
CSA1	posedge CLKA	297	297	297	0	0	0
CSA2	posedge CLKA	297	297	297	0	0	0
CSB0	posedge CLKB	0	0	0	32	32	32
CSB1	posedge CLKB	0	0	0	32	32	32
CSB2	posedge CLKB	0	0	0	32	32	32
DIA0	posedge CLKA	0	0	0	245	245	245
DIA1	posedge CLKA	0	0	0	245	245	245
DIA2	posedge CLKA	0	0	0	245	245	245
DIA3	posedge CLKA	0	0	0	245	245	245
DIA4	posedge CLKA	0	0	0	245	245	245
DIA5	posedge CLKA	0	0	0	245	245	245
DIA6	posedge CLKA	0	0	0	245	245	245
DIA7	posedge CLKA	0	0	0	245	245	245
DIA8	posedge CLKA	0	0	0	245	245	245
DIB0	posedge CLKB	0	0	0	422	422	422
DIB1	posedge CLKB	0	0	0	422	422	422
DIB2	posedge CLKB	0	0	0	422	422	422
DIB3	posedge CLKB	0	0	0	422	422	422
DIB4	posedge CLKB	0	0	0	422	422	422
DIB5	posedge CLKB	0	0	0	422	422	422
DIB6	posedge CLKB	0	0	0	422	422	422
DIB7	posedge CLKB	0	0	0	422	422	422
DIB8	posedge CLKB	0	0	0	422	422	422
OCEA	posedge CLKA	133	133	133	0	0	0
OCEB	posedge CLKB	100	100	100	0	0	0
RSTA	posedge CLKA	684	684	684	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	266	266	266	0	0	0
WEB	posedge CLKB	0	0	0	129	129	129

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	5555	5555	5555	90	90	90
negedge CLKB	5555	5555	5555	90	90	90
posedge CLKA	5555	5555	5555	90	90	90
posedge CLKB	5555	5555	5555	90	90	90

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	7995	7995	7995	7995	7995	7995
CLKA	DOA1	7995	7995	7995	7995	7995	7995
CLKA	DOA2	7995	7995	7995	7995	7995	7995
CLKA	DOA3	7995	7995	7995	7995	7995	7995
CLKA	DOA4	7995	7995	7995	7995	7995	7995
CLKA	DOA5	7995	7995	7995	7995	7995	7995
CLKA	DOA6	7995	7995	7995	7995	7995	7995
CLKA	DOA7	7995	7995	7995	7995	7995	7995
CLKA	DOA8	7995	7995	7995	7995	7995	7995
CLKB	DOB0	1950	1950	1950	1950	1950	1950
CLKB	DOB1	1950	1950	1950	1950	1950	1950
CLKB	DOB2	1950	1950	1950	1950	1950	1950
CLKB	DOB3	1950	1950	1950	1950	1950	1950
CLKB	DOB4	1950	1950	1950	1950	1950	1950
CLKB	DOB5	1950	1950	1950	1950	1950	1950
CLKB	DOB6	1950	1950	1950	1950	1950	1950
CLKB	DOB7	1950	1950	1950	1950	1950	1950
CLKB	DOB8	1950	1950	1950	1950	1950	1950

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	207	207	207
ADA1	posedge CLKA	0	0	0	207	207	207
ADA10	posedge CLKA	0	0	0	207	207	207
ADA11	posedge CLKA	0	0	0	207	207	207
ADA12	posedge CLKA	0	0	0	207	207	207
ADA2	posedge CLKA	0	0	0	207	207	207
ADA3	posedge CLKA	0	0	0	207	207	207
ADA4	posedge CLKA	0	0	0	207	207	207
ADA5	posedge CLKA	0	0	0	207	207	207
ADA6	posedge CLKA	0	0	0	207	207	207
ADA7	posedge CLKA	0	0	0	207	207	207
ADA8	posedge CLKA	0	0	0	207	207	207
ADA9	posedge CLKA	0	0	0	207	207	207
ADB0	posedge CLKB	0	0	0	411	411	411
ADB1	posedge CLKB	0	0	0	411	411	411
ADB10	posedge CLKB	0	0	0	411	411	411
ADB11	posedge CLKB	0	0	0	411	411	411
ADB12	posedge CLKB	0	0	0	411	411	411
ADB2	posedge CLKB	0	0	0	411	411	411
ADB3	posedge CLKB	0	0	0	411	411	411
ADB4	posedge CLKB	0	0	0	411	411	411
ADB5	posedge CLKB	0	0	0	411	411	411
ADB6	posedge CLKB	0	0	0	411	411	411
ADB7	posedge CLKB	0	0	0	411	411	411
ADB8	posedge CLKB	0	0	0	411	411	411
ADB9	posedge CLKB	0	0	0	411	411	411
CEA	posedge CLKA	133	133	133	0	0	0
CEB	posedge CLKB	100	100	100	0	0	0
CSA0	posedge CLKA	297	297	297	0	0	0
CSA1	posedge CLKA	297	297	297	0	0	0
CSA2	posedge CLKA	297	297	297	0	0	0
CSB0	posedge CLKB	0	0	0	32	32	32
CSB1	posedge CLKB	0	0	0	32	32	32
CSB2	posedge CLKB	0	0	0	32	32	32
DIA0	posedge CLKA	0	0	0	245	245	245
DIA1	posedge CLKA	0	0	0	245	245	245
DIA2	posedge CLKA	0	0	0	245	245	245
DIA3	posedge CLKA	0	0	0	245	245	245
DIA4	posedge CLKA	0	0	0	245	245	245
DIA5	posedge CLKA	0	0	0	245	245	245
DIA6	posedge CLKA	0	0	0	245	245	245
DIA7	posedge CLKA	0	0	0	245	245	245
DIA8	posedge CLKA	0	0	0	245	245	245
DIB0	posedge CLKB	0	0	0	422	422	422
DIB1	posedge CLKB	0	0	0	422	422	422
DIB2	posedge CLKB	0	0	0	422	422	422
DIB3	posedge CLKB	0	0	0	422	422	422
DIB4	posedge CLKB	0	0	0	422	422	422
DIB5	posedge CLKB	0	0	0	422	422	422
DIB6	posedge CLKB	0	0	0	422	422	422
DIB7	posedge CLKB	0	0	0	422	422	422
DIB8	posedge CLKB	0	0	0	422	422	422
OCEA	posedge CLKA	133	133	133	0	0	0
OCEB	posedge CLKB	100	100	100	0	0	0
RSTA	posedge CLKA	684	684	684	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	266	266	266	0	0	0
WEB	posedge CLKB	0	0	0	129	129	129

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	5555	5555	5555	90	90	90
negedge CLKB	5555	5555	5555	90	90	90
posedge CLKA	5555	5555	5555	90	90	90
posedge CLKB	5555	5555	5555	90	90	90

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	1900	1900	1900	1900	1900	1900
CLKA	DOA1	1900	1900	1900	1900	1900	1900
CLKA	DOA2	1900	1900	1900	1900	1900	1900
CLKA	DOA3	1900	1900	1900	1900	1900	1900
CLKA	DOA4	1900	1900	1900	1900	1900	1900
CLKA	DOA5	1900	1900	1900	1900	1900	1900
CLKA	DOA6	1900	1900	1900	1900	1900	1900
CLKA	DOA7	1900	1900	1900	1900	1900	1900
CLKA	DOA8	1900	1900	1900	1900	1900	1900
CLKB	DOB0	8506	8506	8506	8506	8506	8506
CLKB	DOB1	8506	8506	8506	8506	8506	8506
CLKB	DOB2	8506	8506	8506	8506	8506	8506
CLKB	DOB3	8506	8506	8506	8506	8506	8506
CLKB	DOB4	8506	8506	8506	8506	8506	8506
CLKB	DOB5	8506	8506	8506	8506	8506	8506
CLKB	DOB6	8506	8506	8506	8506	8506	8506
CLKB	DOB7	8506	8506	8506	8506	8506	8506
CLKB	DOB8	8506	8506	8506	8506	8506	8506

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	207	207	207
ADA1	posedge CLKA	0	0	0	207	207	207
ADA10	posedge CLKA	0	0	0	207	207	207
ADA11	posedge CLKA	0	0	0	207	207	207
ADA12	posedge CLKA	0	0	0	207	207	207
ADA2	posedge CLKA	0	0	0	207	207	207
ADA3	posedge CLKA	0	0	0	207	207	207
ADA4	posedge CLKA	0	0	0	207	207	207
ADA5	posedge CLKA	0	0	0	207	207	207
ADA6	posedge CLKA	0	0	0	207	207	207
ADA7	posedge CLKA	0	0	0	207	207	207
ADA8	posedge CLKA	0	0	0	207	207	207
ADA9	posedge CLKA	0	0	0	207	207	207
ADB0	posedge CLKB	0	0	0	411	411	411
ADB1	posedge CLKB	0	0	0	411	411	411
ADB10	posedge CLKB	0	0	0	411	411	411
ADB11	posedge CLKB	0	0	0	411	411	411
ADB12	posedge CLKB	0	0	0	411	411	411
ADB2	posedge CLKB	0	0	0	411	411	411
ADB3	posedge CLKB	0	0	0	411	411	411
ADB4	posedge CLKB	0	0	0	411	411	411
ADB5	posedge CLKB	0	0	0	411	411	411
ADB6	posedge CLKB	0	0	0	411	411	411
ADB7	posedge CLKB	0	0	0	411	411	411
ADB8	posedge CLKB	0	0	0	411	411	411
ADB9	posedge CLKB	0	0	0	411	411	411
CEA	posedge CLKA	133	133	133	0	0	0
CEB	posedge CLKB	100	100	100	0	0	0
CSA0	posedge CLKA	297	297	297	0	0	0
CSA1	posedge CLKA	297	297	297	0	0	0
CSA2	posedge CLKA	297	297	297	0	0	0
CSB0	posedge CLKB	0	0	0	32	32	32
CSB1	posedge CLKB	0	0	0	32	32	32
CSB2	posedge CLKB	0	0	0	32	32	32
DIA0	posedge CLKA	0	0	0	245	245	245
DIA1	posedge CLKA	0	0	0	245	245	245
DIA2	posedge CLKA	0	0	0	245	245	245
DIA3	posedge CLKA	0	0	0	245	245	245
DIA4	posedge CLKA	0	0	0	245	245	245
DIA5	posedge CLKA	0	0	0	245	245	245
DIA6	posedge CLKA	0	0	0	245	245	245
DIA7	posedge CLKA	0	0	0	245	245	245
DIA8	posedge CLKA	0	0	0	245	245	245
DIB0	posedge CLKB	0	0	0	422	422	422
DIB1	posedge CLKB	0	0	0	422	422	422
DIB2	posedge CLKB	0	0	0	422	422	422
DIB3	posedge CLKB	0	0	0	422	422	422
DIB4	posedge CLKB	0	0	0	422	422	422
DIB5	posedge CLKB	0	0	0	422	422	422
DIB6	posedge CLKB	0	0	0	422	422	422
DIB7	posedge CLKB	0	0	0	422	422	422
DIB8	posedge CLKB	0	0	0	422	422	422
OCEA	posedge CLKA	133	133	133	0	0	0
OCEB	posedge CLKB	100	100	100	0	0	0
RSTA	posedge CLKA	684	684	684	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	266	266	266	0	0	0
WEB	posedge CLKB	0	0	0	129	129	129

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	5555	5555	5555	90	90	90
negedge CLKB	5555	5555	5555	90	90	90
posedge CLKA	5555	5555	5555	90	90	90
posedge CLKB	5555	5555	5555	90	90	90

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	1900	1900	1900	1900	1900	1900
CLKA	DOA1	1900	1900	1900	1900	1900	1900
CLKA	DOA2	1900	1900	1900	1900	1900	1900
CLKA	DOA3	1900	1900	1900	1900	1900	1900
CLKA	DOA4	1900	1900	1900	1900	1900	1900
CLKA	DOA5	1900	1900	1900	1900	1900	1900
CLKA	DOA6	1900	1900	1900	1900	1900	1900
CLKA	DOA7	1900	1900	1900	1900	1900	1900
CLKA	DOA8	1900	1900	1900	1900	1900	1900
CLKB	DOB0	1950	1950	1950	1950	1950	1950
CLKB	DOB1	1950	1950	1950	1950	1950	1950
CLKB	DOB2	1950	1950	1950	1950	1950	1950
CLKB	DOB3	1950	1950	1950	1950	1950	1950
CLKB	DOB4	1950	1950	1950	1950	1950	1950
CLKB	DOB5	1950	1950	1950	1950	1950	1950
CLKB	DOB6	1950	1950	1950	1950	1950	1950
CLKB	DOB7	1950	1950	1950	1950	1950	1950
CLKB	DOB8	1950	1950	1950	1950	1950	1950

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	207	207	207
ADA1	posedge CLKA	0	0	0	207	207	207
ADA10	posedge CLKA	0	0	0	207	207	207
ADA11	posedge CLKA	0	0	0	207	207	207
ADA12	posedge CLKA	0	0	0	207	207	207
ADA2	posedge CLKA	0	0	0	207	207	207
ADA3	posedge CLKA	0	0	0	207	207	207
ADA4	posedge CLKA	0	0	0	207	207	207
ADA5	posedge CLKA	0	0	0	207	207	207
ADA6	posedge CLKA	0	0	0	207	207	207
ADA7	posedge CLKA	0	0	0	207	207	207
ADA8	posedge CLKA	0	0	0	207	207	207
ADA9	posedge CLKA	0	0	0	207	207	207
ADB0	posedge CLKB	0	0	0	411	411	411
ADB1	posedge CLKB	0	0	0	411	411	411
ADB10	posedge CLKB	0	0	0	411	411	411
ADB11	posedge CLKB	0	0	0	411	411	411
ADB12	posedge CLKB	0	0	0	411	411	411
ADB2	posedge CLKB	0	0	0	411	411	411
ADB3	posedge CLKB	0	0	0	411	411	411
ADB4	posedge CLKB	0	0	0	411	411	411
ADB5	posedge CLKB	0	0	0	411	411	411
ADB6	posedge CLKB	0	0	0	411	411	411
ADB7	posedge CLKB	0	0	0	411	411	411
ADB8	posedge CLKB	0	0	0	411	411	411
ADB9	posedge CLKB	0	0	0	411	411	411
CEA	posedge CLKA	133	133	133	0	0	0
CEB	posedge CLKB	100	100	100	0	0	0
CSA0	posedge CLKA	297	297	297	0	0	0
CSA1	posedge CLKA	297	297	297	0	0	0
CSA2	posedge CLKA	297	297	297	0	0	0
CSB0	posedge CLKB	0	0	0	32	32	32
CSB1	posedge CLKB	0	0	0	32	32	32
CSB2	posedge CLKB	0	0	0	32	32	32
DIA0	posedge CLKA	0	0	0	245	245	245
DIA1	posedge CLKA	0	0	0	245	245	245
DIA2	posedge CLKA	0	0	0	245	245	245
DIA3	posedge CLKA	0	0	0	245	245	245
DIA4	posedge CLKA	0	0	0	245	245	245
DIA5	posedge CLKA	0	0	0	245	245	245
DIA6	posedge CLKA	0	0	0	245	245	245
DIA7	posedge CLKA	0	0	0	245	245	245
DIA8	posedge CLKA	0	0	0	245	245	245
DIB0	posedge CLKB	0	0	0	422	422	422
DIB1	posedge CLKB	0	0	0	422	422	422
DIB2	posedge CLKB	0	0	0	422	422	422
DIB3	posedge CLKB	0	0	0	422	422	422
DIB4	posedge CLKB	0	0	0	422	422	422
DIB5	posedge CLKB	0	0	0	422	422	422
DIB6	posedge CLKB	0	0	0	422	422	422
DIB7	posedge CLKB	0	0	0	422	422	422
DIB8	posedge CLKB	0	0	0	422	422	422
OCEA	posedge CLKA	133	133	133	0	0	0
OCEB	posedge CLKB	100	100	100	0	0	0
RSTA	posedge CLKA	684	684	684	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	266	266	266	0	0	0
WEB	posedge CLKB	0	0	0	129	129	129

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	5555	5555	5555	90	90	90
negedge CLKB	5555	5555	5555	90	90	90
posedge CLKA	5555	5555	5555	90	90	90
posedge CLKB	5555	5555	5555	90	90	90

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	7995	7995	7995	7995	7995	7995
CLKA	DOA1	7995	7995	7995	7995	7995	7995
CLKA	DOA2	7995	7995	7995	7995	7995	7995
CLKA	DOA3	7995	7995	7995	7995	7995	7995
CLKA	DOA4	7995	7995	7995	7995	7995	7995
CLKA	DOA5	7995	7995	7995	7995	7995	7995
CLKA	DOA6	7995	7995	7995	7995	7995	7995
CLKA	DOA7	7995	7995	7995	7995	7995	7995
CLKA	DOA8	7995	7995	7995	7995	7995	7995
CLKB	DOB0	8506	8506	8506	8506	8506	8506
CLKB	DOB1	8506	8506	8506	8506	8506	8506
CLKB	DOB2	8506	8506	8506	8506	8506	8506
CLKB	DOB3	8506	8506	8506	8506	8506	8506
CLKB	DOB4	8506	8506	8506	8506	8506	8506
CLKB	DOB5	8506	8506	8506	8506	8506	8506
CLKB	DOB6	8506	8506	8506	8506	8506	8506
CLKB	DOB7	8506	8506	8506	8506	8506	8506
CLKB	DOB8	8506	8506	8506	8506	8506	8506

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	207	207	207
ADA1	posedge CLKA	0	0	0	207	207	207
ADA10	posedge CLKA	0	0	0	207	207	207
ADA11	posedge CLKA	0	0	0	207	207	207
ADA12	posedge CLKA	0	0	0	207	207	207
ADA2	posedge CLKA	0	0	0	207	207	207
ADA3	posedge CLKA	0	0	0	207	207	207
ADA4	posedge CLKA	0	0	0	207	207	207
ADA5	posedge CLKA	0	0	0	207	207	207
ADA6	posedge CLKA	0	0	0	207	207	207
ADA7	posedge CLKA	0	0	0	207	207	207
ADA8	posedge CLKA	0	0	0	207	207	207
ADA9	posedge CLKA	0	0	0	207	207	207
ADB0	posedge CLKB	0	0	0	411	411	411
ADB1	posedge CLKB	0	0	0	411	411	411
ADB10	posedge CLKB	0	0	0	411	411	411
ADB11	posedge CLKB	0	0	0	411	411	411
ADB12	posedge CLKB	0	0	0	411	411	411
ADB2	posedge CLKB	0	0	0	411	411	411
ADB3	posedge CLKB	0	0	0	411	411	411
ADB4	posedge CLKB	0	0	0	411	411	411
ADB5	posedge CLKB	0	0	0	411	411	411
ADB6	posedge CLKB	0	0	0	411	411	411
ADB7	posedge CLKB	0	0	0	411	411	411
ADB8	posedge CLKB	0	0	0	411	411	411
ADB9	posedge CLKB	0	0	0	411	411	411
CEA	posedge CLKA	133	133	133	0	0	0
CEB	posedge CLKB	100	100	100	0	0	0
CSA0	posedge CLKA	297	297	297	0	0	0
CSA1	posedge CLKA	297	297	297	0	0	0
CSA2	posedge CLKA	297	297	297	0	0	0
CSB0	posedge CLKB	0	0	0	32	32	32
CSB1	posedge CLKB	0	0	0	32	32	32
CSB2	posedge CLKB	0	0	0	32	32	32
DIA0	posedge CLKA	0	0	0	245	245	245
DIA1	posedge CLKA	0	0	0	245	245	245
DIA2	posedge CLKA	0	0	0	245	245	245
DIA3	posedge CLKA	0	0	0	245	245	245
DIA4	posedge CLKA	0	0	0	245	245	245
DIA5	posedge CLKA	0	0	0	245	245	245
DIA6	posedge CLKA	0	0	0	245	245	245
DIA7	posedge CLKA	0	0	0	245	245	245
DIA8	posedge CLKA	0	0	0	245	245	245
DIB0	posedge CLKB	0	0	0	422	422	422
DIB1	posedge CLKB	0	0	0	422	422	422
DIB2	posedge CLKB	0	0	0	422	422	422
DIB3	posedge CLKB	0	0	0	422	422	422
DIB4	posedge CLKB	0	0	0	422	422	422
DIB5	posedge CLKB	0	0	0	422	422	422
DIB6	posedge CLKB	0	0	0	422	422	422
DIB7	posedge CLKB	0	0	0	422	422	422
DIB8	posedge CLKB	0	0	0	422	422	422
OCEA	posedge CLKA	133	133	133	0	0	0
OCEB	posedge CLKB	100	100	100	0	0	0
RSTA	posedge CLKA	684	684	684	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	266	266	266	0	0	0
WEB	posedge CLKB	0	0	0	129	129	129

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	5555	5555	5555	90	90	90
negedge CLKB	5555	5555	5555	90	90	90
posedge CLKA	5555	5555	5555	90	90	90
posedge CLKB	5555	5555	5555	90	90	90

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	7995	7995	7995	7995	7995	7995
CLKA	DOA1	7995	7995	7995	7995	7995	7995
CLKA	DOA2	7995	7995	7995	7995	7995	7995
CLKA	DOA3	7995	7995	7995	7995	7995	7995
CLKA	DOA4	7995	7995	7995	7995	7995	7995
CLKA	DOA5	7995	7995	7995	7995	7995	7995
CLKA	DOA6	7995	7995	7995	7995	7995	7995
CLKA	DOA7	7995	7995	7995	7995	7995	7995
CLKA	DOA8	7995	7995	7995	7995	7995	7995
CLKB	DOB0	8512	8512	8512	8512	8512	8512
CLKB	DOB1	8512	8512	8512	8512	8512	8512
CLKB	DOB2	8512	8512	8512	8512	8512	8512
CLKB	DOB3	8512	8512	8512	8512	8512	8512
CLKB	DOB4	8512	8512	8512	8512	8512	8512
CLKB	DOB5	8512	8512	8512	8512	8512	8512
CLKB	DOB6	8512	8512	8512	8512	8512	8512
CLKB	DOB7	8512	8512	8512	8512	8512	8512
CLKB	DOB8	8512	8512	8512	8512	8512	8512

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	207	207	207
ADA1	posedge CLKA	0	0	0	207	207	207
ADA10	posedge CLKA	0	0	0	207	207	207
ADA11	posedge CLKA	0	0	0	207	207	207
ADA12	posedge CLKA	0	0	0	207	207	207
ADA2	posedge CLKA	0	0	0	207	207	207
ADA3	posedge CLKA	0	0	0	207	207	207
ADA4	posedge CLKA	0	0	0	207	207	207
ADA5	posedge CLKA	0	0	0	207	207	207
ADA6	posedge CLKA	0	0	0	207	207	207
ADA7	posedge CLKA	0	0	0	207	207	207
ADA8	posedge CLKA	0	0	0	207	207	207
ADA9	posedge CLKA	0	0	0	207	207	207
ADB0	posedge CLKB	0	0	0	411	411	411
ADB1	posedge CLKB	0	0	0	411	411	411
ADB10	posedge CLKB	0	0	0	411	411	411
ADB11	posedge CLKB	0	0	0	411	411	411
ADB12	posedge CLKB	0	0	0	411	411	411
ADB2	posedge CLKB	0	0	0	411	411	411
ADB3	posedge CLKB	0	0	0	411	411	411
ADB4	posedge CLKB	0	0	0	411	411	411
ADB5	posedge CLKB	0	0	0	411	411	411
ADB6	posedge CLKB	0	0	0	411	411	411
ADB7	posedge CLKB	0	0	0	411	411	411
ADB8	posedge CLKB	0	0	0	411	411	411
ADB9	posedge CLKB	0	0	0	411	411	411
CEA	posedge CLKA	133	133	133	0	0	0
CEB	posedge CLKB	100	100	100	0	0	0
CSA0	posedge CLKA	297	297	297	0	0	0
CSA1	posedge CLKA	297	297	297	0	0	0
CSA2	posedge CLKA	297	297	297	0	0	0
CSB0	posedge CLKB	0	0	0	32	32	32
CSB1	posedge CLKB	0	0	0	32	32	32
CSB2	posedge CLKB	0	0	0	32	32	32
DIA0	posedge CLKA	0	0	0	245	245	245
DIA1	posedge CLKA	0	0	0	245	245	245
DIA2	posedge CLKA	0	0	0	245	245	245
DIA3	posedge CLKA	0	0	0	245	245	245
DIA4	posedge CLKA	0	0	0	245	245	245
DIA5	posedge CLKA	0	0	0	245	245	245
DIA6	posedge CLKA	0	0	0	245	245	245
DIA7	posedge CLKA	0	0	0	245	245	245
DIA8	posedge CLKA	0	0	0	245	245	245
DIB0	posedge CLKB	0	0	0	422	422	422
DIB1	posedge CLKB	0	0	0	422	422	422
DIB2	posedge CLKB	0	0	0	422	422	422
DIB3	posedge CLKB	0	0	0	422	422	422
DIB4	posedge CLKB	0	0	0	422	422	422
DIB5	posedge CLKB	0	0	0	422	422	422
DIB6	posedge CLKB	0	0	0	422	422	422
DIB7	posedge CLKB	0	0	0	422	422	422
DIB8	posedge CLKB	0	0	0	422	422	422
OCEA	posedge CLKA	133	133	133	0	0	0
OCEB	posedge CLKB	100	100	100	0	0	0
RSTA	posedge CLKA	684	684	684	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	266	266	266	0	0	0
WEB	posedge CLKB	0	0	0	129	129	129

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	5555	5555	5555	90	90	90
negedge CLKB	8334	8334	8334	60	60	60
posedge CLKA	5555	5555	5555	90	90	90
posedge CLKB	8334	8334	8334	60	60	60

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	7995	7995	7995	7995	7995	7995
CLKA	DOA1	7995	7995	7995	7995	7995	7995
CLKA	DOA2	7995	7995	7995	7995	7995	7995
CLKA	DOA3	7995	7995	7995	7995	7995	7995
CLKA	DOA4	7995	7995	7995	7995	7995	7995
CLKA	DOA5	7995	7995	7995	7995	7995	7995
CLKA	DOA6	7995	7995	7995	7995	7995	7995
CLKA	DOA7	7995	7995	7995	7995	7995	7995
CLKA	DOA8	7995	7995	7995	7995	7995	7995
CLKB	DOB0	8513	8513	8513	8513	8513	8513
CLKB	DOB1	8513	8513	8513	8513	8513	8513
CLKB	DOB2	8513	8513	8513	8513	8513	8513
CLKB	DOB3	8513	8513	8513	8513	8513	8513
CLKB	DOB4	8513	8513	8513	8513	8513	8513
CLKB	DOB5	8513	8513	8513	8513	8513	8513
CLKB	DOB6	8513	8513	8513	8513	8513	8513
CLKB	DOB7	8513	8513	8513	8513	8513	8513
CLKB	DOB8	8513	8513	8513	8513	8513	8513

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	207	207	207
ADA1	posedge CLKA	0	0	0	207	207	207
ADA10	posedge CLKA	0	0	0	207	207	207
ADA11	posedge CLKA	0	0	0	207	207	207
ADA12	posedge CLKA	0	0	0	207	207	207
ADA2	posedge CLKA	0	0	0	207	207	207
ADA3	posedge CLKA	0	0	0	207	207	207
ADA4	posedge CLKA	0	0	0	207	207	207
ADA5	posedge CLKA	0	0	0	207	207	207
ADA6	posedge CLKA	0	0	0	207	207	207
ADA7	posedge CLKA	0	0	0	207	207	207
ADA8	posedge CLKA	0	0	0	207	207	207
ADA9	posedge CLKA	0	0	0	207	207	207
ADB0	posedge CLKB	0	0	0	411	411	411
ADB1	posedge CLKB	0	0	0	411	411	411
ADB10	posedge CLKB	0	0	0	411	411	411
ADB11	posedge CLKB	0	0	0	411	411	411
ADB12	posedge CLKB	0	0	0	411	411	411
ADB2	posedge CLKB	0	0	0	411	411	411
ADB3	posedge CLKB	0	0	0	411	411	411
ADB4	posedge CLKB	0	0	0	411	411	411
ADB5	posedge CLKB	0	0	0	411	411	411
ADB6	posedge CLKB	0	0	0	411	411	411
ADB7	posedge CLKB	0	0	0	411	411	411
ADB8	posedge CLKB	0	0	0	411	411	411
ADB9	posedge CLKB	0	0	0	411	411	411
CEA	posedge CLKA	133	133	133	0	0	0
CEB	posedge CLKB	100	100	100	0	0	0
CSA0	posedge CLKA	297	297	297	0	0	0
CSA1	posedge CLKA	297	297	297	0	0	0
CSA2	posedge CLKA	297	297	297	0	0	0
CSB0	posedge CLKB	0	0	0	32	32	32
CSB1	posedge CLKB	0	0	0	32	32	32
CSB2	posedge CLKB	0	0	0	32	32	32
DIA0	posedge CLKA	0	0	0	245	245	245
DIA1	posedge CLKA	0	0	0	245	245	245
DIA2	posedge CLKA	0	0	0	245	245	245
DIA3	posedge CLKA	0	0	0	245	245	245
DIA4	posedge CLKA	0	0	0	245	245	245
DIA5	posedge CLKA	0	0	0	245	245	245
DIA6	posedge CLKA	0	0	0	245	245	245
DIA7	posedge CLKA	0	0	0	245	245	245
DIA8	posedge CLKA	0	0	0	245	245	245
DIB0	posedge CLKB	0	0	0	422	422	422
DIB1	posedge CLKB	0	0	0	422	422	422
DIB2	posedge CLKB	0	0	0	422	422	422
DIB3	posedge CLKB	0	0	0	422	422	422
DIB4	posedge CLKB	0	0	0	422	422	422
DIB5	posedge CLKB	0	0	0	422	422	422
DIB6	posedge CLKB	0	0	0	422	422	422
DIB7	posedge CLKB	0	0	0	422	422	422
DIB8	posedge CLKB	0	0	0	422	422	422
OCEA	posedge CLKA	133	133	133	0	0	0
OCEB	posedge CLKB	100	100	100	0	0	0
RSTA	posedge CLKA	684	684	684	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	266	266	266	0	0	0
WEB	posedge CLKB	0	0	0	129	129	129

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	5555	5555	5555	90	90	90
negedge CLKB	5555	5555	5555	90	90	90
posedge CLKA	5555	5555	5555	90	90	90
posedge CLKB	5555	5555	5555	90	90	90

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1498	1674	1850	1498	1674	1850
PADDO	PAD	7648	7785	7922	7648	7785	7922
PADDT	PAD	5248	9069	12890	5248	9069	12890

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	5500	5500	5500	91	91	91
posedge PAD	5500	5500	5500	91	91	91

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2585	2620	2655	2585	2620	2655
PADDO	PAD	4871	5024	5177	4871	5024	5177
PADDT	PAD	3573	5725	7877	3573	5725	7877

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2038	2063	2088	2038	2063	2088
PADDO	PAD	3741	3910	4079	3741	3910	4079
PADDT	PAD	3102	4443	5784	3102	4443	5784

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1504	1560	1616	1504	1560	1616
PADDO	PAD	3222	3335	3448	3222	3335	3448
PADDT	PAD	2578	3708	4839	2578	3708	4839

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1247	1316	1385	1247	1316	1385
PADDO	PAD	2601	2704	2807	2601	2704	2807
PADDT	PAD	2638	3513	4388	2638	3513	4388

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1604	1649	1694	1604	1649	1694
PADDO	PAD	3096	3293	3491	3096	3293	3491
PADDT	PAD	3754	4790	5827	3754	4790	5827

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

SLICE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	620	697	774	620	697	774
A0	F1	1187	1329	1471	1187	1329	1471
A0	FCO	1367	1529	1692	1367	1529	1692
A0	OFX0	924	1037	1151	924	1037	1151
A1	F1	620	697	774	620	697	774
A1	FCO	1187	1329	1471	1187	1329	1471
A1	OFX0	924	1037	1151	924	1037	1151
B0	F0	620	697	774	620	697	774
B0	F1	1187	1329	1471	1187	1329	1471
B0	FCO	1367	1529	1692	1367	1529	1692
B0	OFX0	924	1037	1151	924	1037	1151
B1	F1	620	697	774	620	697	774
B1	FCO	1187	1329	1471	1187	1329	1471
B1	OFX0	924	1037	1151	924	1037	1151
C0	F0	620	697	774	620	697	774
C0	F1	1187	1329	1471	1187	1329	1471
C0	FCO	1367	1529	1692	1367	1529	1692
C0	OFX0	924	1037	1151	924	1037	1151
C1	F1	620	697	774	620	697	774
C1	FCO	1187	1329	1471	1187	1329	1471
C1	OFX0	924	1037	1151	924	1037	1151
CLK	Q0	703	752	801	703	752	801
CLK	Q1	703	752	801	703	752	801
D0	F0	620	697	774	620	697	774
D0	F1	1187	1329	1471	1187	1329	1471
D0	FCO	1367	1529	1692	1367	1529	1692
D0	OFX0	924	1037	1151	924	1037	1151
D1	F1	620	697	774	620	697	774
D1	FCO	1187	1329	1471	1187	1329	1471
D1	OFX0	924	1037	1151	924	1037	1151
FCI	F0	783	875	968	783	875	968
FCI	F1	858	961	1064	858	961	1064
FCI	FCO	218	239	260	218	239	260
FXA	OFX1	316	363	410	316	363	410
FXB	OFX1	316	363	410	316	363	410
LSR	Q0	1405	1569	1734	1405	1569	1734
M0	OFX0	531	563	595	531	563	595
M1	OFX1	531	563	595	531	563	595
WCK	F0	1866	2059	2252	1866	2059	2252
WCK	F1	1866	2059	2252	1866	2059	2252

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	negedge CLK	408	457	507	0	0	0
CE	posedge CLK	378	422	467	0	0	0
DI0	negedge CLK	309	333	358	0	0	0
DI0	posedge CLK	309	333	358	0	0	0
DI1	posedge CLK	309	333	358	0	0	0
LSR	negedge CLK	987	1105	1223	0	0	0
LSR	posedge CLK	970	1086	1202	0	0	0
LSR	posedge CLK	1213	1213	1213	0	0	0
M0	posedge CLK	473	558	644	0	0	0
M1	negedge CLK	473	558	644	0	0	0
M1	posedge CLK	473	558	644	0	0	0
WAD0	posedge WCK	0	0	0	787	862	937
WAD1	posedge WCK	0	0	0	787	862	937
WAD2	posedge WCK	0	0	0	787	862	937
WAD3	posedge WCK	0	0	0	787	862	937
WD0	posedge WCK	0	0	0	837	904	972
WD1	posedge WCK	0	0	0	837	904	972
WRE	posedge WCK	46	64	82	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1250	1250	1250	400	400	400
negedge LSR	4000	4000	4000	125	125	125
negedge WCK	1250	1250	1250	400	400	400
posedge CLK	1250	1250	1250	400	400	400
posedge LSR	4000	4000	4000	125	125	125
posedge WCK	1250	1250	1250	400	400	400

MachXO2 Speed Grade -3 Cell Timings

Contents

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS25

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS33

Propagation Delays

Width Checks

PIO:IOTYPE=LVDS

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_II

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_II

Propagation Delays

Width Checks

SLICE

Propagation Delays

Setup/Hold Checks

Width Checks