MachXO2 Speed Grade -2 Cell Timings

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SLICE

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	8820	8820	8820	8820	8820	8820
CLKA	DOA1	8820	8820	8820	8820	8820	8820
CLKA	DOA2	8820	8820	8820	8820	8820	8820
CLKA	DOA3	8820	8820	8820	8820	8820	8820
CLKA	DOA4	8820	8820	8820	8820	8820	8820
CLKA	DOA5	8820	8820	8820	8820	8820	8820
CLKA	DOA6	8820	8820	8820	8820	8820	8820
CLKA	DOA7	8820	8820	8820	8820	8820	8820
CLKA	DOA8	8820	8820	8820	8820	8820	8820
CLKB	DOB0	9392	9392	9392	9392	9392	9392
CLKB	DOB1	9392	9392	9392	9392	9392	9392
CLKB	DOB2	9392	9392	9392	9392	9392	9392
CLKB	DOB3	9392	9392	9392	9392	9392	9392
CLKB	DOB4	9392	9392	9392	9392	9392	9392
CLKB	DOB5	9392	9392	9392	9392	9392	9392
CLKB	DOB6	9392	9392	9392	9392	9392	9392
CLKB	DOB7	9392	9392	9392	9392	9392	9392
CLKB	DOB8	9392	9392	9392	9392	9392	9392

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	229	229	229
ADA1	posedge CLKA	0	0	0	229	229	229
ADA10	posedge CLKA	0	0	0	229	229	229
ADA11	posedge CLKA	0	0	0	229	229	229
ADA12	posedge CLKA	0	0	0	229	229	229
ADA2	posedge CLKA	0	0	0	229	229	229
ADA3	posedge CLKA	0	0	0	229	229	229
ADA4	posedge CLKA	0	0	0	229	229	229
ADA5	posedge CLKA	0	0	0	229	229	229
ADA6	posedge CLKA	0	0	0	229	229	229
ADA7	posedge CLKA	0	0	0	229	229	229
ADA8	posedge CLKA	0	0	0	229	229	229
ADA9	posedge CLKA	0	0	0	229	229	229
ADB0	posedge CLKB	0	0	0	453	453	453
ADB1	posedge CLKB	0	0	0	453	453	453
ADB10	posedge CLKB	0	0	0	453	453	453
ADB11	posedge CLKB	0	0	0	453	453	453
ADB12	posedge CLKB	0	0	0	453	453	453
ADB2	posedge CLKB	0	0	0	453	453	453
ADB3	posedge CLKB	0	0	0	453	453	453
ADB4	posedge CLKB	0	0	0	453	453	453
ADB5	posedge CLKB	0	0	0	453	453	453
ADB6	posedge CLKB	0	0	0	453	453	453
ADB7	posedge CLKB	0	0	0	453	453	453
ADB8	posedge CLKB	0	0	0	453	453	453
ADB9	posedge CLKB	0	0	0	453	453	453
CEA	posedge CLKA	135	135	135	0	0	0
CEB	posedge CLKB	101	101	101	0	0	0
CSA0	posedge CLKA	316	316	316	0	0	0
CSA1	posedge CLKA	316	316	316	0	0	0
CSA2	posedge CLKA	316	316	316	0	0	0
CSB0	posedge CLKB	0	0	0	47	47	47
CSB1	posedge CLKB	0	0	0	47	47	47
CSB2	posedge CLKB	0	0	0	47	47	47
DIA0	posedge CLKA	0	0	0	268	268	268
DIA1	posedge CLKA	0	0	0	268	268	268
DIA2	posedge CLKA	0	0	0	268	268	268
DIA3	posedge CLKA	0	0	0	268	268	268
DIA4	posedge CLKA	0	0	0	268	268	268
DIA5	posedge CLKA	0	0	0	268	268	268
DIA6	posedge CLKA	0	0	0	268	268	268
DIA7	posedge CLKA	0	0	0	268	268	268
DIA8	posedge CLKA	0	0	0	268	268	268
DIB0	posedge CLKB	0	0	0	468	468	468
DIB1	posedge CLKB	0	0	0	468	468	468
DIB2	posedge CLKB	0	0	0	468	468	468
DIB3	posedge CLKB	0	0	0	468	468	468
DIB4	posedge CLKB	0	0	0	468	468	468
DIB5	posedge CLKB	0	0	0	468	468	468
DIB6	posedge CLKB	0	0	0	468	468	468
DIB7	posedge CLKB	0	0	0	468	468	468
DIB8	posedge CLKB	0	0	0	468	468	468
OCEA	posedge CLKA	135	135	135	0	0	0
OCEB	posedge CLKB	101	101	101	0	0	0
RSTA	posedge CLKA	754	754	754	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	296	296	296	0	0	0
WEB	posedge CLKB	0	0	0	155	155	155

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6095	6095	6095	82	82	82
negedge CLKB	6095	6095	6095	82	82	82
posedge CLKA	6095	6095	6095	82	82	82
posedge CLKB	6095	6095	6095	82	82	82

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	8820	8820	8820	8820	8820	8820
CLKA	DOA1	8820	8820	8820	8820	8820	8820
CLKA	DOA2	8820	8820	8820	8820	8820	8820
CLKA	DOA3	8820	8820	8820	8820	8820	8820
CLKA	DOA4	8820	8820	8820	8820	8820	8820
CLKA	DOA5	8820	8820	8820	8820	8820	8820
CLKA	DOA6	8820	8820	8820	8820	8820	8820
CLKA	DOA7	8820	8820	8820	8820	8820	8820
CLKA	DOA8	8820	8820	8820	8820	8820	8820
CLKB	DOB0	2152	2152	2152	2152	2152	2152
CLKB	DOB1	2152	2152	2152	2152	2152	2152
CLKB	DOB2	2152	2152	2152	2152	2152	2152
CLKB	DOB3	2152	2152	2152	2152	2152	2152
CLKB	DOB4	2152	2152	2152	2152	2152	2152
CLKB	DOB5	2152	2152	2152	2152	2152	2152
CLKB	DOB6	2152	2152	2152	2152	2152	2152
CLKB	DOB7	2152	2152	2152	2152	2152	2152
CLKB	DOB8	2152	2152	2152	2152	2152	2152

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	229	229	229
ADA1	posedge CLKA	0	0	0	229	229	229
ADA10	posedge CLKA	0	0	0	229	229	229
ADA11	posedge CLKA	0	0	0	229	229	229
ADA12	posedge CLKA	0	0	0	229	229	229
ADA2	posedge CLKA	0	0	0	229	229	229
ADA3	posedge CLKA	0	0	0	229	229	229
ADA4	posedge CLKA	0	0	0	229	229	229
ADA5	posedge CLKA	0	0	0	229	229	229
ADA6	posedge CLKA	0	0	0	229	229	229
ADA7	posedge CLKA	0	0	0	229	229	229
ADA8	posedge CLKA	0	0	0	229	229	229
ADA9	posedge CLKA	0	0	0	229	229	229
ADB0	posedge CLKB	0	0	0	453	453	453
ADB1	posedge CLKB	0	0	0	453	453	453
ADB10	posedge CLKB	0	0	0	453	453	453
ADB11	posedge CLKB	0	0	0	453	453	453
ADB12	posedge CLKB	0	0	0	453	453	453
ADB2	posedge CLKB	0	0	0	453	453	453
ADB3	posedge CLKB	0	0	0	453	453	453
ADB4	posedge CLKB	0	0	0	453	453	453
ADB5	posedge CLKB	0	0	0	453	453	453
ADB6	posedge CLKB	0	0	0	453	453	453
ADB7	posedge CLKB	0	0	0	453	453	453
ADB8	posedge CLKB	0	0	0	453	453	453
ADB9	posedge CLKB	0	0	0	453	453	453
CEA	posedge CLKA	135	135	135	0	0	0
CEB	posedge CLKB	101	101	101	0	0	0
CSA0	posedge CLKA	316	316	316	0	0	0
CSA1	posedge CLKA	316	316	316	0	0	0
CSA2	posedge CLKA	316	316	316	0	0	0
CSB0	posedge CLKB	0	0	0	47	47	47
CSB1	posedge CLKB	0	0	0	47	47	47
CSB2	posedge CLKB	0	0	0	47	47	47
DIA0	posedge CLKA	0	0	0	268	268	268
DIA1	posedge CLKA	0	0	0	268	268	268
DIA2	posedge CLKA	0	0	0	268	268	268
DIA3	posedge CLKA	0	0	0	268	268	268
DIA4	posedge CLKA	0	0	0	268	268	268
DIA5	posedge CLKA	0	0	0	268	268	268
DIA6	posedge CLKA	0	0	0	268	268	268
DIA7	posedge CLKA	0	0	0	268	268	268
DIA8	posedge CLKA	0	0	0	268	268	268
DIB0	posedge CLKB	0	0	0	468	468	468
DIB1	posedge CLKB	0	0	0	468	468	468
DIB2	posedge CLKB	0	0	0	468	468	468
DIB3	posedge CLKB	0	0	0	468	468	468
DIB4	posedge CLKB	0	0	0	468	468	468
DIB5	posedge CLKB	0	0	0	468	468	468
DIB6	posedge CLKB	0	0	0	468	468	468
DIB7	posedge CLKB	0	0	0	468	468	468
DIB8	posedge CLKB	0	0	0	468	468	468
OCEA	posedge CLKA	135	135	135	0	0	0
OCEB	posedge CLKB	101	101	101	0	0	0
RSTA	posedge CLKA	754	754	754	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	296	296	296	0	0	0
WEB	posedge CLKB	0	0	0	155	155	155

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6095	6095	6095	82	82	82
negedge CLKB	6095	6095	6095	82	82	82
posedge CLKA	6095	6095	6095	82	82	82
posedge CLKB	6095	6095	6095	82	82	82

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	2097	2097	2097	2097	2097	2097
CLKA	DOA1	2097	2097	2097	2097	2097	2097
CLKA	DOA2	2097	2097	2097	2097	2097	2097
CLKA	DOA3	2097	2097	2097	2097	2097	2097
CLKA	DOA4	2097	2097	2097	2097	2097	2097
CLKA	DOA5	2097	2097	2097	2097	2097	2097
CLKA	DOA6	2097	2097	2097	2097	2097	2097
CLKA	DOA7	2097	2097	2097	2097	2097	2097
CLKA	DOA8	2097	2097	2097	2097	2097	2097
CLKB	DOB0	9392	9392	9392	9392	9392	9392
CLKB	DOB1	9392	9392	9392	9392	9392	9392
CLKB	DOB2	9392	9392	9392	9392	9392	9392
CLKB	DOB3	9392	9392	9392	9392	9392	9392
CLKB	DOB4	9392	9392	9392	9392	9392	9392
CLKB	DOB5	9392	9392	9392	9392	9392	9392
CLKB	DOB6	9392	9392	9392	9392	9392	9392
CLKB	DOB7	9392	9392	9392	9392	9392	9392
CLKB	DOB8	9392	9392	9392	9392	9392	9392

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	229	229	229
ADA1	posedge CLKA	0	0	0	229	229	229
ADA10	posedge CLKA	0	0	0	229	229	229
ADA11	posedge CLKA	0	0	0	229	229	229
ADA12	posedge CLKA	0	0	0	229	229	229
ADA2	posedge CLKA	0	0	0	229	229	229
ADA3	posedge CLKA	0	0	0	229	229	229
ADA4	posedge CLKA	0	0	0	229	229	229
ADA5	posedge CLKA	0	0	0	229	229	229
ADA6	posedge CLKA	0	0	0	229	229	229
ADA7	posedge CLKA	0	0	0	229	229	229
ADA8	posedge CLKA	0	0	0	229	229	229
ADA9	posedge CLKA	0	0	0	229	229	229
ADB0	posedge CLKB	0	0	0	453	453	453
ADB1	posedge CLKB	0	0	0	453	453	453
ADB10	posedge CLKB	0	0	0	453	453	453
ADB11	posedge CLKB	0	0	0	453	453	453
ADB12	posedge CLKB	0	0	0	453	453	453
ADB2	posedge CLKB	0	0	0	453	453	453
ADB3	posedge CLKB	0	0	0	453	453	453
ADB4	posedge CLKB	0	0	0	453	453	453
ADB5	posedge CLKB	0	0	0	453	453	453
ADB6	posedge CLKB	0	0	0	453	453	453
ADB7	posedge CLKB	0	0	0	453	453	453
ADB8	posedge CLKB	0	0	0	453	453	453
ADB9	posedge CLKB	0	0	0	453	453	453
CEA	posedge CLKA	135	135	135	0	0	0
CEB	posedge CLKB	101	101	101	0	0	0
CSA0	posedge CLKA	316	316	316	0	0	0
CSA1	posedge CLKA	316	316	316	0	0	0
CSA2	posedge CLKA	316	316	316	0	0	0
CSB0	posedge CLKB	0	0	0	47	47	47
CSB1	posedge CLKB	0	0	0	47	47	47
CSB2	posedge CLKB	0	0	0	47	47	47
DIA0	posedge CLKA	0	0	0	268	268	268
DIA1	posedge CLKA	0	0	0	268	268	268
DIA2	posedge CLKA	0	0	0	268	268	268
DIA3	posedge CLKA	0	0	0	268	268	268
DIA4	posedge CLKA	0	0	0	268	268	268
DIA5	posedge CLKA	0	0	0	268	268	268
DIA6	posedge CLKA	0	0	0	268	268	268
DIA7	posedge CLKA	0	0	0	268	268	268
DIA8	posedge CLKA	0	0	0	268	268	268
DIB0	posedge CLKB	0	0	0	468	468	468
DIB1	posedge CLKB	0	0	0	468	468	468
DIB2	posedge CLKB	0	0	0	468	468	468
DIB3	posedge CLKB	0	0	0	468	468	468
DIB4	posedge CLKB	0	0	0	468	468	468
DIB5	posedge CLKB	0	0	0	468	468	468
DIB6	posedge CLKB	0	0	0	468	468	468
DIB7	posedge CLKB	0	0	0	468	468	468
DIB8	posedge CLKB	0	0	0	468	468	468
OCEA	posedge CLKA	135	135	135	0	0	0
OCEB	posedge CLKB	101	101	101	0	0	0
RSTA	posedge CLKA	754	754	754	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	296	296	296	0	0	0
WEB	posedge CLKB	0	0	0	155	155	155

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6095	6095	6095	82	82	82
negedge CLKB	6095	6095	6095	82	82	82
posedge CLKA	6095	6095	6095	82	82	82
posedge CLKB	6095	6095	6095	82	82	82

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	2097	2097	2097	2097	2097	2097
CLKA	DOA1	2097	2097	2097	2097	2097	2097
CLKA	DOA2	2097	2097	2097	2097	2097	2097
CLKA	DOA3	2097	2097	2097	2097	2097	2097
CLKA	DOA4	2097	2097	2097	2097	2097	2097
CLKA	DOA5	2097	2097	2097	2097	2097	2097
CLKA	DOA6	2097	2097	2097	2097	2097	2097
CLKA	DOA7	2097	2097	2097	2097	2097	2097
CLKA	DOA8	2097	2097	2097	2097	2097	2097
CLKB	DOB0	2152	2152	2152	2152	2152	2152
CLKB	DOB1	2152	2152	2152	2152	2152	2152
CLKB	DOB2	2152	2152	2152	2152	2152	2152
CLKB	DOB3	2152	2152	2152	2152	2152	2152
CLKB	DOB4	2152	2152	2152	2152	2152	2152
CLKB	DOB5	2152	2152	2152	2152	2152	2152
CLKB	DOB6	2152	2152	2152	2152	2152	2152
CLKB	DOB7	2152	2152	2152	2152	2152	2152
CLKB	DOB8	2152	2152	2152	2152	2152	2152

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	229	229	229
ADA1	posedge CLKA	0	0	0	229	229	229
ADA10	posedge CLKA	0	0	0	229	229	229
ADA11	posedge CLKA	0	0	0	229	229	229
ADA12	posedge CLKA	0	0	0	229	229	229
ADA2	posedge CLKA	0	0	0	229	229	229
ADA3	posedge CLKA	0	0	0	229	229	229
ADA4	posedge CLKA	0	0	0	229	229	229
ADA5	posedge CLKA	0	0	0	229	229	229
ADA6	posedge CLKA	0	0	0	229	229	229
ADA7	posedge CLKA	0	0	0	229	229	229
ADA8	posedge CLKA	0	0	0	229	229	229
ADA9	posedge CLKA	0	0	0	229	229	229
ADB0	posedge CLKB	0	0	0	453	453	453
ADB1	posedge CLKB	0	0	0	453	453	453
ADB10	posedge CLKB	0	0	0	453	453	453
ADB11	posedge CLKB	0	0	0	453	453	453
ADB12	posedge CLKB	0	0	0	453	453	453
ADB2	posedge CLKB	0	0	0	453	453	453
ADB3	posedge CLKB	0	0	0	453	453	453
ADB4	posedge CLKB	0	0	0	453	453	453
ADB5	posedge CLKB	0	0	0	453	453	453
ADB6	posedge CLKB	0	0	0	453	453	453
ADB7	posedge CLKB	0	0	0	453	453	453
ADB8	posedge CLKB	0	0	0	453	453	453
ADB9	posedge CLKB	0	0	0	453	453	453
CEA	posedge CLKA	135	135	135	0	0	0
CEB	posedge CLKB	101	101	101	0	0	0
CSA0	posedge CLKA	316	316	316	0	0	0
CSA1	posedge CLKA	316	316	316	0	0	0
CSA2	posedge CLKA	316	316	316	0	0	0
CSB0	posedge CLKB	0	0	0	47	47	47
CSB1	posedge CLKB	0	0	0	47	47	47
CSB2	posedge CLKB	0	0	0	47	47	47
DIA0	posedge CLKA	0	0	0	268	268	268
DIA1	posedge CLKA	0	0	0	268	268	268
DIA2	posedge CLKA	0	0	0	268	268	268
DIA3	posedge CLKA	0	0	0	268	268	268
DIA4	posedge CLKA	0	0	0	268	268	268
DIA5	posedge CLKA	0	0	0	268	268	268
DIA6	posedge CLKA	0	0	0	268	268	268
DIA7	posedge CLKA	0	0	0	268	268	268
DIA8	posedge CLKA	0	0	0	268	268	268
DIB0	posedge CLKB	0	0	0	468	468	468
DIB1	posedge CLKB	0	0	0	468	468	468
DIB2	posedge CLKB	0	0	0	468	468	468
DIB3	posedge CLKB	0	0	0	468	468	468
DIB4	posedge CLKB	0	0	0	468	468	468
DIB5	posedge CLKB	0	0	0	468	468	468
DIB6	posedge CLKB	0	0	0	468	468	468
DIB7	posedge CLKB	0	0	0	468	468	468
DIB8	posedge CLKB	0	0	0	468	468	468
OCEA	posedge CLKA	135	135	135	0	0	0
OCEB	posedge CLKB	101	101	101	0	0	0
RSTA	posedge CLKA	754	754	754	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	296	296	296	0	0	0
WEB	posedge CLKB	0	0	0	155	155	155

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6095	6095	6095	82	82	82
negedge CLKB	6095	6095	6095	82	82	82
posedge CLKA	6095	6095	6095	82	82	82
posedge CLKB	6095	6095	6095	82	82	82

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	8820	8820	8820	8820	8820	8820
CLKA	DOA1	8820	8820	8820	8820	8820	8820
CLKA	DOA2	8820	8820	8820	8820	8820	8820
CLKA	DOA3	8820	8820	8820	8820	8820	8820
CLKA	DOA4	8820	8820	8820	8820	8820	8820
CLKA	DOA5	8820	8820	8820	8820	8820	8820
CLKA	DOA6	8820	8820	8820	8820	8820	8820
CLKA	DOA7	8820	8820	8820	8820	8820	8820
CLKA	DOA8	8820	8820	8820	8820	8820	8820
CLKB	DOB0	9392	9392	9392	9392	9392	9392
CLKB	DOB1	9392	9392	9392	9392	9392	9392
CLKB	DOB2	9392	9392	9392	9392	9392	9392
CLKB	DOB3	9392	9392	9392	9392	9392	9392
CLKB	DOB4	9392	9392	9392	9392	9392	9392
CLKB	DOB5	9392	9392	9392	9392	9392	9392
CLKB	DOB6	9392	9392	9392	9392	9392	9392
CLKB	DOB7	9392	9392	9392	9392	9392	9392
CLKB	DOB8	9392	9392	9392	9392	9392	9392

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	229	229	229
ADA1	posedge CLKA	0	0	0	229	229	229
ADA10	posedge CLKA	0	0	0	229	229	229
ADA11	posedge CLKA	0	0	0	229	229	229
ADA12	posedge CLKA	0	0	0	229	229	229
ADA2	posedge CLKA	0	0	0	229	229	229
ADA3	posedge CLKA	0	0	0	229	229	229
ADA4	posedge CLKA	0	0	0	229	229	229
ADA5	posedge CLKA	0	0	0	229	229	229
ADA6	posedge CLKA	0	0	0	229	229	229
ADA7	posedge CLKA	0	0	0	229	229	229
ADA8	posedge CLKA	0	0	0	229	229	229
ADA9	posedge CLKA	0	0	0	229	229	229
ADB0	posedge CLKB	0	0	0	453	453	453
ADB1	posedge CLKB	0	0	0	453	453	453
ADB10	posedge CLKB	0	0	0	453	453	453
ADB11	posedge CLKB	0	0	0	453	453	453
ADB12	posedge CLKB	0	0	0	453	453	453
ADB2	posedge CLKB	0	0	0	453	453	453
ADB3	posedge CLKB	0	0	0	453	453	453
ADB4	posedge CLKB	0	0	0	453	453	453
ADB5	posedge CLKB	0	0	0	453	453	453
ADB6	posedge CLKB	0	0	0	453	453	453
ADB7	posedge CLKB	0	0	0	453	453	453
ADB8	posedge CLKB	0	0	0	453	453	453
ADB9	posedge CLKB	0	0	0	453	453	453
CEA	posedge CLKA	135	135	135	0	0	0
CEB	posedge CLKB	101	101	101	0	0	0
CSA0	posedge CLKA	316	316	316	0	0	0
CSA1	posedge CLKA	316	316	316	0	0	0
CSA2	posedge CLKA	316	316	316	0	0	0
CSB0	posedge CLKB	0	0	0	47	47	47
CSB1	posedge CLKB	0	0	0	47	47	47
CSB2	posedge CLKB	0	0	0	47	47	47
DIA0	posedge CLKA	0	0	0	268	268	268
DIA1	posedge CLKA	0	0	0	268	268	268
DIA2	posedge CLKA	0	0	0	268	268	268
DIA3	posedge CLKA	0	0	0	268	268	268
DIA4	posedge CLKA	0	0	0	268	268	268
DIA5	posedge CLKA	0	0	0	268	268	268
DIA6	posedge CLKA	0	0	0	268	268	268
DIA7	posedge CLKA	0	0	0	268	268	268
DIA8	posedge CLKA	0	0	0	268	268	268
DIB0	posedge CLKB	0	0	0	468	468	468
DIB1	posedge CLKB	0	0	0	468	468	468
DIB2	posedge CLKB	0	0	0	468	468	468
DIB3	posedge CLKB	0	0	0	468	468	468
DIB4	posedge CLKB	0	0	0	468	468	468
DIB5	posedge CLKB	0	0	0	468	468	468
DIB6	posedge CLKB	0	0	0	468	468	468
DIB7	posedge CLKB	0	0	0	468	468	468
DIB8	posedge CLKB	0	0	0	468	468	468
OCEA	posedge CLKA	135	135	135	0	0	0
OCEB	posedge CLKB	101	101	101	0	0	0
RSTA	posedge CLKA	754	754	754	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	296	296	296	0	0	0
WEB	posedge CLKB	0	0	0	155	155	155

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6095	6095	6095	82	82	82
negedge CLKB	6095	6095	6095	82	82	82
posedge CLKA	6095	6095	6095	82	82	82
posedge CLKB	6095	6095	6095	82	82	82

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	8820	8820	8820	8820	8820	8820
CLKA	DOA1	8820	8820	8820	8820	8820	8820
CLKA	DOA2	8820	8820	8820	8820	8820	8820
CLKA	DOA3	8820	8820	8820	8820	8820	8820
CLKA	DOA4	8820	8820	8820	8820	8820	8820
CLKA	DOA5	8820	8820	8820	8820	8820	8820
CLKA	DOA6	8820	8820	8820	8820	8820	8820
CLKA	DOA7	8820	8820	8820	8820	8820	8820
CLKA	DOA8	8820	8820	8820	8820	8820	8820
CLKB	DOB0	9398	9398	9398	9398	9398	9398
CLKB	DOB1	9398	9398	9398	9398	9398	9398
CLKB	DOB2	9398	9398	9398	9398	9398	9398
CLKB	DOB3	9398	9398	9398	9398	9398	9398
CLKB	DOB4	9398	9398	9398	9398	9398	9398
CLKB	DOB5	9398	9398	9398	9398	9398	9398
CLKB	DOB6	9398	9398	9398	9398	9398	9398
CLKB	DOB7	9398	9398	9398	9398	9398	9398
CLKB	DOB8	9398	9398	9398	9398	9398	9398

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	229	229	229
ADA1	posedge CLKA	0	0	0	229	229	229
ADA10	posedge CLKA	0	0	0	229	229	229
ADA11	posedge CLKA	0	0	0	229	229	229
ADA12	posedge CLKA	0	0	0	229	229	229
ADA2	posedge CLKA	0	0	0	229	229	229
ADA3	posedge CLKA	0	0	0	229	229	229
ADA4	posedge CLKA	0	0	0	229	229	229
ADA5	posedge CLKA	0	0	0	229	229	229
ADA6	posedge CLKA	0	0	0	229	229	229
ADA7	posedge CLKA	0	0	0	229	229	229
ADA8	posedge CLKA	0	0	0	229	229	229
ADA9	posedge CLKA	0	0	0	229	229	229
ADB0	posedge CLKB	0	0	0	453	453	453
ADB1	posedge CLKB	0	0	0	453	453	453
ADB10	posedge CLKB	0	0	0	453	453	453
ADB11	posedge CLKB	0	0	0	453	453	453
ADB12	posedge CLKB	0	0	0	453	453	453
ADB2	posedge CLKB	0	0	0	453	453	453
ADB3	posedge CLKB	0	0	0	453	453	453
ADB4	posedge CLKB	0	0	0	453	453	453
ADB5	posedge CLKB	0	0	0	453	453	453
ADB6	posedge CLKB	0	0	0	453	453	453
ADB7	posedge CLKB	0	0	0	453	453	453
ADB8	posedge CLKB	0	0	0	453	453	453
ADB9	posedge CLKB	0	0	0	453	453	453
CEA	posedge CLKA	135	135	135	0	0	0
CEB	posedge CLKB	101	101	101	0	0	0
CSA0	posedge CLKA	316	316	316	0	0	0
CSA1	posedge CLKA	316	316	316	0	0	0
CSA2	posedge CLKA	316	316	316	0	0	0
CSB0	posedge CLKB	0	0	0	47	47	47
CSB1	posedge CLKB	0	0	0	47	47	47
CSB2	posedge CLKB	0	0	0	47	47	47
DIA0	posedge CLKA	0	0	0	268	268	268
DIA1	posedge CLKA	0	0	0	268	268	268
DIA2	posedge CLKA	0	0	0	268	268	268
DIA3	posedge CLKA	0	0	0	268	268	268
DIA4	posedge CLKA	0	0	0	268	268	268
DIA5	posedge CLKA	0	0	0	268	268	268
DIA6	posedge CLKA	0	0	0	268	268	268
DIA7	posedge CLKA	0	0	0	268	268	268
DIA8	posedge CLKA	0	0	0	268	268	268
DIB0	posedge CLKB	0	0	0	468	468	468
DIB1	posedge CLKB	0	0	0	468	468	468
DIB2	posedge CLKB	0	0	0	468	468	468
DIB3	posedge CLKB	0	0	0	468	468	468
DIB4	posedge CLKB	0	0	0	468	468	468
DIB5	posedge CLKB	0	0	0	468	468	468
DIB6	posedge CLKB	0	0	0	468	468	468
DIB7	posedge CLKB	0	0	0	468	468	468
DIB8	posedge CLKB	0	0	0	468	468	468
OCEA	posedge CLKA	135	135	135	0	0	0
OCEB	posedge CLKB	101	101	101	0	0	0
RSTA	posedge CLKA	754	754	754	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	296	296	296	0	0	0
WEB	posedge CLKB	0	0	0	155	155	155

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6095	6095	6095	82	82	82
negedge CLKB	9166	9166	9166	55	55	55
posedge CLKA	6095	6095	6095	82	82	82
posedge CLKB	9166	9166	9166	55	55	55

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	8820	8820	8820	8820	8820	8820
CLKA	DOA1	8820	8820	8820	8820	8820	8820
CLKA	DOA2	8820	8820	8820	8820	8820	8820
CLKA	DOA3	8820	8820	8820	8820	8820	8820
CLKA	DOA4	8820	8820	8820	8820	8820	8820
CLKA	DOA5	8820	8820	8820	8820	8820	8820
CLKA	DOA6	8820	8820	8820	8820	8820	8820
CLKA	DOA7	8820	8820	8820	8820	8820	8820
CLKA	DOA8	8820	8820	8820	8820	8820	8820
CLKB	DOB0	9394	9394	9394	9394	9394	9394
CLKB	DOB1	9394	9394	9394	9394	9394	9394
CLKB	DOB2	9394	9394	9394	9394	9394	9394
CLKB	DOB3	9394	9394	9394	9394	9394	9394
CLKB	DOB4	9394	9394	9394	9394	9394	9394
CLKB	DOB5	9394	9394	9394	9394	9394	9394
CLKB	DOB6	9394	9394	9394	9394	9394	9394
CLKB	DOB7	9394	9394	9394	9394	9394	9394
CLKB	DOB8	9394	9394	9394	9394	9394	9394

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	229	229	229
ADA1	posedge CLKA	0	0	0	229	229	229
ADA10	posedge CLKA	0	0	0	229	229	229
ADA11	posedge CLKA	0	0	0	229	229	229
ADA12	posedge CLKA	0	0	0	229	229	229
ADA2	posedge CLKA	0	0	0	229	229	229
ADA3	posedge CLKA	0	0	0	229	229	229
ADA4	posedge CLKA	0	0	0	229	229	229
ADA5	posedge CLKA	0	0	0	229	229	229
ADA6	posedge CLKA	0	0	0	229	229	229
ADA7	posedge CLKA	0	0	0	229	229	229
ADA8	posedge CLKA	0	0	0	229	229	229
ADA9	posedge CLKA	0	0	0	229	229	229
ADB0	posedge CLKB	0	0	0	453	453	453
ADB1	posedge CLKB	0	0	0	453	453	453
ADB10	posedge CLKB	0	0	0	453	453	453
ADB11	posedge CLKB	0	0	0	453	453	453
ADB12	posedge CLKB	0	0	0	453	453	453
ADB2	posedge CLKB	0	0	0	453	453	453
ADB3	posedge CLKB	0	0	0	453	453	453
ADB4	posedge CLKB	0	0	0	453	453	453
ADB5	posedge CLKB	0	0	0	453	453	453
ADB6	posedge CLKB	0	0	0	453	453	453
ADB7	posedge CLKB	0	0	0	453	453	453
ADB8	posedge CLKB	0	0	0	453	453	453
ADB9	posedge CLKB	0	0	0	453	453	453
CEA	posedge CLKA	135	135	135	0	0	0
CEB	posedge CLKB	101	101	101	0	0	0
CSA0	posedge CLKA	316	316	316	0	0	0
CSA1	posedge CLKA	316	316	316	0	0	0
CSA2	posedge CLKA	316	316	316	0	0	0
CSB0	posedge CLKB	0	0	0	47	47	47
CSB1	posedge CLKB	0	0	0	47	47	47
CSB2	posedge CLKB	0	0	0	47	47	47
DIA0	posedge CLKA	0	0	0	268	268	268
DIA1	posedge CLKA	0	0	0	268	268	268
DIA2	posedge CLKA	0	0	0	268	268	268
DIA3	posedge CLKA	0	0	0	268	268	268
DIA4	posedge CLKA	0	0	0	268	268	268
DIA5	posedge CLKA	0	0	0	268	268	268
DIA6	posedge CLKA	0	0	0	268	268	268
DIA7	posedge CLKA	0	0	0	268	268	268
DIA8	posedge CLKA	0	0	0	268	268	268
DIB0	posedge CLKB	0	0	0	468	468	468
DIB1	posedge CLKB	0	0	0	468	468	468
DIB2	posedge CLKB	0	0	0	468	468	468
DIB3	posedge CLKB	0	0	0	468	468	468
DIB4	posedge CLKB	0	0	0	468	468	468
DIB5	posedge CLKB	0	0	0	468	468	468
DIB6	posedge CLKB	0	0	0	468	468	468
DIB7	posedge CLKB	0	0	0	468	468	468
DIB8	posedge CLKB	0	0	0	468	468	468
OCEA	posedge CLKA	135	135	135	0	0	0
OCEB	posedge CLKB	101	101	101	0	0	0
RSTA	posedge CLKA	754	754	754	0	0	0
RSTB	posedge CLKB	117	117	117	0	0	0
WEA	posedge CLKA	296	296	296	0	0	0
WEB	posedge CLKB	0	0	0	155	155	155

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6095	6095	6095	82	82	82
negedge CLKB	6095	6095	6095	82	82	82
posedge CLKA	6095	6095	6095	82	82	82
posedge CLKB	6095	6095	6095	82	82	82

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1498	1674	1850	1498	1674	1850
PADDO	PAD	7648	7785	7922	7648	7785	7922
PADDT	PAD	5248	9069	12890	5248	9069	12890

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	5500	5500	5500	91	91	91
posedge PAD	5500	5500	5500	91	91	91

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2585	2620	2655	2585	2620	2655
PADDO	PAD	4871	5024	5177	4871	5024	5177
PADDT	PAD	3573	5725	7877	3573	5725	7877

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2038	2063	2088	2038	2063	2088
PADDO	PAD	3741	3910	4079	3741	3910	4079
PADDT	PAD	3102	4443	5784	3102	4443	5784

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1504	1560	1616	1504	1560	1616
PADDO	PAD	3222	3335	3448	3222	3335	3448
PADDT	PAD	2578	3708	4839	2578	3708	4839

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1247	1316	1385	1247	1316	1385
PADDO	PAD	2601	2704	2807	2601	2704	2807
PADDT	PAD	2638	3513	4388	2638	3513	4388

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1604	1649	1694	1604	1649	1694
PADDO	PAD	3096	3293	3491	3096	3293	3491
PADDT	PAD	3754	4790	5827	3754	4790	5827

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

SLICE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	680	764	849	680	764	849
A0	F1	1317	1475	1633	1317	1475	1633
A0	FCO	1518	1698	1878	1518	1698	1878
A0	OFX0	1014	1134	1255	1014	1134	1255
A1	F1	680	764	849	680	764	849
A1	FCO	1317	1475	1633	1317	1475	1633
A1	OFX0	1014	1134	1255	1014	1134	1255
B0	F0	680	764	849	680	764	849
B0	F1	1317	1475	1633	1317	1475	1633
B0	FCO	1518	1698	1878	1518	1698	1878
B0	OFX0	1014	1134	1255	1014	1134	1255
B1	F1	680	764	849	680	764	849
B1	FCO	1317	1475	1633	1317	1475	1633
B1	OFX0	1014	1134	1255	1014	1134	1255
C0	F0	680	764	849	680	764	849
C0	F1	1317	1475	1633	1317	1475	1633
C0	FCO	1518	1698	1878	1518	1698	1878
C0	OFX0	1014	1134	1255	1014	1134	1255
C1	F1	680	764	849	680	764	849
C1	FCO	1317	1475	1633	1317	1475	1633
C1	OFX0	1014	1134	1255	1014	1134	1255
CLK	Q0	771	824	878	771	824	878
CLK	Q1	771	824	878	771	824	878
D0	F0	680	764	849	680	764	849
D0	F1	1317	1475	1633	1317	1475	1633
D0	FCO	1518	1698	1878	1518	1698	1878
D0	OFX0	1014	1134	1255	1014	1134	1255
D1	F1	680	764	849	680	764	849
D1	FCO	1317	1475	1633	1317	1475	1633
D1	OFX0	1014	1134	1255	1014	1134	1255
FCI	F0	869	972	1075	869	972	1075
FCI	F1	952	1066	1181	952	1066	1181
FCI	FCO	240	264	288	240	264	288
FXA	OFX1	349	396	444	349	396	444
FXB	OFX1	349	396	444	349	396	444
LSR	Q0	1538	1718	1899	1538	1718	1899
M0	OFX0	584	617	651	584	617	651
M1	OFX1	584	617	651	584	617	651
WCK	F0	2058	2267	2477	2058	2267	2477
WCK	F1	2058	2267	2477	2058	2267	2477

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	negedge CLK	453	508	563	0	0	0
CE	posedge CLK	419	468	518	0	0	0
DI0	negedge CLK	342	368	395	0	0	0
DI0	posedge CLK	342	368	395	0	0	0
DI1	posedge CLK	342	368	395	0	0	0
LSR	negedge CLK	748	844	940	0	0	0
LSR	posedge CLK	731	827	923	0	0	0
LSR	posedge CLK	1347	1347	1347	0	0	0
M0	posedge CLK	524	623	723	0	0	0
M1	negedge CLK	524	623	723	0	0	0
M1	posedge CLK	524	623	723	0	0	0
WAD0	posedge WCK	0	0	0	845	938	1031
WAD1	posedge WCK	0	0	0	845	938	1031
WAD2	posedge WCK	0	0	0	845	938	1031
WAD3	posedge WCK	0	0	0	845	938	1031
WD0	posedge WCK	0	0	0	918	998	1079
WD1	posedge WCK	0	0	0	918	998	1079
WRE	posedge WCK	51	59	68	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1625	1625	1625	308	308	308
negedge LSR	5000	5000	5000	100	100	100
negedge WCK	1625	1625	1625	308	308	308
posedge CLK	1625	1625	1625	308	308	308
posedge LSR	5000	5000	5000	100	100	100
posedge WCK	1625	1625	1625	308	308	308

MachXO2 Speed Grade -2 Cell Timings

Contents

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS25

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS33

Propagation Delays

Width Checks

PIO:IOTYPE=LVDS

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_II

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_II

Propagation Delays

Width Checks

SLICE

Propagation Delays

Setup/Hold Checks

Width Checks