MachXO2 Speed Grade -1 Cell Timings

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SLICE

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	9644	9644	9644	9644	9644	9644
CLKA	DOA1	9644	9644	9644	9644	9644	9644
CLKA	DOA2	9644	9644	9644	9644	9644	9644
CLKA	DOA3	9644	9644	9644	9644	9644	9644
CLKA	DOA4	9644	9644	9644	9644	9644	9644
CLKA	DOA5	9644	9644	9644	9644	9644	9644
CLKA	DOA6	9644	9644	9644	9644	9644	9644
CLKA	DOA7	9644	9644	9644	9644	9644	9644
CLKA	DOA8	9644	9644	9644	9644	9644	9644
CLKB	DOB0	10280	10280	10280	10280	10280	10280
CLKB	DOB1	10280	10280	10280	10280	10280	10280
CLKB	DOB2	10280	10280	10280	10280	10280	10280
CLKB	DOB3	10280	10280	10280	10280	10280	10280
CLKB	DOB4	10280	10280	10280	10280	10280	10280
CLKB	DOB5	10280	10280	10280	10280	10280	10280
CLKB	DOB6	10280	10280	10280	10280	10280	10280
CLKB	DOB7	10280	10280	10280	10280	10280	10280
CLKB	DOB8	10280	10280	10280	10280	10280	10280

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	251	251	251
ADA1	posedge CLKA	0	0	0	251	251	251
ADA10	posedge CLKA	0	0	0	251	251	251
ADA11	posedge CLKA	0	0	0	251	251	251
ADA12	posedge CLKA	0	0	0	251	251	251
ADA2	posedge CLKA	0	0	0	251	251	251
ADA3	posedge CLKA	0	0	0	251	251	251
ADA4	posedge CLKA	0	0	0	251	251	251
ADA5	posedge CLKA	0	0	0	251	251	251
ADA6	posedge CLKA	0	0	0	251	251	251
ADA7	posedge CLKA	0	0	0	251	251	251
ADA8	posedge CLKA	0	0	0	251	251	251
ADA9	posedge CLKA	0	0	0	251	251	251
ADB0	posedge CLKB	0	0	0	496	496	496
ADB1	posedge CLKB	0	0	0	496	496	496
ADB10	posedge CLKB	0	0	0	496	496	496
ADB11	posedge CLKB	0	0	0	496	496	496
ADB12	posedge CLKB	0	0	0	496	496	496
ADB2	posedge CLKB	0	0	0	496	496	496
ADB3	posedge CLKB	0	0	0	496	496	496
ADB4	posedge CLKB	0	0	0	496	496	496
ADB5	posedge CLKB	0	0	0	496	496	496
ADB6	posedge CLKB	0	0	0	496	496	496
ADB7	posedge CLKB	0	0	0	496	496	496
ADB8	posedge CLKB	0	0	0	496	496	496
ADB9	posedge CLKB	0	0	0	496	496	496
CEA	posedge CLKA	139	139	139	0	0	0
CEB	posedge CLKB	102	102	102	0	0	0
CSA0	posedge CLKA	334	334	334	0	0	0
CSA1	posedge CLKA	334	334	334	0	0	0
CSA2	posedge CLKA	334	334	334	0	0	0
CSB0	posedge CLKB	0	0	0	63	63	63
CSB1	posedge CLKB	0	0	0	63	63	63
CSB2	posedge CLKB	0	0	0	63	63	63
DIA0	posedge CLKA	0	0	0	293	293	293
DIA1	posedge CLKA	0	0	0	293	293	293
DIA2	posedge CLKA	0	0	0	293	293	293
DIA3	posedge CLKA	0	0	0	293	293	293
DIA4	posedge CLKA	0	0	0	293	293	293
DIA5	posedge CLKA	0	0	0	293	293	293
DIA6	posedge CLKA	0	0	0	293	293	293
DIA7	posedge CLKA	0	0	0	293	293	293
DIA8	posedge CLKA	0	0	0	293	293	293
DIB0	posedge CLKB	0	0	0	514	514	514
DIB1	posedge CLKB	0	0	0	514	514	514
DIB2	posedge CLKB	0	0	0	514	514	514
DIB3	posedge CLKB	0	0	0	514	514	514
DIB4	posedge CLKB	0	0	0	514	514	514
DIB5	posedge CLKB	0	0	0	514	514	514
DIB6	posedge CLKB	0	0	0	514	514	514
DIB7	posedge CLKB	0	0	0	514	514	514
DIB8	posedge CLKB	0	0	0	514	514	514
OCEA	posedge CLKA	139	139	139	0	0	0
OCEB	posedge CLKB	102	102	102	0	0	0
RSTA	posedge CLKA	823	823	823	0	0	0
RSTB	posedge CLKB	118	118	118	0	0	0
WEA	posedge CLKA	326	326	326	0	0	0
WEB	posedge CLKB	0	0	0	182	182	182

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6638	6638	6638	75	75	75
negedge CLKB	6638	6638	6638	75	75	75
posedge CLKA	6638	6638	6638	75	75	75
posedge CLKB	6638	6638	6638	75	75	75

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	9644	9644	9644	9644	9644	9644
CLKA	DOA1	9644	9644	9644	9644	9644	9644
CLKA	DOA2	9644	9644	9644	9644	9644	9644
CLKA	DOA3	9644	9644	9644	9644	9644	9644
CLKA	DOA4	9644	9644	9644	9644	9644	9644
CLKA	DOA5	9644	9644	9644	9644	9644	9644
CLKA	DOA6	9644	9644	9644	9644	9644	9644
CLKA	DOA7	9644	9644	9644	9644	9644	9644
CLKA	DOA8	9644	9644	9644	9644	9644	9644
CLKB	DOB0	2352	2352	2352	2352	2352	2352
CLKB	DOB1	2352	2352	2352	2352	2352	2352
CLKB	DOB2	2352	2352	2352	2352	2352	2352
CLKB	DOB3	2352	2352	2352	2352	2352	2352
CLKB	DOB4	2352	2352	2352	2352	2352	2352
CLKB	DOB5	2352	2352	2352	2352	2352	2352
CLKB	DOB6	2352	2352	2352	2352	2352	2352
CLKB	DOB7	2352	2352	2352	2352	2352	2352
CLKB	DOB8	2352	2352	2352	2352	2352	2352

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	251	251	251
ADA1	posedge CLKA	0	0	0	251	251	251
ADA10	posedge CLKA	0	0	0	251	251	251
ADA11	posedge CLKA	0	0	0	251	251	251
ADA12	posedge CLKA	0	0	0	251	251	251
ADA2	posedge CLKA	0	0	0	251	251	251
ADA3	posedge CLKA	0	0	0	251	251	251
ADA4	posedge CLKA	0	0	0	251	251	251
ADA5	posedge CLKA	0	0	0	251	251	251
ADA6	posedge CLKA	0	0	0	251	251	251
ADA7	posedge CLKA	0	0	0	251	251	251
ADA8	posedge CLKA	0	0	0	251	251	251
ADA9	posedge CLKA	0	0	0	251	251	251
ADB0	posedge CLKB	0	0	0	496	496	496
ADB1	posedge CLKB	0	0	0	496	496	496
ADB10	posedge CLKB	0	0	0	496	496	496
ADB11	posedge CLKB	0	0	0	496	496	496
ADB12	posedge CLKB	0	0	0	496	496	496
ADB2	posedge CLKB	0	0	0	496	496	496
ADB3	posedge CLKB	0	0	0	496	496	496
ADB4	posedge CLKB	0	0	0	496	496	496
ADB5	posedge CLKB	0	0	0	496	496	496
ADB6	posedge CLKB	0	0	0	496	496	496
ADB7	posedge CLKB	0	0	0	496	496	496
ADB8	posedge CLKB	0	0	0	496	496	496
ADB9	posedge CLKB	0	0	0	496	496	496
CEA	posedge CLKA	139	139	139	0	0	0
CEB	posedge CLKB	102	102	102	0	0	0
CSA0	posedge CLKA	334	334	334	0	0	0
CSA1	posedge CLKA	334	334	334	0	0	0
CSA2	posedge CLKA	334	334	334	0	0	0
CSB0	posedge CLKB	0	0	0	63	63	63
CSB1	posedge CLKB	0	0	0	63	63	63
CSB2	posedge CLKB	0	0	0	63	63	63
DIA0	posedge CLKA	0	0	0	293	293	293
DIA1	posedge CLKA	0	0	0	293	293	293
DIA2	posedge CLKA	0	0	0	293	293	293
DIA3	posedge CLKA	0	0	0	293	293	293
DIA4	posedge CLKA	0	0	0	293	293	293
DIA5	posedge CLKA	0	0	0	293	293	293
DIA6	posedge CLKA	0	0	0	293	293	293
DIA7	posedge CLKA	0	0	0	293	293	293
DIA8	posedge CLKA	0	0	0	293	293	293
DIB0	posedge CLKB	0	0	0	514	514	514
DIB1	posedge CLKB	0	0	0	514	514	514
DIB2	posedge CLKB	0	0	0	514	514	514
DIB3	posedge CLKB	0	0	0	514	514	514
DIB4	posedge CLKB	0	0	0	514	514	514
DIB5	posedge CLKB	0	0	0	514	514	514
DIB6	posedge CLKB	0	0	0	514	514	514
DIB7	posedge CLKB	0	0	0	514	514	514
DIB8	posedge CLKB	0	0	0	514	514	514
OCEA	posedge CLKA	139	139	139	0	0	0
OCEB	posedge CLKB	102	102	102	0	0	0
RSTA	posedge CLKA	823	823	823	0	0	0
RSTB	posedge CLKB	118	118	118	0	0	0
WEA	posedge CLKA	326	326	326	0	0	0
WEB	posedge CLKB	0	0	0	182	182	182

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6638	6638	6638	75	75	75
negedge CLKB	6638	6638	6638	75	75	75
posedge CLKA	6638	6638	6638	75	75	75
posedge CLKB	6638	6638	6638	75	75	75

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	2295	2295	2295	2295	2295	2295
CLKA	DOA1	2295	2295	2295	2295	2295	2295
CLKA	DOA2	2295	2295	2295	2295	2295	2295
CLKA	DOA3	2295	2295	2295	2295	2295	2295
CLKA	DOA4	2295	2295	2295	2295	2295	2295
CLKA	DOA5	2295	2295	2295	2295	2295	2295
CLKA	DOA6	2295	2295	2295	2295	2295	2295
CLKA	DOA7	2295	2295	2295	2295	2295	2295
CLKA	DOA8	2295	2295	2295	2295	2295	2295
CLKB	DOB0	10280	10280	10280	10280	10280	10280
CLKB	DOB1	10280	10280	10280	10280	10280	10280
CLKB	DOB2	10280	10280	10280	10280	10280	10280
CLKB	DOB3	10280	10280	10280	10280	10280	10280
CLKB	DOB4	10280	10280	10280	10280	10280	10280
CLKB	DOB5	10280	10280	10280	10280	10280	10280
CLKB	DOB6	10280	10280	10280	10280	10280	10280
CLKB	DOB7	10280	10280	10280	10280	10280	10280
CLKB	DOB8	10280	10280	10280	10280	10280	10280

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	251	251	251
ADA1	posedge CLKA	0	0	0	251	251	251
ADA10	posedge CLKA	0	0	0	251	251	251
ADA11	posedge CLKA	0	0	0	251	251	251
ADA12	posedge CLKA	0	0	0	251	251	251
ADA2	posedge CLKA	0	0	0	251	251	251
ADA3	posedge CLKA	0	0	0	251	251	251
ADA4	posedge CLKA	0	0	0	251	251	251
ADA5	posedge CLKA	0	0	0	251	251	251
ADA6	posedge CLKA	0	0	0	251	251	251
ADA7	posedge CLKA	0	0	0	251	251	251
ADA8	posedge CLKA	0	0	0	251	251	251
ADA9	posedge CLKA	0	0	0	251	251	251
ADB0	posedge CLKB	0	0	0	496	496	496
ADB1	posedge CLKB	0	0	0	496	496	496
ADB10	posedge CLKB	0	0	0	496	496	496
ADB11	posedge CLKB	0	0	0	496	496	496
ADB12	posedge CLKB	0	0	0	496	496	496
ADB2	posedge CLKB	0	0	0	496	496	496
ADB3	posedge CLKB	0	0	0	496	496	496
ADB4	posedge CLKB	0	0	0	496	496	496
ADB5	posedge CLKB	0	0	0	496	496	496
ADB6	posedge CLKB	0	0	0	496	496	496
ADB7	posedge CLKB	0	0	0	496	496	496
ADB8	posedge CLKB	0	0	0	496	496	496
ADB9	posedge CLKB	0	0	0	496	496	496
CEA	posedge CLKA	139	139	139	0	0	0
CEB	posedge CLKB	102	102	102	0	0	0
CSA0	posedge CLKA	334	334	334	0	0	0
CSA1	posedge CLKA	334	334	334	0	0	0
CSA2	posedge CLKA	334	334	334	0	0	0
CSB0	posedge CLKB	0	0	0	63	63	63
CSB1	posedge CLKB	0	0	0	63	63	63
CSB2	posedge CLKB	0	0	0	63	63	63
DIA0	posedge CLKA	0	0	0	293	293	293
DIA1	posedge CLKA	0	0	0	293	293	293
DIA2	posedge CLKA	0	0	0	293	293	293
DIA3	posedge CLKA	0	0	0	293	293	293
DIA4	posedge CLKA	0	0	0	293	293	293
DIA5	posedge CLKA	0	0	0	293	293	293
DIA6	posedge CLKA	0	0	0	293	293	293
DIA7	posedge CLKA	0	0	0	293	293	293
DIA8	posedge CLKA	0	0	0	293	293	293
DIB0	posedge CLKB	0	0	0	514	514	514
DIB1	posedge CLKB	0	0	0	514	514	514
DIB2	posedge CLKB	0	0	0	514	514	514
DIB3	posedge CLKB	0	0	0	514	514	514
DIB4	posedge CLKB	0	0	0	514	514	514
DIB5	posedge CLKB	0	0	0	514	514	514
DIB6	posedge CLKB	0	0	0	514	514	514
DIB7	posedge CLKB	0	0	0	514	514	514
DIB8	posedge CLKB	0	0	0	514	514	514
OCEA	posedge CLKA	139	139	139	0	0	0
OCEB	posedge CLKB	102	102	102	0	0	0
RSTA	posedge CLKA	823	823	823	0	0	0
RSTB	posedge CLKB	118	118	118	0	0	0
WEA	posedge CLKA	326	326	326	0	0	0
WEB	posedge CLKB	0	0	0	182	182	182

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6638	6638	6638	75	75	75
negedge CLKB	6638	6638	6638	75	75	75
posedge CLKA	6638	6638	6638	75	75	75
posedge CLKB	6638	6638	6638	75	75	75

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	2295	2295	2295	2295	2295	2295
CLKA	DOA1	2295	2295	2295	2295	2295	2295
CLKA	DOA2	2295	2295	2295	2295	2295	2295
CLKA	DOA3	2295	2295	2295	2295	2295	2295
CLKA	DOA4	2295	2295	2295	2295	2295	2295
CLKA	DOA5	2295	2295	2295	2295	2295	2295
CLKA	DOA6	2295	2295	2295	2295	2295	2295
CLKA	DOA7	2295	2295	2295	2295	2295	2295
CLKA	DOA8	2295	2295	2295	2295	2295	2295
CLKB	DOB0	2352	2352	2352	2352	2352	2352
CLKB	DOB1	2352	2352	2352	2352	2352	2352
CLKB	DOB2	2352	2352	2352	2352	2352	2352
CLKB	DOB3	2352	2352	2352	2352	2352	2352
CLKB	DOB4	2352	2352	2352	2352	2352	2352
CLKB	DOB5	2352	2352	2352	2352	2352	2352
CLKB	DOB6	2352	2352	2352	2352	2352	2352
CLKB	DOB7	2352	2352	2352	2352	2352	2352
CLKB	DOB8	2352	2352	2352	2352	2352	2352

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	251	251	251
ADA1	posedge CLKA	0	0	0	251	251	251
ADA10	posedge CLKA	0	0	0	251	251	251
ADA11	posedge CLKA	0	0	0	251	251	251
ADA12	posedge CLKA	0	0	0	251	251	251
ADA2	posedge CLKA	0	0	0	251	251	251
ADA3	posedge CLKA	0	0	0	251	251	251
ADA4	posedge CLKA	0	0	0	251	251	251
ADA5	posedge CLKA	0	0	0	251	251	251
ADA6	posedge CLKA	0	0	0	251	251	251
ADA7	posedge CLKA	0	0	0	251	251	251
ADA8	posedge CLKA	0	0	0	251	251	251
ADA9	posedge CLKA	0	0	0	251	251	251
ADB0	posedge CLKB	0	0	0	496	496	496
ADB1	posedge CLKB	0	0	0	496	496	496
ADB10	posedge CLKB	0	0	0	496	496	496
ADB11	posedge CLKB	0	0	0	496	496	496
ADB12	posedge CLKB	0	0	0	496	496	496
ADB2	posedge CLKB	0	0	0	496	496	496
ADB3	posedge CLKB	0	0	0	496	496	496
ADB4	posedge CLKB	0	0	0	496	496	496
ADB5	posedge CLKB	0	0	0	496	496	496
ADB6	posedge CLKB	0	0	0	496	496	496
ADB7	posedge CLKB	0	0	0	496	496	496
ADB8	posedge CLKB	0	0	0	496	496	496
ADB9	posedge CLKB	0	0	0	496	496	496
CEA	posedge CLKA	139	139	139	0	0	0
CEB	posedge CLKB	102	102	102	0	0	0
CSA0	posedge CLKA	334	334	334	0	0	0
CSA1	posedge CLKA	334	334	334	0	0	0
CSA2	posedge CLKA	334	334	334	0	0	0
CSB0	posedge CLKB	0	0	0	63	63	63
CSB1	posedge CLKB	0	0	0	63	63	63
CSB2	posedge CLKB	0	0	0	63	63	63
DIA0	posedge CLKA	0	0	0	293	293	293
DIA1	posedge CLKA	0	0	0	293	293	293
DIA2	posedge CLKA	0	0	0	293	293	293
DIA3	posedge CLKA	0	0	0	293	293	293
DIA4	posedge CLKA	0	0	0	293	293	293
DIA5	posedge CLKA	0	0	0	293	293	293
DIA6	posedge CLKA	0	0	0	293	293	293
DIA7	posedge CLKA	0	0	0	293	293	293
DIA8	posedge CLKA	0	0	0	293	293	293
DIB0	posedge CLKB	0	0	0	514	514	514
DIB1	posedge CLKB	0	0	0	514	514	514
DIB2	posedge CLKB	0	0	0	514	514	514
DIB3	posedge CLKB	0	0	0	514	514	514
DIB4	posedge CLKB	0	0	0	514	514	514
DIB5	posedge CLKB	0	0	0	514	514	514
DIB6	posedge CLKB	0	0	0	514	514	514
DIB7	posedge CLKB	0	0	0	514	514	514
DIB8	posedge CLKB	0	0	0	514	514	514
OCEA	posedge CLKA	139	139	139	0	0	0
OCEB	posedge CLKB	102	102	102	0	0	0
RSTA	posedge CLKA	823	823	823	0	0	0
RSTB	posedge CLKB	118	118	118	0	0	0
WEA	posedge CLKA	326	326	326	0	0	0
WEB	posedge CLKB	0	0	0	182	182	182

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6638	6638	6638	75	75	75
negedge CLKB	6638	6638	6638	75	75	75
posedge CLKA	6638	6638	6638	75	75	75
posedge CLKB	6638	6638	6638	75	75	75

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	9644	9644	9644	9644	9644	9644
CLKA	DOA1	9644	9644	9644	9644	9644	9644
CLKA	DOA2	9644	9644	9644	9644	9644	9644
CLKA	DOA3	9644	9644	9644	9644	9644	9644
CLKA	DOA4	9644	9644	9644	9644	9644	9644
CLKA	DOA5	9644	9644	9644	9644	9644	9644
CLKA	DOA6	9644	9644	9644	9644	9644	9644
CLKA	DOA7	9644	9644	9644	9644	9644	9644
CLKA	DOA8	9644	9644	9644	9644	9644	9644
CLKB	DOB0	10280	10280	10280	10280	10280	10280
CLKB	DOB1	10280	10280	10280	10280	10280	10280
CLKB	DOB2	10280	10280	10280	10280	10280	10280
CLKB	DOB3	10280	10280	10280	10280	10280	10280
CLKB	DOB4	10280	10280	10280	10280	10280	10280
CLKB	DOB5	10280	10280	10280	10280	10280	10280
CLKB	DOB6	10280	10280	10280	10280	10280	10280
CLKB	DOB7	10280	10280	10280	10280	10280	10280
CLKB	DOB8	10280	10280	10280	10280	10280	10280

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	251	251	251
ADA1	posedge CLKA	0	0	0	251	251	251
ADA10	posedge CLKA	0	0	0	251	251	251
ADA11	posedge CLKA	0	0	0	251	251	251
ADA12	posedge CLKA	0	0	0	251	251	251
ADA2	posedge CLKA	0	0	0	251	251	251
ADA3	posedge CLKA	0	0	0	251	251	251
ADA4	posedge CLKA	0	0	0	251	251	251
ADA5	posedge CLKA	0	0	0	251	251	251
ADA6	posedge CLKA	0	0	0	251	251	251
ADA7	posedge CLKA	0	0	0	251	251	251
ADA8	posedge CLKA	0	0	0	251	251	251
ADA9	posedge CLKA	0	0	0	251	251	251
ADB0	posedge CLKB	0	0	0	496	496	496
ADB1	posedge CLKB	0	0	0	496	496	496
ADB10	posedge CLKB	0	0	0	496	496	496
ADB11	posedge CLKB	0	0	0	496	496	496
ADB12	posedge CLKB	0	0	0	496	496	496
ADB2	posedge CLKB	0	0	0	496	496	496
ADB3	posedge CLKB	0	0	0	496	496	496
ADB4	posedge CLKB	0	0	0	496	496	496
ADB5	posedge CLKB	0	0	0	496	496	496
ADB6	posedge CLKB	0	0	0	496	496	496
ADB7	posedge CLKB	0	0	0	496	496	496
ADB8	posedge CLKB	0	0	0	496	496	496
ADB9	posedge CLKB	0	0	0	496	496	496
CEA	posedge CLKA	139	139	139	0	0	0
CEB	posedge CLKB	102	102	102	0	0	0
CSA0	posedge CLKA	334	334	334	0	0	0
CSA1	posedge CLKA	334	334	334	0	0	0
CSA2	posedge CLKA	334	334	334	0	0	0
CSB0	posedge CLKB	0	0	0	63	63	63
CSB1	posedge CLKB	0	0	0	63	63	63
CSB2	posedge CLKB	0	0	0	63	63	63
DIA0	posedge CLKA	0	0	0	293	293	293
DIA1	posedge CLKA	0	0	0	293	293	293
DIA2	posedge CLKA	0	0	0	293	293	293
DIA3	posedge CLKA	0	0	0	293	293	293
DIA4	posedge CLKA	0	0	0	293	293	293
DIA5	posedge CLKA	0	0	0	293	293	293
DIA6	posedge CLKA	0	0	0	293	293	293
DIA7	posedge CLKA	0	0	0	293	293	293
DIA8	posedge CLKA	0	0	0	293	293	293
DIB0	posedge CLKB	0	0	0	514	514	514
DIB1	posedge CLKB	0	0	0	514	514	514
DIB2	posedge CLKB	0	0	0	514	514	514
DIB3	posedge CLKB	0	0	0	514	514	514
DIB4	posedge CLKB	0	0	0	514	514	514
DIB5	posedge CLKB	0	0	0	514	514	514
DIB6	posedge CLKB	0	0	0	514	514	514
DIB7	posedge CLKB	0	0	0	514	514	514
DIB8	posedge CLKB	0	0	0	514	514	514
OCEA	posedge CLKA	139	139	139	0	0	0
OCEB	posedge CLKB	102	102	102	0	0	0
RSTA	posedge CLKA	823	823	823	0	0	0
RSTB	posedge CLKB	118	118	118	0	0	0
WEA	posedge CLKA	326	326	326	0	0	0
WEB	posedge CLKB	0	0	0	182	182	182

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6638	6638	6638	75	75	75
negedge CLKB	6638	6638	6638	75	75	75
posedge CLKA	6638	6638	6638	75	75	75
posedge CLKB	6638	6638	6638	75	75	75

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	9644	9644	9644	9644	9644	9644
CLKA	DOA1	9644	9644	9644	9644	9644	9644
CLKA	DOA2	9644	9644	9644	9644	9644	9644
CLKA	DOA3	9644	9644	9644	9644	9644	9644
CLKA	DOA4	9644	9644	9644	9644	9644	9644
CLKA	DOA5	9644	9644	9644	9644	9644	9644
CLKA	DOA6	9644	9644	9644	9644	9644	9644
CLKA	DOA7	9644	9644	9644	9644	9644	9644
CLKA	DOA8	9644	9644	9644	9644	9644	9644
CLKB	DOB0	10290	10290	10290	10290	10290	10290
CLKB	DOB1	10290	10290	10290	10290	10290	10290
CLKB	DOB2	10290	10290	10290	10290	10290	10290
CLKB	DOB3	10290	10290	10290	10290	10290	10290
CLKB	DOB4	10290	10290	10290	10290	10290	10290
CLKB	DOB5	10290	10290	10290	10290	10290	10290
CLKB	DOB6	10290	10290	10290	10290	10290	10290
CLKB	DOB7	10290	10290	10290	10290	10290	10290
CLKB	DOB8	10290	10290	10290	10290	10290	10290

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	251	251	251
ADA1	posedge CLKA	0	0	0	251	251	251
ADA10	posedge CLKA	0	0	0	251	251	251
ADA11	posedge CLKA	0	0	0	251	251	251
ADA12	posedge CLKA	0	0	0	251	251	251
ADA2	posedge CLKA	0	0	0	251	251	251
ADA3	posedge CLKA	0	0	0	251	251	251
ADA4	posedge CLKA	0	0	0	251	251	251
ADA5	posedge CLKA	0	0	0	251	251	251
ADA6	posedge CLKA	0	0	0	251	251	251
ADA7	posedge CLKA	0	0	0	251	251	251
ADA8	posedge CLKA	0	0	0	251	251	251
ADA9	posedge CLKA	0	0	0	251	251	251
ADB0	posedge CLKB	0	0	0	496	496	496
ADB1	posedge CLKB	0	0	0	496	496	496
ADB10	posedge CLKB	0	0	0	496	496	496
ADB11	posedge CLKB	0	0	0	496	496	496
ADB12	posedge CLKB	0	0	0	496	496	496
ADB2	posedge CLKB	0	0	0	496	496	496
ADB3	posedge CLKB	0	0	0	496	496	496
ADB4	posedge CLKB	0	0	0	496	496	496
ADB5	posedge CLKB	0	0	0	496	496	496
ADB6	posedge CLKB	0	0	0	496	496	496
ADB7	posedge CLKB	0	0	0	496	496	496
ADB8	posedge CLKB	0	0	0	496	496	496
ADB9	posedge CLKB	0	0	0	496	496	496
CEA	posedge CLKA	139	139	139	0	0	0
CEB	posedge CLKB	102	102	102	0	0	0
CSA0	posedge CLKA	334	334	334	0	0	0
CSA1	posedge CLKA	334	334	334	0	0	0
CSA2	posedge CLKA	334	334	334	0	0	0
CSB0	posedge CLKB	0	0	0	63	63	63
CSB1	posedge CLKB	0	0	0	63	63	63
CSB2	posedge CLKB	0	0	0	63	63	63
DIA0	posedge CLKA	0	0	0	293	293	293
DIA1	posedge CLKA	0	0	0	293	293	293
DIA2	posedge CLKA	0	0	0	293	293	293
DIA3	posedge CLKA	0	0	0	293	293	293
DIA4	posedge CLKA	0	0	0	293	293	293
DIA5	posedge CLKA	0	0	0	293	293	293
DIA6	posedge CLKA	0	0	0	293	293	293
DIA7	posedge CLKA	0	0	0	293	293	293
DIA8	posedge CLKA	0	0	0	293	293	293
DIB0	posedge CLKB	0	0	0	514	514	514
DIB1	posedge CLKB	0	0	0	514	514	514
DIB2	posedge CLKB	0	0	0	514	514	514
DIB3	posedge CLKB	0	0	0	514	514	514
DIB4	posedge CLKB	0	0	0	514	514	514
DIB5	posedge CLKB	0	0	0	514	514	514
DIB6	posedge CLKB	0	0	0	514	514	514
DIB7	posedge CLKB	0	0	0	514	514	514
DIB8	posedge CLKB	0	0	0	514	514	514
OCEA	posedge CLKA	139	139	139	0	0	0
OCEB	posedge CLKB	102	102	102	0	0	0
RSTA	posedge CLKA	823	823	823	0	0	0
RSTB	posedge CLKB	118	118	118	0	0	0
WEA	posedge CLKA	326	326	326	0	0	0
WEB	posedge CLKB	0	0	0	182	182	182

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6638	6638	6638	75	75	75
negedge CLKB	10000	10000	10000	50	50	50
posedge CLKA	6638	6638	6638	75	75	75
posedge CLKB	10000	10000	10000	50	50	50

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	9644	9644	9644	9644	9644	9644
CLKA	DOA1	9644	9644	9644	9644	9644	9644
CLKA	DOA2	9644	9644	9644	9644	9644	9644
CLKA	DOA3	9644	9644	9644	9644	9644	9644
CLKA	DOA4	9644	9644	9644	9644	9644	9644
CLKA	DOA5	9644	9644	9644	9644	9644	9644
CLKA	DOA6	9644	9644	9644	9644	9644	9644
CLKA	DOA7	9644	9644	9644	9644	9644	9644
CLKA	DOA8	9644	9644	9644	9644	9644	9644
CLKB	DOB0	10280	10280	10280	10280	10280	10280
CLKB	DOB1	10280	10280	10280	10280	10280	10280
CLKB	DOB2	10280	10280	10280	10280	10280	10280
CLKB	DOB3	10280	10280	10280	10280	10280	10280
CLKB	DOB4	10280	10280	10280	10280	10280	10280
CLKB	DOB5	10280	10280	10280	10280	10280	10280
CLKB	DOB6	10280	10280	10280	10280	10280	10280
CLKB	DOB7	10280	10280	10280	10280	10280	10280
CLKB	DOB8	10280	10280	10280	10280	10280	10280

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	0	0	0	251	251	251
ADA1	posedge CLKA	0	0	0	251	251	251
ADA10	posedge CLKA	0	0	0	251	251	251
ADA11	posedge CLKA	0	0	0	251	251	251
ADA12	posedge CLKA	0	0	0	251	251	251
ADA2	posedge CLKA	0	0	0	251	251	251
ADA3	posedge CLKA	0	0	0	251	251	251
ADA4	posedge CLKA	0	0	0	251	251	251
ADA5	posedge CLKA	0	0	0	251	251	251
ADA6	posedge CLKA	0	0	0	251	251	251
ADA7	posedge CLKA	0	0	0	251	251	251
ADA8	posedge CLKA	0	0	0	251	251	251
ADA9	posedge CLKA	0	0	0	251	251	251
ADB0	posedge CLKB	0	0	0	496	496	496
ADB1	posedge CLKB	0	0	0	496	496	496
ADB10	posedge CLKB	0	0	0	496	496	496
ADB11	posedge CLKB	0	0	0	496	496	496
ADB12	posedge CLKB	0	0	0	496	496	496
ADB2	posedge CLKB	0	0	0	496	496	496
ADB3	posedge CLKB	0	0	0	496	496	496
ADB4	posedge CLKB	0	0	0	496	496	496
ADB5	posedge CLKB	0	0	0	496	496	496
ADB6	posedge CLKB	0	0	0	496	496	496
ADB7	posedge CLKB	0	0	0	496	496	496
ADB8	posedge CLKB	0	0	0	496	496	496
ADB9	posedge CLKB	0	0	0	496	496	496
CEA	posedge CLKA	139	139	139	0	0	0
CEB	posedge CLKB	102	102	102	0	0	0
CSA0	posedge CLKA	334	334	334	0	0	0
CSA1	posedge CLKA	334	334	334	0	0	0
CSA2	posedge CLKA	334	334	334	0	0	0
CSB0	posedge CLKB	0	0	0	63	63	63
CSB1	posedge CLKB	0	0	0	63	63	63
CSB2	posedge CLKB	0	0	0	63	63	63
DIA0	posedge CLKA	0	0	0	293	293	293
DIA1	posedge CLKA	0	0	0	293	293	293
DIA2	posedge CLKA	0	0	0	293	293	293
DIA3	posedge CLKA	0	0	0	293	293	293
DIA4	posedge CLKA	0	0	0	293	293	293
DIA5	posedge CLKA	0	0	0	293	293	293
DIA6	posedge CLKA	0	0	0	293	293	293
DIA7	posedge CLKA	0	0	0	293	293	293
DIA8	posedge CLKA	0	0	0	293	293	293
DIB0	posedge CLKB	0	0	0	514	514	514
DIB1	posedge CLKB	0	0	0	514	514	514
DIB2	posedge CLKB	0	0	0	514	514	514
DIB3	posedge CLKB	0	0	0	514	514	514
DIB4	posedge CLKB	0	0	0	514	514	514
DIB5	posedge CLKB	0	0	0	514	514	514
DIB6	posedge CLKB	0	0	0	514	514	514
DIB7	posedge CLKB	0	0	0	514	514	514
DIB8	posedge CLKB	0	0	0	514	514	514
OCEA	posedge CLKA	139	139	139	0	0	0
OCEB	posedge CLKB	102	102	102	0	0	0
RSTA	posedge CLKA	823	823	823	0	0	0
RSTB	posedge CLKB	118	118	118	0	0	0
WEA	posedge CLKA	326	326	326	0	0	0
WEB	posedge CLKB	0	0	0	182	182	182

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	6638	6638	6638	75	75	75
negedge CLKB	6638	6638	6638	75	75	75
posedge CLKA	6638	6638	6638	75	75	75
posedge CLKB	6638	6638	6638	75	75	75

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1498	1674	1850	1498	1674	1850
PADDO	PAD	7648	7785	7922	7648	7785	7922
PADDT	PAD	5248	9069	12890	5248	9069	12890

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	5500	5500	5500	91	91	91
posedge PAD	5500	5500	5500	91	91	91

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2585	2620	2655	2585	2620	2655
PADDO	PAD	4871	5024	5177	4871	5024	5177
PADDT	PAD	3573	5725	7877	3573	5725	7877

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	2038	2063	2088	2038	2063	2088
PADDO	PAD	3741	3910	4079	3741	3910	4079
PADDT	PAD	3102	4443	5784	3102	4443	5784

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1504	1560	1616	1504	1560	1616
PADDO	PAD	3222	3335	3448	3222	3335	3448
PADDT	PAD	2578	3708	4839	2578	3708	4839

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1247	1316	1385	1247	1316	1385
PADDO	PAD	2601	2704	2807	2601	2704	2807
PADDT	PAD	2638	3513	4388	2638	3513	4388

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1604	1649	1694	1604	1649	1694
PADDO	PAD	3096	3293	3491	3096	3293	3491
PADDT	PAD	3754	4790	5827	3754	4790	5827

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1441	1467	1493	1441	1467	1493
PADDO	PAD	2795	2800	2806	2795	2800	2806
PADDT	PAD	3108	4252	5396	3108	4252	5396

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	3330	3330	3330	150	150	150
posedge PAD	3330	3330	3330	150	150	150

SLICE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	741	832	923	741	832	923
A0	F1	1448	1621	1795	1448	1621	1795
A0	FCO	1668	1866	2064	1668	1866	2064
A0	OFX0	1105	1232	1359	1105	1232	1359
A1	F1	741	832	923	741	832	923
A1	FCO	1448	1621	1795	1448	1621	1795
A1	OFX0	1105	1232	1359	1105	1232	1359
B0	F0	741	832	923	741	832	923
B0	F1	1448	1621	1795	1448	1621	1795
B0	FCO	1668	1866	2064	1668	1866	2064
B0	OFX0	1105	1232	1359	1105	1232	1359
B1	F1	741	832	923	741	832	923
B1	FCO	1448	1621	1795	1448	1621	1795
B1	OFX0	1105	1232	1359	1105	1232	1359
C0	F0	741	832	923	741	832	923
C0	F1	1448	1621	1795	1448	1621	1795
C0	FCO	1668	1866	2064	1668	1866	2064
C0	OFX0	1105	1232	1359	1105	1232	1359
C1	F1	741	832	923	741	832	923
C1	FCO	1448	1621	1795	1448	1621	1795
C1	OFX0	1105	1232	1359	1105	1232	1359
CLK	Q0	840	897	955	840	897	955
CLK	Q1	840	897	955	840	897	955
D0	F0	741	832	923	741	832	923
D0	F1	1448	1621	1795	1448	1621	1795
D0	FCO	1668	1866	2064	1668	1866	2064
D0	OFX0	1105	1232	1359	1105	1232	1359
D1	F1	741	832	923	741	832	923
D1	FCO	1448	1621	1795	1448	1621	1795
D1	OFX0	1105	1232	1359	1105	1232	1359
FCI	F0	955	1068	1181	955	1068	1181
FCI	F1	1047	1172	1298	1047	1172	1298
FCI	FCO	262	289	317	262	289	317
FXA	OFX1	381	429	478	381	429	478
FXB	OFX1	381	429	478	381	429	478
LSR	Q0	1672	1868	2064	1672	1868	2064
M0	OFX0	633	672	712	633	672	712
M1	OFX1	633	672	712	633	672	712
WCK	F0	2249	2475	2702	2249	2475	2702
WCK	F1	2249	2475	2702	2249	2475	2702

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	negedge CLK	498	558	619	0	0	0
CE	posedge CLK	461	515	570	0	0	0
DI0	negedge CLK	375	403	432	0	0	0
DI0	posedge CLK	375	403	432	0	0	0
DI1	posedge CLK	375	403	432	0	0	0
LSR	negedge CLK	542	631	720	0	0	0
LSR	posedge CLK	527	616	705	0	0	0
LSR	posedge CLK	1480	1480	1480	0	0	0
M0	posedge CLK	575	688	802	0	0	0
M1	negedge CLK	575	688	802	0	0	0
M1	posedge CLK	575	688	802	0	0	0
WAD0	posedge WCK	0	0	0	903	1014	1126
WAD1	posedge WCK	0	0	0	903	1014	1126
WAD2	posedge WCK	0	0	0	903	1014	1126
WAD3	posedge WCK	0	0	0	903	1014	1126
WD0	posedge WCK	0	0	0	1000	1093	1186
WD1	posedge WCK	0	0	0	1000	1093	1186
WRE	posedge WCK	48	60	72	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
negedge LSR	6000	6000	6000	83	83	83
negedge WCK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250
posedge LSR	6000	6000	6000	83	83	83
posedge WCK	2000	2000	2000	250	250	250

MachXO2 Speed Grade -1 Cell Timings

Contents

DP8KC:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP8KC:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS25

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS33

Propagation Delays

Width Checks

PIO:IOTYPE=LVDS

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL15_II

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_I

Propagation Delays

Width Checks

PIO:IOTYPE=SSTL18_II

Propagation Delays

Width Checks

SLICE

Propagation Delays

Setup/Hold Checks

Width Checks