PIC_T0 Bit Data



T	T		R	I	E
T	T	R	M	R	M
		G	O	C	C
		V	V	V	V
T	T		S	C	V
T	T
T	T		T	T	L
T	T	Q	L	C	O
D	D	T	O	O	M
D	D				L
D	D
D	D				T
O	O		R	I	R
O	O	E	M	R
P	P	G	O	C	C
P	P	V	V	V	V
D	D	L	S	C	V
D	D
O	O		T	T
O	O	Q	L	C	O
D	D	T	O	O
D	D				L
P	P
P	P
P	P		R	I
P	P	R	M	R	M
S	S	G	O	C	C
S	S	V	V	V	V
	T	L	S	C	V

T	T		T	T	O
T	T	Q	L	C	L
H	H	T	O	O	M
H	H	L	L
D	D
D	D				T
C	C		R	I
C	C	R	M	R
		G	O	C	C
		V	V	V	V
		L	S	C	V

			T	T
		Q	L	C	O
		T	O	O	L

Mux driving DIA_TIOLOGIC

Source	F2B9
JDIA	1

Mux driving DIB_IOLOGIC

Source	F2B21
JDIB	1

Mux driving DIC_TSIOLOGIC

Source	F2B33
JDIC	1

Mux driving DID_IOLOGIC

Source	F2B45
JDID	1

Mux driving ECLKA

Source	F2B15
G_TECLK0	-
G_TECLK1	1

Mux driving ECLKC

Source	F5B2
G_TECLK0	-
G_TECLK1	1

Mux driving JDIA

Source	F2B9
JPADDIA_PIO	-
INDDA_TIOLOGIC	1

Mux driving JDIB

Source	F2B21
JPADDIB_PIO	-
INDDB_IOLOGIC	1

Mux driving JDIC

Source	F2B33
JPADDIC_PIO	-
INDDC_TSIOLOGIC	1

Mux driving JDID

Source	F2B45
JPADDID_PIO	-
INDDD_IOLOGIC	1

Mux driving S1_JQ0

Source	F2B9
JDIA	1

Mux driving S1_JQ1

Source	F2B21
JDIB	1

Mux driving S1_JQ2

Source	F2B33
JDIC	1

Mux driving S1_JQ3

Source	F2B45
JDID	1

Configuration word IOLOGICA.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICA.DELAY.DEL_VALUE[0]	F2B5
IOLOGICA.DELAY.DEL_VALUE[1]	F3B5
IOLOGICA.DELAY.DEL_VALUE[2]	F4B5
IOLOGICA.DELAY.DEL_VALUE[3]	F5B6
IOLOGICA.DELAY.DEL_VALUE[4]	F5B5

Configuration word IOLOGICB.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICB.DELAY.DEL_VALUE[0]	F2B17
IOLOGICB.DELAY.DEL_VALUE[1]	F3B17
IOLOGICB.DELAY.DEL_VALUE[2]	F4B17
IOLOGICB.DELAY.DEL_VALUE[3]	F5B18
IOLOGICB.DELAY.DEL_VALUE[4]	F5B17

Configuration word IOLOGICC.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICC.DELAY.DEL_VALUE[0]	F2B29
IOLOGICC.DELAY.DEL_VALUE[1]	F3B29
IOLOGICC.DELAY.DEL_VALUE[2]	F4B29
IOLOGICC.DELAY.DEL_VALUE[3]	F5B30
IOLOGICC.DELAY.DEL_VALUE[4]	F5B29

Configuration word IOLOGICD.DELAY.DEL_VALUE

Default value: 5'b00000

IOLOGICD.DELAY.DEL_VALUE[0]	F2B41
IOLOGICD.DELAY.DEL_VALUE[1]	F3B41
IOLOGICD.DELAY.DEL_VALUE[2]	F4B41
IOLOGICD.DELAY.DEL_VALUE[3]	F5B42
IOLOGICD.DELAY.DEL_VALUE[4]	F5B41

Configuration Setting IOLOGICA.CEIMUX

Default value: CEMUX

Value	F4B4
CEMUX	-
1	1

Configuration Setting IOLOGICA.CEOMUX

Default value: CEMUX

Value	F4B6
CEMUX	-
1	1

Configuration Setting IOLOGICA.CLKIMUX

Default value: 0

Value	F4B9
0	-
CLK	1
INV	1

Configuration Setting IOLOGICA.CLKOMUX

Default value: 0

Value	F5B4
0	-
CLK	1
INV	1

Configuration Setting IOLOGICA.FF.INREGMODE

Default value: FF

Value	F4B2
FF	-
LATCH	1

Configuration Setting IOLOGICA.FF.REGSET

Default value: RESET

Value	F4B3
RESET	-
SET	1

Configuration Setting IOLOGICA.GSR

Default value: ENABLED

Value	F2B4
DISABLED	1
ENABLED	-

Configuration Setting IOLOGICA.LSRIMUX

Default value: 0

Value	F3B9
0	-
LSRMUX	1

Configuration Setting IOLOGICA.LSRMUX

Default value: LSR

Value	F5B8
INV	1
LSR	-

Configuration Setting IOLOGICA.LSROMUX

Default value: 0

Value	F5B11
0	-
LSRMUX	1

Configuration Setting IOLOGICA.MODE

Default value: IREG_OREG

Value	F3B3	F5B3	F5B34
NONE	-	-	-
IDDR_ODDR	1	-	-
IREG_OREG	-	-	-
ODDR2	-	1	1
ODDR4	-	1	-

Configuration Setting IOLOGICA.ODDR4.LVDS71

Default value: NONE

Value	F2B35	F5B33
NONE	-	-
NO	1	-
YES	-	1

Configuration Setting IOLOGICA.OUTREG.OUTREGMODE

Default value: FF

Value	F4B10
FF	-
LATCH	1

Configuration Setting IOLOGICA.OUTREG.REGSET

Default value: RESET

Value	F2B3
RESET	-
SET	1

Configuration Setting IOLOGICA.SRMODE

Default value: ASYNC

Value	F3B6
ASYNC	-
LSR_OVER_CE	1

Configuration Setting IOLOGICA.TSMUX

Default value: TS

Value	F2B10
INV	1
TS	-

Configuration Setting IOLOGICA.TSREG.OUTREGMODE

Default value: FF

Value	F3B10
FF	-
LATCH	1

Configuration Setting IOLOGICA.TSREG.REGSET

Default value: RESET

Value	F3B2
RESET	-
SET	1

Configuration Setting IOLOGICB.CEIMUX

Default value: CEMUX

Value	F4B16
CEMUX	-
1	1

Configuration Setting IOLOGICB.CEOMUX

Default value: CEMUX

Value	F4B18
CEMUX	-
1	1

Configuration Setting IOLOGICB.CLKIMUX

Default value: 0

Value	F4B21
0	-
CLK	1
INV	1

Configuration Setting IOLOGICB.CLKOMUX

Default value: 0

Value	F5B16
0	-
CLK	1
INV	1

Configuration Setting IOLOGICB.FF.INREGMODE

Default value: FF

Value	F4B14
FF	-
LATCH	1

Configuration Setting IOLOGICB.FF.REGSET

Default value: RESET

Value	F4B15
RESET	-
SET	1

Configuration Setting IOLOGICB.GSR

Default value: ENABLED

Value	F2B16
DISABLED	1
ENABLED	-

Configuration Setting IOLOGICB.LSRIMUX

Default value: 0

Value	F3B21
0	-
LSRMUX	1

Configuration Setting IOLOGICB.LSRMUX

Default value: LSR

Value	F2B18
INV	1
LSR	-

Configuration Setting IOLOGICB.LSROMUX

Default value: 0

Value	F5B23
0	-
LSRMUX	1

Configuration Setting IOLOGICB.MODE

Default value: IREG_OREG

Value	F3B15
NONE	-
IDDR_ODDR	1
IREG_OREG	-

Configuration Setting IOLOGICB.OUTREG.OUTREGMODE

Default value: FF

Value	F4B22
FF	-
LATCH	1

Configuration Setting IOLOGICB.OUTREG.REGSET

Default value: RESET

Value	F5B14
RESET	-
SET	1

Configuration Setting IOLOGICB.SRMODE

Default value: ASYNC

Value	F3B18
ASYNC	-
LSR_OVER_CE	1

Configuration Setting IOLOGICB.TSMUX

Default value: TS

Value	F2B22
INV	1
TS	-

Configuration Setting IOLOGICB.TSREG.OUTREGMODE

Default value: FF

Value	F3B22
FF	-
LATCH	1

Configuration Setting IOLOGICB.TSREG.REGSET

Default value: RESET

Value	F3B14
RESET	-
SET	1

Configuration Setting IOLOGICC.CEIMUX

Default value: CEMUX

Value	F4B28
CEMUX	-
1	1

Configuration Setting IOLOGICC.CEOMUX

Default value: CEMUX

Value	F4B30
CEMUX	-
1	1

Configuration Setting IOLOGICC.CLKIMUX

Default value: 0

Value	F4B33
0	-
CLK	1
INV	1

Configuration Setting IOLOGICC.CLKOMUX

Default value: 0

Value	F5B28
0	-
CLK	1
INV	1

Configuration Setting IOLOGICC.FF.INREGMODE

Default value: FF

Value	F4B26
FF	-
LATCH	1

Configuration Setting IOLOGICC.FF.REGSET

Default value: RESET

Value	F4B27
RESET	-
SET	1

Configuration Setting IOLOGICC.GSR

Default value: ENABLED

Value	F2B28
DISABLED	1
ENABLED	-

Configuration Setting IOLOGICC.LSRIMUX

Default value: 0

Value	F3B33
0	-
LSRMUX	1

Configuration Setting IOLOGICC.LSRMUX

Default value: LSR

Value	F2B30
INV	1
LSR	-

Configuration Setting IOLOGICC.LSROMUX

Default value: 0

Value	F3B35
0	-
LSRMUX	1

Configuration Setting IOLOGICC.MODE

Default value: IREG_OREG

Value	F3B27	F5B10	F5B27
NONE	-	-	-
IDDR_ODDR	1	-	-
IREG_OREG	-	-	-
ODDR2	-	1	1

Configuration Setting IOLOGICC.OUTREG.OUTREGMODE

Default value: FF

Value	F4B34
FF	-
LATCH	1

Configuration Setting IOLOGICC.OUTREG.REGSET

Default value: RESET

Value	F2B27
RESET	-
SET	1

Configuration Setting IOLOGICC.SRMODE

Default value: ASYNC

Value	F3B30
ASYNC	-
LSR_OVER_CE	1

Configuration Setting IOLOGICC.TSMUX

Default value: TS

Value	F2B34
INV	1
TS	-

Configuration Setting IOLOGICC.TSREG.OUTREGMODE

Default value: FF

Value	F3B34
FF	-
LATCH	1

Configuration Setting IOLOGICC.TSREG.REGSET

Default value: RESET

Value	F3B26
RESET	-
SET	1

Configuration Setting IOLOGICD.CEIMUX

Default value: CEMUX

Value	F4B40
CEMUX	-
1	1

Configuration Setting IOLOGICD.CEOMUX

Default value: CEMUX

Value	F4B42
CEMUX	-
1	1

Configuration Setting IOLOGICD.CLKIMUX

Default value: 0

Value	F4B45
0	-
CLK	1
INV	1

Configuration Setting IOLOGICD.CLKOMUX

Default value: 0

Value	F5B40
0	-
CLK	1
INV	1

Configuration Setting IOLOGICD.FF.INREGMODE

Default value: FF

Value	F4B38
FF	-
LATCH	1

Configuration Setting IOLOGICD.FF.REGSET

Default value: RESET

Value	F4B39
RESET	-
SET	1

Configuration Setting IOLOGICD.GSR

Default value: ENABLED

Value	F2B40
DISABLED	1
ENABLED	-

Configuration Setting IOLOGICD.LSRIMUX

Default value: 0

Value	F3B45
0	-
LSRMUX	1

Configuration Setting IOLOGICD.LSRMUX

Default value: LSR

Value	F2B42
INV	1
LSR	-

Configuration Setting IOLOGICD.LSROMUX

Default value: 0

Value	F5B46
0	-
LSRMUX	1

Configuration Setting IOLOGICD.MODE

Default value: IREG_OREG

Value	F3B39
NONE	-
IDDR_ODDR	1
IREG_OREG	-

Configuration Setting IOLOGICD.OUTREG.OUTREGMODE

Default value: FF

Value	F4B46
FF	-
LATCH	1

Configuration Setting IOLOGICD.OUTREG.REGSET

Default value: RESET

Value	F2B39
RESET	-
SET	1

Configuration Setting IOLOGICD.SRMODE

Default value: ASYNC

Value	F3B42
ASYNC	-
LSR_OVER_CE	1

Configuration Setting IOLOGICD.TSMUX

Default value: TS

Value	F2B46
INV	1
TS	-

Configuration Setting IOLOGICD.TSREG.OUTREGMODE

Default value: FF

Value	F3B46
FF	-
LATCH	1

Configuration Setting IOLOGICD.TSREG.REGSET

Default value: RESET

Value	F3B38
RESET	-
SET	1

Configuration Setting PIOA.BASE_TYPE

Default value: NONE

Value	F0B6	F0B10	F0B12	F0B14	F0B18	F0B20	F0B22	F0B24	F0B38	F1B2	F1B6	F1B8	F1B10	F1B12	F1B14	F1B18	F1B20	F1B22	F1B24	F1B30	F1B32	F1B36	F1B38	F4B8	F5B13
NONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
BIDIR_MIPI	1	1	1	1	1	1	1	1	-	1	-	-	1	1	1	1	1	1	1	-	-	-	1	1	1
INPUT_MIPI	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
OUTPUT_MIPI	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS12	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	1	-	1	-	-	-	1	1	1	-
BIDIR_LVCMOS12D	1	1	1	1	1	1	1	1	-	1	-	-	1	1	1	1	1	1	1	-	-	-	1	1	1
INPUT_LVCMOS12	-	-	-	-	-	-	-	-	-	-	1	1	-	1	-	-	1	-	-	-	-	1	1	-	-
INPUT_LVCMOS12D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	-	1	-	-
OUTPUT_LVCMOS12	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-	1	-	-	-	1	-	1	-
OUTPUT_LVCMOS12D	1	1	-	1	1	-	1	1	-	-	1	-	1	-	1	1	-	1	1	-	-	1	-	1	1
BIDIR_LVCMOS15	-	-	-	-	-	-	-	-	-	-	1	1	1	1	1	-	-	1	-	-	-	1	1	1	-
BIDIR_LVCMOS15D	1	1	1	1	1	1	1	1	-	1	-	-	1	1	1	1	1	1	1	-	-	-	1	1	1
INPUT_LVCMOS15	-	-	-	-	-	-	-	-	-	-	1	1	-	1	-	-	1	-	-	-	-	1	1	-	-
INPUT_LVCMOS15D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	-	1	-	-
OUTPUT_LVCMOS15	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	1	-	-	-	1	-	1	-
OUTPUT_LVCMOS15D	1	1	1	1	-	-	1	1	-	-	1	-	1	1	1	-	-	1	1	-	-	1	-	1	1
BIDIR_HSTL18D_I	1	-	-	1	1	-	1	1	-	1	-	-	-	-	1	1	-	1	1	-	-	1	-	1	1
BIDIR_HSTL18_I	-	-	-	-	-	-	-	-	-	1	1	-	-	-	1	1	-	1	1	-	-	1	-	1	-
BIDIR_LVCMOS18	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	1	1	-	-	-	1	1	1	-
BIDIR_LVCMOS18D	1	1	-	-	1	1	1	1	1	1	-	-	1	-	-	1	1	1	1	-	-	1	1	1	1
BIDIR_SSTL18D_I	1	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	1	-	-	1	-	1	1
BIDIR_SSTL18_I	-	-	-	1	1	-	1	-	-	1	1	-	-	-	1	1	-	1	1	-	-	1	-	1	-
INPUT_HSTL18D_I	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-	-
INPUT_HSTL18D_II	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-	-
INPUT_HSTL18_I	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	1	-	-	-
INPUT_HSTL18_II	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	1	-	-	-
INPUT_LVCMOS18	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	-	-	1	1	-	-
INPUT_LVCMOS18D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	1	1	-	-
INPUT_SSTL18D_I	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-	-
INPUT_SSTL18D_II	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-	-
INPUT_SSTL18_I	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	1	-	-	-
INPUT_SSTL18_II	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	1	-	-	-
OUTPUT_HSTL18D_I	1	-	-	1	1	-	1	1	-	-	1	-	-	-	1	1	-	1	1	-	-	1	-	1	1
OUTPUT_HSTL18_I	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	1	1	-	-	1	-	1	-
OUTPUT_LVCMOS18	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	1	1	-	-	-	1	-	1	-
OUTPUT_LVCMOS18D	1	1	-	-	1	1	1	1	-	-	1	-	1	-	-	1	1	1	1	-	-	1	-	1	1
OUTPUT_SSTL18D_I	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	1	-	1	1
OUTPUT_SSTL18_I	-	-	-	1	1	-	1	-	-	-	-	-	-	-	1	1	-	1	1	-	-	1	-	1	-
BIDIR_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-
BIDIR_LVCMOS25D	1	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	1	-	-	-	1	1	1
BIDIR_SSTL25D_I	1	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	1	-	-	-	-	1	1
BIDIR_SSTL25_I	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	1	-	-	-	-	1	-
INPUT_BLVDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	-	1	-	1	-	-
INPUT_LVCMOS25D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	-	1	-	-
INPUT_LVDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_MLVDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_RSDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_SSTL25D_I	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_SSTL25D_II	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_SSTL25_I	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_SSTL25_II	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	-	-	-	-
OUTPUT_BLVDS25E	1	1	1	1	1	1	1	1	-	-	1	-	1	1	1	1	1	1	1	-	-	-	-	1	1
OUTPUT_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-
OUTPUT_LVCMOS25D	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	-	1	1
OUTPUT_LVDS25	1	-	1	-	-	1	-	1	-	-	1	-	-	1	-	-	1	-	1	1	-	-	-	1	1
OUTPUT_LVDS25E	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	-	1	1
OUTPUT_MLVDS25E	1	1	1	1	1	1	1	1	-	-	1	-	1	1	1	1	1	1	1	-	-	-	-	1	1
OUTPUT_RSDS25E	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	-	1	1
OUTPUT_SSTL25D_I	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	-	1	1
OUTPUT_SSTL25_I	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-
BIDIR_LVCMOS33D	1	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	1	-	-	-	1	1	1
BIDIR_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-
BIDIR_LVTTL33D	1	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	1	-	-	-	1	1	1
INPUT_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	-	1	-	1	-	-
INPUT_LVCMOS33D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	-	1	-	-
INPUT_LVPECL33	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-	-
INPUT_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	-	1	-	1	-	-
INPUT_LVTTL33D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	-	1	-	-
OUTPUT_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-
OUTPUT_LVCMOS33D	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	-	1	1
OUTPUT_LVPECL33E	1	1	1	1	1	1	1	1	-	-	1	-	1	1	1	1	1	1	1	-	-	-	-	1	1
OUTPUT_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-
OUTPUT_LVTTL33D	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	-	1	1
BIDIR_LVCMOS10R25	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	-	1	-
INPUT_LVCMOS10R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
BIDIR_LVCMOS10R33	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	-	1	-
INPUT_LVCMOS10R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
BIDIR_LVCMOS12R25	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	-	1	-
INPUT_LVCMOS12R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
BIDIR_LVCMOS12R33	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	-	1	-
INPUT_LVCMOS12R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
INPUT_LVCMOS15R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
INPUT_LVCMOS15R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
INPUT_LVCMOS18R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
INPUT_LVCMOS18R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-
INPUT_LVCMOS25R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	-	1	-	-

Configuration Setting PIOA.CLAMP

Default value: OFF

Value	F1B38
OFF	0
ON	1

Configuration Setting PIOA.DATAMUX_ODDR

Default value: PADDO

Value	F3B4
IOLDO	1
PADDO	-

Configuration Setting PIOA.DATAMUX_OREG

Default value: PADDO

Value	F5B9
IOLDO	1
PADDO	-

Configuration Setting PIOA.DRIVE

Default value: 8

Value	F1B10	F1B12	F1B14	F1B18	F1B20	F1B22	F1B36
2	0	0	0	0	0	0	1
4	1	1	0	1	1	0	0
6	1	0	1	1	0	1	1
8	0	0	0	0	0	0	0
12	1	0	0	1	0	0	0
16	1	1	1	1	1	1	0
24	0	0	1	0	0	1	0

Configuration Setting PIOA.HYSTERESIS

Default value: SMALL

Value	F1B34
LARGE	1
SMALL	0

Configuration Setting PIOA.OPENDRAIN

Default value: OFF

Value	F1B14	F1B20	F1B24
OFF	0	0	0
ON	1	1	1

Configuration Setting PIOA.PGMUX

Default value: INBUF

Value	F1B26
INBUF	-
PGBUF	1

Configuration Setting PIOA.PULLMODE

Default value: FAILSAFE

Value	F1B16	F1B24
NONE	0	1
DOWN	0	0
FAILSAFE	0	0
KEEPER	1	0
UP	1	1

Configuration Setting PIOA.SLEWRATE

Default value: SLOW

Value	F1B28
FAST	1
SLOW	0

Configuration Setting PIOA.TRIMUX_TSREG

Default value: PADDT

Value	F3B8
IOLTO	1
PADDT	-

Configuration Setting PIOB.BASE_TYPE

Default value: NONE

Value	F0B2	F0B6	F0B8	F0B10	F0B12	F0B14	F0B18	F0B20	F0B22	F0B24	F0B32	F0B36	F0B38	F4B20
NONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-
BIDIR_LVCMOS12	-	1	1	1	-	1	1	-	1	-	-	1	1	1
INPUT_LVCMOS12	-	1	1	-	1	-	-	1	-	-	-	1	1	-
OUTPUT_LVCMOS12	-	-	-	1	-	1	1	-	1	-	-	1	-	1
BIDIR_LVCMOS15	-	1	1	1	1	1	-	-	1	-	-	1	1	1
INPUT_LVCMOS15	-	1	1	-	1	-	-	1	-	-	-	1	1	-
OUTPUT_LVCMOS15	-	-	-	1	1	1	-	-	1	-	-	1	-	1
BIDIR_HSTL18_I	1	1	-	-	-	1	1	-	1	1	-	1	-	1
BIDIR_LVCMOS18	-	-	-	1	-	-	1	1	1	-	-	1	1	1
BIDIR_SSTL18_I	1	1	-	-	-	1	1	-	1	1	-	1	-	1
INPUT_HSTL18_I	1	1	-	-	1	-	-	1	-	1	-	1	-	-
INPUT_HSTL18_II	1	1	-	-	1	-	-	1	-	1	-	1	-	-
INPUT_LVCMOS18	-	-	-	-	1	-	-	1	-	-	-	1	1	-
INPUT_SSTL18_I	1	1	-	-	1	-	-	1	-	1	-	1	-	-
INPUT_SSTL18_II	1	1	-	-	1	-	-	1	-	1	-	1	-	-
OUTPUT_HSTL18_I	-	-	-	-	-	1	1	-	1	1	-	1	-	1
OUTPUT_LVCMOS18	-	-	-	1	-	-	1	1	1	-	-	1	-	1
OUTPUT_SSTL18_I	-	-	-	-	-	1	1	-	1	1	-	1	-	1
BIDIR_LVCMOS25	-	-	-	-	-	-	-	-	-	-	1	-	1	1
BIDIR_SSTL25_I	1	1	-	-	-	-	-	-	-	1	-	-	-	1
INPUT_LVCMOS25	-	-	-	-	1	-	-	1	-	-	1	-	1	-
INPUT_SSTL25_I	1	1	-	-	1	-	-	1	-	1	-	-	-	-
INPUT_SSTL25_II	1	1	-	-	1	-	-	1	-	1	-	-	-	-
OUTPUT_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	1
OUTPUT_SSTL25_I	-	-	-	-	-	-	-	-	-	1	-	-	-	1
BIDIR_LVCMOS33	-	-	-	-	-	-	-	-	-	-	1	-	1	1
BIDIR_LVTTL33	-	-	-	-	-	-	-	-	-	-	1	-	1	1
INPUT_LVCMOS33	-	-	-	-	1	-	-	1	-	-	1	-	1	-
INPUT_LVTTL33	-	-	-	-	1	-	-	1	-	-	1	-	1	-
OUTPUT_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	1
OUTPUT_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	1
BIDIR_LVCMOS10R25	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS10R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS10R33	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS10R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS12R25	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS12R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS12R33	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS12R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS15R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS15R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS18R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS18R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS25R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-

Configuration Setting PIOB.CLAMP

Default value: OFF

Value	F0B38
OFF	0
ON	1

Configuration Setting PIOB.DATAMUX_ODDR

Default value: PADDO

Value	F3B16
IOLDO	1
PADDO	-

Configuration Setting PIOB.DATAMUX_OREG

Default value: PADDO

Value	F5B21
IOLDO	1
PADDO	-

Configuration Setting PIOB.DRIVE

Default value: 8

Value	F0B10	F0B12	F0B14	F0B18	F0B20	F0B22	F0B36
2	0	0	0	0	0	0	1
4	1	1	0	1	1	0	0
6	1	0	1	1	0	1	1
8	0	0	0	0	0	0	0
12	1	0	0	1	0	0	0
16	1	1	1	1	1	1	0
24	0	0	1	0	0	1	0

Configuration Setting PIOB.HYSTERESIS

Default value: SMALL

Value	F0B34
LARGE	1
SMALL	0

Configuration Setting PIOB.OPENDRAIN

Default value: OFF

Value	F0B14	F0B20	F0B24
OFF	0	0	0
ON	1	1	1

Configuration Setting PIOB.PGMUX

Default value: INBUF

Value	F0B26
INBUF	-
PGBUF	1

Configuration Setting PIOB.PULLMODE

Default value: FAILSAFE

Value	F0B16	F0B24
NONE	0	1
DOWN	0	0
FAILSAFE	0	0
KEEPER	1	0
UP	1	1

Configuration Setting PIOB.SLEWRATE

Default value: SLOW

Value	F0B28
FAST	1
SLOW	0

Configuration Setting PIOB.TRIMUX_TSREG

Default value: PADDT

Value	F3B20
IOLTO	1
PADDT	-

Configuration Setting PIOC.BASE_TYPE

Default value: NONE

Value	F0B7	F0B11	F0B13	F0B15	F0B19	F0B21	F0B23	F0B25	F0B39	F1B3	F1B7	F1B9	F1B11	F1B13	F1B15	F1B19	F1B21	F1B23	F1B25	F1B33	F1B37	F1B39	F4B32	F5B37
NONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-
BIDIR_MIPI	1	1	1	1	1	1	1	1	-	1	-	-	1	1	1	1	1	1	1	-	-	1	1	1
INPUT_MIPI	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
OUTPUT_MIPI	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	1	-	-	-	1	-
BIDIR_LVCMOS12	-	-	-	-	-	-	-	-	-	-	1	1	1	-	1	1	-	1	-	-	1	1	1	-
BIDIR_LVCMOS12D	1	1	1	1	1	1	1	1	-	1	-	-	1	1	1	1	1	1	1	-	-	1	1	1
INPUT_LVCMOS12	-	-	-	-	-	-	-	-	-	-	1	1	-	1	-	-	1	-	-	-	1	1	-	-
INPUT_LVCMOS12D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-
OUTPUT_LVCMOS12	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-	1	-	-	1	-	1	-
OUTPUT_LVCMOS12D	1	1	-	1	1	-	1	1	-	-	1	-	1	-	1	1	-	1	1	-	1	-	1	1
BIDIR_LVCMOS15	-	-	-	-	-	-	-	-	-	-	1	1	1	1	1	-	-	1	-	-	1	1	1	-
BIDIR_LVCMOS15D	1	1	1	1	1	1	1	1	-	1	-	-	1	1	1	1	1	1	1	-	-	1	1	1
INPUT_LVCMOS15	-	-	-	-	-	-	-	-	-	-	1	1	-	1	-	-	1	-	-	-	1	1	-	-
INPUT_LVCMOS15D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-
OUTPUT_LVCMOS15	-	-	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	1	-	-	1	-	1	-
OUTPUT_LVCMOS15D	1	1	1	1	-	-	1	1	-	-	1	-	1	1	1	-	-	1	1	-	1	-	1	1
BIDIR_HSTL18D_I	1	-	-	1	1	-	1	1	-	1	-	-	-	-	1	1	-	1	1	-	1	-	1	1
BIDIR_HSTL18_I	-	-	-	-	-	-	-	-	-	1	1	-	-	-	1	1	-	1	1	-	1	-	1	-
BIDIR_LVCMOS18	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	1	1	-	-	1	1	1	-
BIDIR_LVCMOS18D	1	1	-	-	1	1	1	1	1	1	-	-	1	-	-	1	1	1	1	-	1	1	1	1
BIDIR_SSTL18D_I	1	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	1	-	1	-	1	1
BIDIR_SSTL18_I	-	-	-	1	1	-	1	-	-	1	1	-	-	-	1	1	-	1	1	-	1	-	1	-
INPUT_HSTL18D_I	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	1	-	-	-
INPUT_HSTL18D_II	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	1	-	-	-
INPUT_HSTL18_I	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	1	-	-	-
INPUT_HSTL18_II	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	1	-	-	-
INPUT_LVCMOS18	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	-	1	1	-	-
INPUT_LVCMOS18D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	1	1	-	-
INPUT_SSTL18D_I	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	1	-	-	-
INPUT_SSTL18D_II	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	1	-	-	-
INPUT_SSTL18_I	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	1	-	-	-
INPUT_SSTL18_II	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	1	-	-	-
OUTPUT_HSTL18D_I	1	-	-	1	1	-	1	1	-	-	1	-	-	-	1	1	-	1	1	-	1	-	1	1
OUTPUT_HSTL18_I	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	1	1	-	1	-	1	-
OUTPUT_LVCMOS18	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	1	1	-	-	1	-	1	-
OUTPUT_LVCMOS18D	1	1	-	-	1	1	1	1	-	-	1	-	1	-	-	1	1	1	1	-	1	-	1	1
OUTPUT_SSTL18D_I	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	1	-	1	1
OUTPUT_SSTL18_I	-	-	-	1	1	-	1	-	-	-	-	-	-	-	1	1	-	1	1	-	1	-	1	-
BIDIR_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-
BIDIR_LVCMOS25D	1	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	1	-	-	1	1	1
BIDIR_SSTL25D_I	1	-	-	-	-	-	-	1	-	1	-	-	-	-	-	-	-	-	1	-	-	-	1	1
BIDIR_SSTL25_I	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	1	-	-	-	1	-
INPUT_BLVDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	1	-	1	-	-
INPUT_LVCMOS25D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-
INPUT_LVDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_MLVDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_RSDS25	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_SSTL25D_I	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_SSTL25D_II	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_SSTL25_I	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_SSTL25_II	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	1	-	-	-	-	-
OUTPUT_BLVDS25E	1	1	1	1	1	1	1	1	-	-	1	-	1	1	1	1	1	1	1	-	-	-	1	1
OUTPUT_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-
OUTPUT_LVCMOS25D	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	1	1
OUTPUT_LVDS25E	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	1	1
OUTPUT_MLVDS25E	1	1	1	1	1	1	1	1	-	-	1	-	1	1	1	1	1	1	1	-	-	-	1	1
OUTPUT_RSDS25E	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	1	1
OUTPUT_SSTL25D_I	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	1	1
OUTPUT_SSTL25_I	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	1	-
BIDIR_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-
BIDIR_LVCMOS33D	1	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	1	-	-	1	1	1
BIDIR_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	1	1	-
BIDIR_LVTTL33D	1	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	1	-	-	1	1	1
INPUT_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	1	-	1	-	-
INPUT_LVCMOS33D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-
INPUT_LVPECL33	1	-	1	-	-	1	-	1	-	1	-	-	-	1	-	-	1	-	1	-	-	-	-	-
INPUT_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	1	-	-	1	-	1	-	-
INPUT_LVTTL33D	1	-	1	-	-	1	-	1	1	1	-	-	-	1	-	-	1	-	1	-	-	1	-	-
OUTPUT_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-
OUTPUT_LVCMOS33D	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	1	1
OUTPUT_LVPECL33E	1	1	1	1	1	1	1	1	-	-	1	-	1	1	1	1	1	1	1	-	-	-	1	1
OUTPUT_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-
OUTPUT_LVTTL33D	1	-	-	-	-	-	-	1	-	-	1	-	-	-	-	-	-	-	1	-	-	-	1	1
BIDIR_LVCMOS10R25	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	1	-
INPUT_LVCMOS10R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
BIDIR_LVCMOS10R33	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	1	-
INPUT_LVCMOS10R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
BIDIR_LVCMOS12R25	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	1	-
INPUT_LVCMOS12R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
BIDIR_LVCMOS12R33	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	1	-	1	-	-	-	1	-
INPUT_LVCMOS12R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
INPUT_LVCMOS15R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
INPUT_LVCMOS15R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
INPUT_LVCMOS18R25	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
INPUT_LVCMOS18R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-
INPUT_LVCMOS25R33	-	-	-	-	-	-	-	-	-	1	1	-	-	1	-	-	1	-	-	-	-	1	-	-

Configuration Setting PIOC.CLAMP

Default value: OFF

Value	F1B39
OFF	0
ON	1

Configuration Setting PIOC.DATAMUX_ODDR

Default value: PADDO

Value	F3B28
IOLDO	1
PADDO	-

Configuration Setting PIOC.DATAMUX_OREG

Default value: PADDO

Value	F5B32
IOLDO	1
PADDO	-

Configuration Setting PIOC.DRIVE

Default value: 8

Value	F1B11	F1B13	F1B15	F1B19	F1B21	F1B23	F1B37
2	0	0	0	0	0	0	1
4	1	1	0	1	1	0	0
6	1	0	1	1	0	1	1
8	0	0	0	0	0	0	0
12	1	0	0	1	0	0	0
16	1	1	1	1	1	1	0
24	0	0	1	0	0	1	0

Configuration Setting PIOC.HYSTERESIS

Default value: SMALL

Value	F1B35
LARGE	1
SMALL	0

Configuration Setting PIOC.OPENDRAIN

Default value: OFF

Value	F1B15	F1B21	F1B25
OFF	0	0	0
ON	1	1	1

Configuration Setting PIOC.PGMUX

Default value: INBUF

Value	F1B27
INBUF	-
PGBUF	1

Configuration Setting PIOC.PULLMODE

Default value: FAILSAFE

Value	F1B17	F1B25
NONE	0	1
DOWN	0	0
FAILSAFE	0	0
KEEPER	1	0
UP	1	1

Configuration Setting PIOC.SLEWRATE

Default value: SLOW

Value	F1B29
FAST	1
SLOW	0

Configuration Setting PIOC.TRIMUX_TSREG

Default value: PADDT

Value	F3B32
IOLTO	1
PADDT	-

Configuration Setting PIOD.BASE_TYPE

Default value: NONE

Value	F0B3	F0B7	F0B9	F0B11	F0B13	F0B15	F0B19	F0B21	F0B23	F0B25	F0B33	F0B37	F0B39	F4B44
NONE	-	-	-	-	-	-	-	-	-	-	-	-	-	-
BIDIR_LVCMOS12	-	1	1	1	-	1	1	-	1	-	-	1	1	1
INPUT_LVCMOS12	-	1	1	-	1	-	-	1	-	-	-	1	1	-
OUTPUT_LVCMOS12	-	-	-	1	-	1	1	-	1	-	-	1	-	1
BIDIR_LVCMOS15	-	1	1	1	1	1	-	-	1	-	-	1	1	1
INPUT_LVCMOS15	-	1	1	-	1	-	-	1	-	-	-	1	1	-
OUTPUT_LVCMOS15	-	-	-	1	1	1	-	-	1	-	-	1	-	1
BIDIR_HSTL18_I	1	1	-	-	-	1	1	-	1	1	-	1	-	1
BIDIR_LVCMOS18	-	-	-	1	-	-	1	1	1	-	-	1	1	1
BIDIR_SSTL18_I	1	1	-	-	-	1	1	-	1	1	-	1	-	1
INPUT_HSTL18_I	1	1	-	-	1	-	-	1	-	1	-	1	-	-
INPUT_HSTL18_II	1	1	-	-	1	-	-	1	-	1	-	1	-	-
INPUT_LVCMOS18	-	-	-	-	1	-	-	1	-	-	-	1	1	-
INPUT_SSTL18_I	1	1	-	-	1	-	-	1	-	1	-	1	-	-
INPUT_SSTL18_II	1	1	-	-	1	-	-	1	-	1	-	1	-	-
OUTPUT_HSTL18_I	-	-	-	-	-	1	1	-	1	1	-	1	-	1
OUTPUT_LVCMOS18	-	-	-	1	-	-	1	1	1	-	-	1	-	1
OUTPUT_SSTL18_I	-	-	-	-	-	1	1	-	1	1	-	1	-	1
BIDIR_LVCMOS25	-	-	-	-	-	-	-	-	-	-	1	-	1	1
BIDIR_SSTL25_I	1	1	-	-	-	-	-	-	-	1	-	-	-	1
INPUT_LVCMOS25	-	-	-	-	1	-	-	1	-	-	1	-	1	-
INPUT_SSTL25_I	1	1	-	-	1	-	-	1	-	1	-	-	-	-
INPUT_SSTL25_II	1	1	-	-	1	-	-	1	-	1	-	-	-	-
OUTPUT_LVCMOS25	-	-	-	-	-	-	-	-	-	-	-	-	-	1
OUTPUT_SSTL25_I	-	-	-	-	-	-	-	-	-	1	-	-	-	1
BIDIR_LVCMOS33	-	-	-	-	-	-	-	-	-	-	1	-	1	1
BIDIR_LVTTL33	-	-	-	-	-	-	-	-	-	-	1	-	1	1
INPUT_LVCMOS33	-	-	-	-	1	-	-	1	-	-	1	-	1	-
INPUT_LVTTL33	-	-	-	-	1	-	-	1	-	-	1	-	1	-
OUTPUT_LVCMOS33	-	-	-	-	-	-	-	-	-	-	-	-	-	1
OUTPUT_LVTTL33	-	-	-	-	-	-	-	-	-	-	-	-	-	1
BIDIR_LVCMOS10R25	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS10R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS10R33	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS10R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS12R25	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS12R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
BIDIR_LVCMOS12R33	1	1	-	-	-	-	-	1	-	1	-	-	-	1
INPUT_LVCMOS12R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS15R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS15R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS18R25	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS18R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-
INPUT_LVCMOS25R33	1	1	-	-	1	-	-	1	-	-	-	-	1	-

Configuration Setting PIOD.CLAMP

Default value: OFF

Value	F0B39
OFF	0
ON	1

Configuration Setting PIOD.DATAMUX_ODDR

Default value: PADDO

Value	F3B40
IOLDO	1
PADDO	-

Configuration Setting PIOD.DATAMUX_OREG

Default value: PADDO

Value	F5B45
IOLDO	1
PADDO	-

Configuration Setting PIOD.DRIVE

Default value: 8

Value	F0B11	F0B13	F0B15	F0B19	F0B21	F0B23	F0B37
2	0	0	0	0	0	0	1
4	1	1	0	1	1	0	0
6	1	0	1	1	0	1	1
8	0	0	0	0	0	0	0
12	1	0	0	1	0	0	0
16	1	1	1	1	1	1	0
24	0	0	1	0	0	1	0

Configuration Setting PIOD.HYSTERESIS

Default value: SMALL

Value	F0B35
LARGE	1
SMALL	0

Configuration Setting PIOD.OPENDRAIN

Default value: OFF

Value	F0B15	F0B21	F0B25
OFF	0	0	0
ON	1	1	1

Configuration Setting PIOD.PGMUX

Default value: INBUF

Value	F0B27
INBUF	-
PGBUF	1

Configuration Setting PIOD.PULLMODE

Default value: FAILSAFE

Value	F0B17	F0B25
NONE	0	1
DOWN	0	0
FAILSAFE	0	0
KEEPER	1	0
UP	1	1

Configuration Setting PIOD.SLEWRATE

Default value: SLOW

Value	F0B29
FAST	1
SLOW	0

Configuration Setting PIOD.TRIMUX_TSREG

Default value: PADDT

Value	F3B44
IOLTO	1
PADDT	-

Fixed Connections

Source		Sink
ECLKA	→	ECLKA_TIOLOGIC
ECLKC	→	ECLKC_TSIOLOGIC
G_INRD	→	G_INRDA_PIO
G_INRD	→	G_INRDB_PIO
G_INRD	→	G_INRDC_PIO
G_INRD	→	G_INRDD_PIO
G_LVDS	→	G_LVDSA_PIO
G_LVDS	→	G_LVDSB_PIO
G_LVDS	→	G_LVDSC_PIO
G_LVDS	→	G_LVDSD_PIO
G_PG	→	G_PGA_PIO
G_PG	→	G_PGB_PIO
G_PG	→	G_PGC_PIO
G_PG	→	G_PGD_PIO
IOLDOA_TIOLOGIC	→	IOLDOA_PIO
IOLDOB_IOLOGIC	→	IOLDOB_PIO
IOLDOC_TSIOLOGIC	→	IOLDOC_PIO
IOLDOD_IOLOGIC	→	IOLDOD_PIO
IOLTOA_TIOLOGIC	→	IOLTOA_PIO
IOLTOB_IOLOGIC	→	IOLTOB_PIO
IOLTOC_TSIOLOGIC	→	IOLTOC_PIO
IOLTOD_IOLOGIC	→	IOLTOD_PIO
S1_JCE0	→	JCEA_TIOLOGIC
S1_JCE1	→	JCEB_IOLOGIC
S1_JCE2	→	JCEC_TSIOLOGIC
S1_JCE3	→	JCED_IOLOGIC
S1_JCLK0	→	JCLKA_TIOLOGIC
S1_JCLK1	→	JCLKB_IOLOGIC
S1_JCLK2	→	JCLKC_TSIOLOGIC
S1_JCLK3	→	JCLKD_IOLOGIC
JINA_TIOLOGIC	→	S1_JF0
JINB_IOLOGIC	→	S1_JF1
JINC_TSIOLOGIC	→	S1_JF2
JIND_IOLOGIC	→	S1_JF3
JIPA_TIOLOGIC	→	S1_JF4
JIPB_IOLOGIC	→	S1_JF5
JIPC_TSIOLOGIC	→	S1_JF6
JIPD_IOLOGIC	→	S1_JF7
S1_JLSR0	→	JLSRA_TIOLOGIC
S1_JLSR1	→	JLSRB_IOLOGIC
S1_JLSR2	→	JLSRC_TSIOLOGIC
S1_JLSR3	→	JLSRD_IOLOGIC
S1_JB0	→	JONEGA_TIOLOGIC
S1_JB1	→	JONEGB_IOLOGIC
S1_JB2	→	JONEGC_TSIOLOGIC
S1_JB3	→	JONEGD_IOLOGIC
S1_JA0	→	JOPOSA_TIOLOGIC
S1_JA1	→	JOPOSB_IOLOGIC
S1_JA2	→	JOPOSC_TSIOLOGIC
S1_JA3	→	JOPOSD_IOLOGIC
S1_JA0	→	JPADDOA
S1_JA1	→	JPADDOB
S1_JA2	→	JPADDOC
S1_JA3	→	JPADDOD
S1_JC0	→	JPADDTA
S1_JC1	→	JPADDTB
S1_JC2	→	JPADDTC
S1_JC3	→	JPADDTD
S1_JC0	→	JTSA_TIOLOGIC
S1_JC1	→	JTSB_IOLOGIC
S1_JC2	→	JTSC_TSIOLOGIC
S1_JC3	→	JTSD_IOLOGIC
S1_JA0	→	JTXD0A_TIOLOGIC
S1_JD0	→	JTXD0C_TSIOLOGIC
S1_JB0	→	JTXD1A_TIOLOGIC
S1_JD1	→	JTXD1C_TSIOLOGIC
S1_JA1	→	JTXD2A_TIOLOGIC
S1_JD2	→	JTXD2C_TSIOLOGIC
S1_JB1	→	JTXD3A_TIOLOGIC
S1_JD3	→	JTXD3C_TSIOLOGIC
S1_JD0	→	JTXD4A_TIOLOGIC
S1_JD1	→	JTXD5A_TIOLOGIC
S1_JD2	→	JTXD6A_TIOLOGIC
S1_JD3	→	JTXD7A_TIOLOGIC
JPADDIA_PIO	→	PADDIA_TIOLOGIC
JPADDIB_PIO	→	PADDIB_IOLOGIC
JPADDIC_PIO	→	PADDIC_TSIOLOGIC
JPADDID_PIO	→	PADDID_IOLOGIC
JPADDOA	→	PADDOA_PIO
JPADDOB	→	PADDOB_PIO
JPADDOC	→	PADDOC_PIO
JPADDOD	→	PADDOD_PIO
JPADDTA	→	PADDTA_PIO
JPADDTB	→	PADDTB_PIO
JPADDTC	→	PADDTC_PIO
JPADDTD	→	PADDTD_PIO



T	T		R	I	E
T	T	R	M	R	M
		G	O	C	C
		V	V	V	V
T	T		S	C	V
T	T
T	T		T	T	L
T	T	Q	L	C	O
D	D	T	O	O	M
D	D				L
D	D
D	D				T
O	O		R	I	R
O	O	E	M	R
P	P	G	O	C	C
P	P	V	V	V	V
D	D	L	S	C	V
D	D
O	O		T	T
O	O	Q	L	C	O
D	D	T	O	O
D	D				L
P	P
P	P
P	P		R	I
P	P	R	M	R	M
S	S	G	O	C	C
S	S	V	V	V	V
	T	L	S	C	V

T	T		T	T	O
T	T	Q	L	C	L
H	H	T	O	O	M
H	H	L	L
D	D
D	D				T
C	C		R	I
C	C	R	M	R
		G	O	C	C
		V	V	V	V
		L	S	C	V

			T	T
		Q	L	C	O
		T	O	O	L



T	T		R	I	E
T	T	R	M	R	M
		G	O	C	C
		V	V	V	V
T	T		S	C	V
T	T
T	T		T	T	L
T	T	Q	L	C	O
D	D	T	O	O	M
D	D				L
D	D
D	D				T
O	O		R	I	R
O	O	E	M	R
P	P	G	O	C	C
P	P	V	V	V	V
D	D	L	S	C	V
D	D
O	O		T	T
O	O	Q	L	C	O
D	D	T	O	O
D	D				L
P	P
P	P
P	P		R	I
P	P	R	M	R	M
S	S	G	O	C	C
S	S	V	V	V	V
	T	L	S	C	V

T	T		T	T	O
T	T	Q	L	C	L
H	H	T	O	O	M
H	H	L	L
D	D
D	D				T
C	C		R	I
C	C	R	M	R
		G	O	C	C
		V	V	V	V
		L	S	C	V

			T	T
		Q	L	C	O
		T	O	O	L



T	T		R	I	E
T	T	R	M	R	M
		G	O	C	C
		V	V	V	V
T	T		S	C	V
T	T
T	T		T	T	L
T	T	Q	L	C	O
D	D	T	O	O	M
D	D				L
D	D
D	D				T
O	O		R	I	R
O	O	E	M	R
P	P	G	O	C	C
P	P	V	V	V	V
D	D	L	S	C	V
D	D
O	O		T	T
O	O	Q	L	C	O
D	D	T	O	O
D	D				L
P	P
P	P
P	P		R	I
P	P	R	M	R	M
S	S	G	O	C	C
S	S	V	V	V	V
	T	L	S	C	V

T	T		T	T	O
T	T	Q	L	C	L
H	H	T	O	O	M
H	H	L	L
D	D
D	D				T
C	C		R	I
C	C	R	M	R
		G	O	C	C
		V	V	V	V
		L	S	C	V

			T	T
		Q	L	C	O
		T	O	O	L