GPLL_R0 Bit Data


W	C		F	C	D
E	C		F	E	D
	C	D	F	D	D
	C	D	E	D	D
	C	D		D	D
	K	D		D	D
	K	R	P	D	D
	K	R	W	D	D
	R	R		D	D
	R	U		R	D
	R	R	P	D	D
	R	R	E	D	D
	R	R		D	D
	R	R		D	D
	R	C	P	D	D
	P	C		D	D
	T	C		D	C
	T	P	P	E	C
	T	P	A	D	C
	T	P	A	D	C
	T	O	M	D	C
	T	O	M	D	C
	S	D	M	D	C
	S	D	M	D
	A	D	M	D	C
	B	D	M	E	C
	C	D	M	D	C
	D	D	M	D	C
	T	D	D	D	C
	T	R	D	D	C
	T	D	D	D	C
	T	D	P	D	M
	C	D	D	D	C
	C	D	D	E	C
		D	D	F	C
		D	P	F	C
		D	P	F	C
		V	P	S	C
		G	P	F	C
		G	P	F
		G	M	F	C
		I	M	E	C
		F	M	F	C
		T	S	F	C
		R		F	C
		P			C

Mux driving S1W1_CLKFB

Source	F2B15	F2B16	F2B17
S1W1_CLKINTFB	-	-	-
S1W1_JCLKFB0	-	-	-
S1W1_JCLKFB1	1	-	-
S1W1_JCLKFB2	-	1	-
G_TECLK1	1	1	-
S1W1_JCLKFB4	-	-	1
G_TECLK0	1	-	1

Mux driving S1W1_JCLKOP_PLL

Source	F3B7	F3B37
S1W1_CLKI_PLL	1	1

Mux driving S1W1_JCLKOS2_PLL

Source	F3B18	F3B39
S1W1_CLKI_PLL	1	1

Mux driving S1W1_JCLKOS3_PLL

Source	F3B15	F3B40
S1W1_CLKI_PLL	1	1

Mux driving S1W1_JCLKOS_PLL

Source	F3B11	F3B38
S1W1_CLKI_PLL	1	1

Mux driving S1W1_REFCLK0

Source	F2B11	F2B12	F2B13
S1W1_JREFCLK0	-	-	-
S1W1_JREFCLK1_0	1	-	-
S1W1_JREFCLK2_0	-	1	-
S1W1_JREFCLK3	1	1	-
S1W1_JREFCLK4	-	-	1
S1W1_JREFCLK5	1	-	1
S1W1_JREFCLK6	-	1	1
S1W1_JREFCLK7	1	1	1

Mux driving S1W1_REFCLK1

Source	F2B7	F2B8	F2B9
S1W1_JREFCLK0	-	-	-
S1W1_JREFCLK1_1	1	-	-
S1W1_JREFCLK2_1	-	1	-
S1W1_JREFCLK3	1	1	-
S1W1_JREFCLK4	-	-	1
S1W1_JREFCLK5	1	-	1
S1W1_JREFCLK6	-	1	1
S1W1_JREFCLK7	1	1	1

Configuration word CLKFB_DIV

Default value: 7'b0000000

CLKFB_DIV[0]	F2B31
CLKFB_DIV[1]	F2B32
CLKFB_DIV[2]	F2B33
CLKFB_DIV[3]	F2B34
CLKFB_DIV[4]	F2B35
CLKFB_DIV[5]	F2B36
CLKFB_DIV[6]	F2B37

Configuration word CLKI_DIV

Default value: 7'b0000000

CLKI_DIV[0]	F2B23
CLKI_DIV[1]	F2B24
CLKI_DIV[2]	F2B25
CLKI_DIV[3]	F2B26
CLKI_DIV[4]	F2B27
CLKI_DIV[5]	F2B28
CLKI_DIV[6]	F2B29

Configuration word CLKOP_CPHASE

Default value: 7'b0000000

CLKOP_CPHASE[0]	F5B17
CLKOP_CPHASE[1]	F5B18
CLKOP_CPHASE[2]	F5B19
CLKOP_CPHASE[3]	F5B20
CLKOP_CPHASE[4]	F5B21
CLKOP_CPHASE[5]	F5B22
CLKOP_CPHASE[6]	F5B23

Configuration word CLKOP_DIV

Default value: 7'b0000000

CLKOP_DIV[0]	F4B3
CLKOP_DIV[1]	F4B4
CLKOP_DIV[2]	F4B5
CLKOP_DIV[3]	F4B6
CLKOP_DIV[4]	F4B7
CLKOP_DIV[5]	F4B8
CLKOP_DIV[6]	F4B9

Configuration word CLKOP_FPHASE

Default value: 3'b000

CLKOP_FPHASE[0]	F4B35
CLKOP_FPHASE[1]	F4B36
CLKOP_FPHASE[2]	F4B37

Configuration word CLKOS2_CPHASE

Default value: 7'b0000000

CLKOS2_CPHASE[0]	F5B33
CLKOS2_CPHASE[1]	F5B34
CLKOS2_CPHASE[2]	F5B35
CLKOS2_CPHASE[3]	F5B36
CLKOS2_CPHASE[4]	F5B37
CLKOS2_CPHASE[5]	F5B38
CLKOS2_CPHASE[6]	F5B39

Configuration word CLKOS2_DIV

Default value: 7'b0000000

CLKOS2_DIV[0]	F4B19
CLKOS2_DIV[1]	F4B20
CLKOS2_DIV[2]	F4B21
CLKOS2_DIV[3]	F4B22
CLKOS2_DIV[4]	F4B23
CLKOS2_DIV[5]	F4B24
CLKOS2_DIV[6]	F4B25

Configuration word CLKOS2_FPHASE

Default value: 3'b000

CLKOS2_FPHASE[0]	F4B43
CLKOS2_FPHASE[1]	F4B44
CLKOS2_FPHASE[2]	F4B45

Configuration word CLKOS3_CPHASE

Default value: 7'b0000000

CLKOS3_CPHASE[0]	F5B41
CLKOS3_CPHASE[1]	F5B42
CLKOS3_CPHASE[2]	F5B43
CLKOS3_CPHASE[3]	F5B44
CLKOS3_CPHASE[4]	F5B45
CLKOS3_CPHASE[5]	F5B46
CLKOS3_CPHASE[6]	F4B1

Configuration word CLKOS3_DIV

Default value: 7'b0000000

CLKOS3_DIV[0]	F4B27
CLKOS3_DIV[1]	F4B28
CLKOS3_DIV[2]	F4B29
CLKOS3_DIV[3]	F4B30
CLKOS3_DIV[4]	F4B31
CLKOS3_DIV[5]	F4B32
CLKOS3_DIV[6]	F4B33

Configuration word CLKOS3_FPHASE

Default value: 3'b000

CLKOS3_FPHASE[0]	F3B1
CLKOS3_FPHASE[1]	F3B2
CLKOS3_FPHASE[2]	F3B3

Configuration word CLKOS_CPHASE

Default value: 7'b0000000

CLKOS_CPHASE[0]	F5B25
CLKOS_CPHASE[1]	F5B26
CLKOS_CPHASE[2]	F5B27
CLKOS_CPHASE[3]	F5B28
CLKOS_CPHASE[4]	F5B29
CLKOS_CPHASE[5]	F5B30
CLKOS_CPHASE[6]	F5B31

Configuration word CLKOS_DIV

Default value: 7'b0000000

CLKOS_DIV[0]	F4B11
CLKOS_DIV[1]	F4B12
CLKOS_DIV[2]	F4B13
CLKOS_DIV[3]	F4B14
CLKOS_DIV[4]	F4B15
CLKOS_DIV[5]	F4B16
CLKOS_DIV[6]	F4B17

Configuration word CLKOS_FPHASE

Default value: 3'b000

CLKOS_FPHASE[0]	F4B39
CLKOS_FPHASE[1]	F4B40
CLKOS_FPHASE[2]	F4B41

Configuration word FRACN_DIV

Default value: 16'b0000000000000000

FRACN_DIV[0]	F5B1
FRACN_DIV[1]	F5B2
FRACN_DIV[2]	F5B3
FRACN_DIV[3]	F5B4
FRACN_DIV[4]	F5B5
FRACN_DIV[5]	F5B6
FRACN_DIV[6]	F5B7
FRACN_DIV[7]	F5B8
FRACN_DIV[8]	F5B9
FRACN_DIV[9]	F5B10
FRACN_DIV[10]	F5B11
FRACN_DIV[11]	F5B12
FRACN_DIV[12]	F5B13
FRACN_DIV[13]	F5B14
FRACN_DIV[14]	F5B15
FRACN_DIV[15]	F5B16

Configuration word FRACN_ORDER

Default value: 2'b00

FRACN_ORDER[0]	F2B21
FRACN_ORDER[1]	F2B22

Configuration word FREQ_LOCK_ACCURACY

Default value: 2'b00

FREQ_LOCK_ACCURACY[0]	F3B19
FREQ_LOCK_ACCURACY[1]	F3B20

Configuration word GMC_GAIN

Default value: 3'b000

GMC_GAIN[0]	F2B39
GMC_GAIN[1]	F2B40
GMC_GAIN[2]	F2B41

Configuration word GMC_TEST

Default value: 4'b0000

GMC_TEST[0]	F1B29
GMC_TEST[1]	F1B30
GMC_TEST[2]	F1B31
GMC_TEST[3]	F1B32

Configuration word ICP_CURRENT

Default value: 5'b00000

ICP_CURRENT[0]	F1B1
ICP_CURRENT[1]	F1B2
ICP_CURRENT[2]	F1B3
ICP_CURRENT[3]	F1B4
ICP_CURRENT[4]	F1B5

Configuration word KVCO

Default value: 3'b000

KVCO[0]	F1B6
KVCO[1]	F1B7
KVCO[2]	F1B8

Configuration word LPF_CAPACITOR

Default value: 2'b00

LPF_CAPACITOR[0]	F1B33
LPF_CAPACITOR[1]	F1B34

Configuration word LPF_RESISTOR

Default value: 7'b0000000

LPF_RESISTOR[0]	F1B9
LPF_RESISTOR[1]	F1B10
LPF_RESISTOR[2]	F1B11
LPF_RESISTOR[3]	F1B12
LPF_RESISTOR[4]	F1B13
LPF_RESISTOR[5]	F1B14
LPF_RESISTOR[6]	F1B15

Configuration word MFG1_TEST

Default value: 3'b000

MFG1_TEST[0]	F1B17
MFG1_TEST[1]	F1B18
MFG1_TEST[2]	F1B19

Configuration word MFG2_TEST

Default value: 3'b000

MFG2_TEST[0]	F1B20
MFG2_TEST[1]	F1B21
MFG2_TEST[2]	F1B22

Configuration bit MFG_ENABLE_FILTEROPAMP

Default value: 1'b0

MFG_ENABLE_FILTEROPAMP[0]

F2B43

Configuration bit MFG_EN_UP

Default value: 1'b0

MFG_EN_UP[0]

F2B10

Configuration bit MFG_FLOAT_ICP

Default value: 1'b0

MFG_FLOAT_ICP[0]

F2B42

Configuration bit MFG_FORCE_VFILTER

Default value: 1'b0

MFG_FORCE_VFILTER[0]

F2B38

Configuration word MFG_GMCREF_SEL

Default value: 2'b00

MFG_GMCREF_SEL[0]	F1B23
MFG_GMCREF_SEL[1]	F1B24

Configuration bit MFG_GMC_PRESET

Default value: 1'b0

MFG_GMC_PRESET[0]

F1B16

Configuration bit MFG_GMC_RESET

Default value: 1'b0

MFG_GMC_RESET[0]

F2B30

Configuration bit MFG_ICP_TEST

Default value: 1'b0

MFG_ICP_TEST[0]

F2B44

Configuration bit MFG_LF_PRESET

Default value: 1'b0

MFG_LF_PRESET[0]

F2B46

Configuration bit MFG_LF_RESET

Default value: 1'b0

MFG_LF_RESET[0]

F2B45

Configuration bit MFG_LF_RESGRND

Default value: 1'b0

MFG_LF_RESGRND[0]

F2B14

Configuration word PLL_LOCK_MODE

Default value: 3'b000

PLL_LOCK_MODE[0]	F3B41
PLL_LOCK_MODE[1]	F3B42
PLL_LOCK_MODE[2]	F3B43

Configuration word PREDIVIDER_MUXA1

Default value: 2'b00

PREDIVIDER_MUXA1[0]	F3B27
PREDIVIDER_MUXA1[1]	F3B28

Configuration word PREDIVIDER_MUXB1

Default value: 2'b00

PREDIVIDER_MUXB1[0]	F3B25
PREDIVIDER_MUXB1[1]	F3B26

Configuration word PREDIVIDER_MUXC1

Default value: 2'b00

PREDIVIDER_MUXC1[0]	F3B23
PREDIVIDER_MUXC1[1]	F3B24

Configuration word PREDIVIDER_MUXD1

Default value: 2'b00

PREDIVIDER_MUXD1[0]	F3B21
PREDIVIDER_MUXD1[1]	F3B22

Configuration Setting CLKOP_ENABLE

Default value: DISABLED

Value	F3B37
DISABLED	-
ENABLED	1

Configuration Setting CLKOP_TRIM_DELAY

Default value: 0

Value	F2B3	F2B4	F2B5	F2B6	F3B33	F3B34	F3B35
0	0	0	0	0	0	0	0
1	1	1	1	1	1	0	0
2	1	1	1	1	0	1	0
4	1	1	1	1	0	0	1

Configuration Setting CLKOP_TRIM_POL

Default value: FALLING

Value	F3B36
FALLING	0
RISING	1

Configuration Setting CLKOS2_ENABLE

Default value: DISABLED

Value	F3B39
DISABLED	-
ENABLED	1

Configuration Setting CLKOS3_ENABLE

Default value: DISABLED

Value	F3B40
DISABLED	-
ENABLED	1

Configuration Setting CLKOS_ENABLE

Default value: DISABLED

Value	F3B38
DISABLED	-
ENABLED	1

Configuration Setting CLKOS_TRIM_DELAY

Default value: 0

Value	F2B4	F3B29	F3B30	F3B31
0	0	0	0	0
1	1	1	0	0
2	1	0	1	0
4	1	0	0	1

Configuration Setting CLKOS_TRIM_POL

Default value: FALLING

Value	F3B32
FALLING	0
RISING	1

Configuration Setting CLOCK_ENABLE_PORTS

Default value: ENABLED

Value	F3B37	F3B38	F3B39	F3B40
DISABLED	1	1	1	1
ENABLED	-	-	-	-

Configuration Setting DCRST_ENA

Default value: DISABLED

Value	F3B4
DISABLED	0
ENABLED	1

Configuration Setting DDRST_ENA

Default value: DISABLED

Value	F3B12
DISABLED	0
ENABLED	1

Configuration Setting DPHASE_SOURCE

Default value: DISABLED

Value	F3B44
DISABLED	0
ENABLED	1

Configuration Setting FEEDBK_PATH

Default value: USERCLOCK

Value	F2B15	F2B16	F2B18	F2B19	F2B20
CLKOP	-	-	-	-	-
CLKOS	-	-	-	-	-
INT_DIVA	1	1	1	-	-
INT_DIVB	-	1	1	1	-
INT_DIVC	1	-	1	-	1
INT_DIVD	-	-	1	1	1
USERCLOCK	-	-	-	-	-
CLKOS2	-	-	-	-	-
CLKOS3	-	-	-	-	-

Configuration Setting FRACN_ENABLE

Default value: DISABLED

Value	F4B2
DISABLED	-
ENABLED	1

Configuration Setting INTFB_WAKE

Default value: DISABLED

Value	F3B8
DISABLED	0
ENABLED	1

Configuration Setting INT_LOCK_STICKY

Default value: DISABLED

Value	F4B38
DISABLED	0
ENABLED	1

Configuration Setting MODE

Default value: NONE

Value	F5B32
NONE	-
EHXPLLJ	1

Configuration Setting MRST_ENA

Default value: DISABLED

Value	F4B26
DISABLED	0
ENABLED	1

Configuration Setting OUTDIVIDER_MUXA2

Default value: DIVA

Value	F3B7
DIVA	-
REFCLK	1

Configuration Setting OUTDIVIDER_MUXB2

Default value: DIVB

Value	F3B11
DIVB	-
REFCLK	1

Configuration Setting OUTDIVIDER_MUXC2

Default value: DIVC

Value	F3B18
DIVC	-
REFCLK	1

Configuration Setting OUTDIVIDER_MUXD2

Default value: DIVD

Value	F3B15
DIVD	-
REFCLK	1

Configuration Setting PLLRST_ENA

Default value: DISABLED

Value	F4B18
DISABLED	0
ENABLED	1

Configuration Setting PLL_EXPERT

Default value: DISABLED

Value	F0B2
DISABLED	-
ENABLED	1

Configuration Setting PLL_USE_WB

Default value: DISABLED

Value	F0B1
DISABLED	-
ENABLED	1

Configuration Setting REFIN_RESET

Default value: DISABLED

Value	F4B10
DISABLED	0
ENABLED	1

Configuration Setting STDBY_ENABLE

Default value: DISABLED

Value	F4B34
DISABLED	0
ENABLED	1

Configuration Setting SYNC_ENABLE

Default value: DISABLED

Value	F4B42
DISABLED	0
ENABLED	1

Configuration Setting VCO_BYPASS_A0

Default value: ENABLED

Value	F1B25
DISABLED	1
ENABLED	-

Configuration Setting VCO_BYPASS_B0

Default value: ENABLED

Value	F1B26
DISABLED	1
ENABLED	-

Configuration Setting VCO_BYPASS_C0

Default value: ENABLED

Value	F1B27
DISABLED	1
ENABLED	-

Configuration Setting VCO_BYPASS_D0

Default value: ENABLED

Value	F1B28
DISABLED	1
ENABLED	-

Fixed Connections

Source		Sink
S1W1_JCLKOP_PLL	→	4000_S1W16_JPLLCLKOP1
S1W1_JCLKOS_PLL	→	4000_S1W16_JPLLCLKOS1
S1W1_JPLLACK_PLL	→	4000_S1W28_JPLL1ACKI
S1W1_JPLLDATO0_PLL	→	4000_S1W28_JPLL1DATI0
S1W1_JPLLDATO1_PLL	→	4000_S1W28_JPLL1DATI1
S1W1_JPLLDATO2_PLL	→	4000_S1W28_JPLL1DATI2
S1W1_JPLLDATO3_PLL	→	4000_S1W28_JPLL1DATI3
S1W1_JPLLDATO4_PLL	→	4000_S1W28_JPLL1DATI4
S1W1_JPLLDATO5_PLL	→	4000_S1W28_JPLL1DATI5
S1W1_JPLLDATO6_PLL	→	4000_S1W28_JPLL1DATI6
S1W1_JPLLDATO7_PLL	→	4000_S1W28_JPLL1DATI7
S1W1_JCLKOP_PLL	→	4000_S21W16_JA1_CLKFBBUF
S1W1_JCLKOP_PLL	→	4000_S21W16_JPLLCLKOP1
S1W1_JCLKOS_PLL	→	4000_S21W16_JPLLCLKOS1
S1W1_JCLKOP_PLL	→	7000_S1W22_JPLLCLKOP1
S1W1_JCLKOS_PLL	→	7000_S1W22_JPLLCLKOS1
S1W1_JPLLACK_PLL	→	7000_S1W37_JPLL1ACKI
S1W1_JPLLDATO0_PLL	→	7000_S1W37_JPLL1DATI0
S1W1_JPLLDATO1_PLL	→	7000_S1W37_JPLL1DATI1
S1W1_JPLLDATO2_PLL	→	7000_S1W37_JPLL1DATI2
S1W1_JPLLDATO3_PLL	→	7000_S1W37_JPLL1DATI3
S1W1_JPLLDATO4_PLL	→	7000_S1W37_JPLL1DATI4
S1W1_JPLLDATO5_PLL	→	7000_S1W37_JPLL1DATI5
S1W1_JPLLDATO6_PLL	→	7000_S1W37_JPLL1DATI6
S1W1_JPLLDATO7_PLL	→	7000_S1W37_JPLL1DATI7
S1W1_JCLKOP_PLL	→	7000_S26W22_JA1_CLKFBBUF
S1W1_JCLKOP_PLL	→	7000_S26W22_JPLLCLKOP1
S1W1_JCLKOS_PLL	→	7000_S26W22_JPLLCLKOS1
S1W1_REFCLK0	→	S1W1_CLK0_PLLREFCS
S1W1_REFCLK1	→	S1W1_CLK1_PLLREFCS
S1W1_CLKFB	→	S1W1_CLKFB_PLL
S1W1_CLKINTFB_PLL	→	S1W1_CLKINTFB
S1W1_PLLCSOUT_PLLREFCS	→	S1W1_CLKI_PLL
S1W1_JCLKOP_PLL	→	G_JRPLLCLK0
S1W1_JCLKOS_PLL	→	G_JRPLLCLK1
S1W1_JCLKOS2_PLL	→	G_JRPLLCLK2
S1W1_JCLKOS3_PLL	→	G_JRPLLCLK3
S1W1_JCLK1	→	S1W1_JCLKFB1
4000_S21W16_JPLLCLKFB1	→	S1W1_JCLKFB2
7000_S26W22_JPLLCLKFB1	→	S1W1_JCLKFB2
4000_S21W16_JPLLCLKFB0	→	S1W1_JCLKFB4
7000_S26W22_JPLLCLKFB0	→	S1W1_JCLKFB4
S1W1_JD2	→	S1W1_JENCLKOP_PLL
S1W1_JB3	→	S1W1_JENCLKOS2_PLL
S1W1_JC3	→	S1W1_JENCLKOS3_PLL
S1W1_JA3	→	S1W1_JENCLKOS_PLL
S1W1_JCLKOP_PLL	→	S1W1_JF0
S1W1_JCLKOS_PLL	→	S1W1_JF2
S1W1_JCLKOS2_PLL	→	S1W1_JF4
S1W1_JCLKOS3_PLL	→	S1W1_JF6
S1W1_JD3	→	S1W1_JLOADREG_PLL
S1W1_JD4	→	S1W1_JPHASEDIR_PLL
S1W1_JB4	→	S1W1_JPHASESEL0_PLL
S1W1_JA4	→	S1W1_JPHASESEL1_PLL
S1W1_JC4	→	S1W1_JPHASESTEP_PLL
4000_S1W28_JPLLADRO0_EFB	→	S1W1_JPLLADDR0_PLL
7000_S1W37_JPLLADRO0_EFB	→	S1W1_JPLLADDR0_PLL
4000_S1W28_JPLLADRO1_EFB	→	S1W1_JPLLADDR1_PLL
7000_S1W37_JPLLADRO1_EFB	→	S1W1_JPLLADDR1_PLL
4000_S1W28_JPLLADRO2_EFB	→	S1W1_JPLLADDR2_PLL
7000_S1W37_JPLLADRO2_EFB	→	S1W1_JPLLADDR2_PLL
4000_S1W28_JPLLADRO3_EFB	→	S1W1_JPLLADDR3_PLL
7000_S1W37_JPLLADRO3_EFB	→	S1W1_JPLLADDR3_PLL
4000_S1W28_JPLLADRO4_EFB	→	S1W1_JPLLADDR4_PLL
7000_S1W37_JPLLADRO4_EFB	→	S1W1_JPLLADDR4_PLL
4000_S1W28_JPLLCLKO_EFB	→	S1W1_JPLLCLK_PLL
7000_S1W37_JPLLCLKO_EFB	→	S1W1_JPLLCLK_PLL
4000_S1W28_JPLLDATO0_EFB	→	S1W1_JPLLDATI0_PLL
7000_S1W37_JPLLDATO0_EFB	→	S1W1_JPLLDATI0_PLL
4000_S1W28_JPLLDATO1_EFB	→	S1W1_JPLLDATI1_PLL
7000_S1W37_JPLLDATO1_EFB	→	S1W1_JPLLDATI1_PLL
4000_S1W28_JPLLDATO2_EFB	→	S1W1_JPLLDATI2_PLL
7000_S1W37_JPLLDATO2_EFB	→	S1W1_JPLLDATI2_PLL
4000_S1W28_JPLLDATO3_EFB	→	S1W1_JPLLDATI3_PLL
7000_S1W37_JPLLDATO3_EFB	→	S1W1_JPLLDATI3_PLL
4000_S1W28_JPLLDATO4_EFB	→	S1W1_JPLLDATI4_PLL
7000_S1W37_JPLLDATO4_EFB	→	S1W1_JPLLDATI4_PLL
4000_S1W28_JPLLDATO5_EFB	→	S1W1_JPLLDATI5_PLL
7000_S1W37_JPLLDATO5_EFB	→	S1W1_JPLLDATI5_PLL
4000_S1W28_JPLLDATO6_EFB	→	S1W1_JPLLDATI6_PLL
7000_S1W37_JPLLDATO6_EFB	→	S1W1_JPLLDATI6_PLL
4000_S1W28_JPLLDATO7_EFB	→	S1W1_JPLLDATI7_PLL
7000_S1W37_JPLLDATO7_EFB	→	S1W1_JPLLDATI7_PLL
4000_S1W28_JPLLRSTO_EFB	→	S1W1_JPLLRST_PLL
7000_S1W37_JPLLRSTO_EFB	→	S1W1_JPLLRST_PLL
4000_S1W28_JPLL1STBOMUX	→	S1W1_JPLLSTB_PLL
7000_S1W37_JPLL1STBOMUX	→	S1W1_JPLLSTB_PLL
S1W1_JC2	→	S1W1_JPLLWAKESYNC_PLL
4000_S1W28_JPLLWEO_EFB	→	S1W1_JPLLWE_PLL
7000_S1W37_JPLLWEO_EFB	→	S1W1_JPLLWE_PLL
S1W1_JREFCLK_PLL	→	S1W1_JQ0
S1W1_JLOCK_PLL	→	S1W1_JQ2
S1W1_JINTLOCK_PLL	→	S1W1_JQ4
S1W1_JDPHSRC_PLL	→	S1W1_JQ6
G_JOSC_OSC	→	S1W1_JREFCLK0
S1W1_JA0	→	S1W1_JREFCLK1_0
S1W2_JA0	→	S1W1_JREFCLK1_1
S1W1_JCLK0	→	S1W1_JREFCLK2_0
S1W2_JCLK0	→	S1W1_JREFCLK2_1
S1W1_CLKI_PLL	→	S1W1_JREFCLK_PLL
S1W1_JD1	→	S1W1_JRESETC_PLL
S1W1_JA2	→	S1W1_JRESETD_PLL
S1W1_JC1	→	S1W1_JRESETM_PLL
S1W1_JB1	→	S1W1_JRST_PLL
S1W1_JB2	→	S1W1_JSEL_PLLREFCS
S1W1_JLSR0	→	S1W1_JSTDBY_PLL
S1W1_CLK0_PLLREFCS	→	S1W1_PLLCSOUT_PLLREFCS


W	C		F	C	D
E	C		F	E	D
	C	D	F	D	D
	C	D	E	D	D
	C	D		D	D
	K	D		D	D
	K	R	P	D	D
	K	R	W	D	D
	R	R		D	D
	R	U		R	D
	R	R	P	D	D
	R	R	E	D	D
	R	R		D	D
	R	R		D	D
	R	C	P	D	D
	P	C		D	D
	T	C		D	C
	T	P	P	E	C
	T	P	A	D	C
	T	P	A	D	C
	T	O	M	D	C
	T	O	M	D	C
	S	D	M	D	C
	S	D	M	D
	A	D	M	D	C
	B	D	M	E	C
	C	D	M	D	C
	D	D	M	D	C
	T	D	D	D	C
	T	R	D	D	C
	T	D	D	D	C
	T	D	P	D	M
	C	D	D	D	C
	C	D	D	E	C
		D	D	F	C
		D	P	F	C
		D	P	F	C
		V	P	S	C
		G	P	F	C
		G	P	F
		G	M	F	C
		I	M	E	C
		F	M	F	C
		T	S	F	C
		R		F	C
		P			C


W	C		F	C	D
E	C		F	E	D
	C	D	F	D	D
	C	D	E	D	D
	C	D		D	D
	K	D		D	D
	K	R	P	D	D
	K	R	W	D	D
	R	R		D	D
	R	U		R	D
	R	R	P	D	D
	R	R	E	D	D
	R	R		D	D
	R	R		D	D
	R	C	P	D	D
	P	C		D	D
	T	C		D	C
	T	P	P	E	C
	T	P	A	D	C
	T	P	A	D	C
	T	O	M	D	C
	T	O	M	D	C
	S	D	M	D	C
	S	D	M	D
	A	D	M	D	C
	B	D	M	E	C
	C	D	M	D	C
	D	D	M	D	C
	T	D	D	D	C
	T	R	D	D	C
	T	D	D	D	C
	T	D	P	D	M
	C	D	D	D	C
	C	D	D	E	C
		D	D	F	C
		D	P	F	C
		D	P	F	C
		V	P	S	C
		G	P	F	C
		G	P	F
		G	M	F	C
		I	M	E	C
		F	M	F	C
		T	S	F	C
		R		F	C
		P			C


W	C		F	C	D
E	C		F	E	D
	C	D	F	D	D
	C	D	E	D	D
	C	D		D	D
	K	D		D	D
	K	R	P	D	D
	K	R	W	D	D
	R	R		D	D
	R	U		R	D
	R	R	P	D	D
	R	R	E	D	D
	R	R		D	D
	R	R		D	D
	R	C	P	D	D
	P	C		D	D
	T	C		D	C
	T	P	P	E	C
	T	P	A	D	C
	T	P	A	D	C
	T	O	M	D	C
	T	O	M	D	C
	S	D	M	D	C
	S	D	M	D
	A	D	M	D	C
	B	D	M	E	C
	C	D	M	D	C
	D	D	M	D	C
	T	D	D	D	C
	T	R	D	D	C
	T	D	D	D	C
	T	D	P	D	M
	C	D	D	D	C
	C	D	D	E	C
		D	D	F	C
		D	P	F	C
		D	P	F	C
		V	P	S	C
		G	P	F	C
		G	P	F
		G	M	F	C
		I	M	E	C
		F	M	F	C
		T	S	F	C
		R		F	C
		P			C