ECP5 Speed Grade -8_5G Cell Timings

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
IOLOGIC:MODE=IDDRX1F
IOLOGIC:MODE=IDDRX2F
IOLOGIC:MODE=IREG
IOLOGIC:MODE=ODDRX1F
IOLOGIC:MODE=ODDRX2F
IOLOGIC:MODE=OREG
IOLOGIC:MODE=TSREG
MULT18X18D:REGS=ALL
MULT18X18D:REGS=INPUT
MULT18X18D:REGS=NONE
MULT18X18D:REGS=OUTPUT
MULT18X18D:REGS=PIPELINE
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SCCU2C
SDPRAME
SLOGICB
SRAMWB

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	1356	1360	1364	1356	1360	1364
CLKA	DOA1	1356	1360	1364	1356	1360	1364
CLKA	DOA10	1356	1360	1364	1356	1360	1364
CLKA	DOA11	1356	1360	1364	1356	1360	1364
CLKA	DOA12	1356	1360	1364	1356	1360	1364
CLKA	DOA13	1356	1360	1364	1356	1360	1364
CLKA	DOA14	1356	1360	1364	1356	1360	1364
CLKA	DOA15	1356	1360	1364	1356	1360	1364
CLKA	DOA16	1356	1360	1364	1356	1360	1364
CLKA	DOA17	1356	1360	1364	1356	1360	1364
CLKA	DOA2	1356	1360	1364	1356	1360	1364
CLKA	DOA3	1356	1360	1364	1356	1360	1364
CLKA	DOA4	1356	1360	1364	1356	1360	1364
CLKA	DOA5	1356	1360	1364	1356	1360	1364
CLKA	DOA6	1356	1360	1364	1356	1360	1364
CLKA	DOA7	1356	1360	1364	1356	1360	1364
CLKA	DOA8	1356	1360	1364	1356	1360	1364
CLKA	DOA9	1356	1360	1364	1356	1360	1364
CLKB	DOB0	1413	1416	1419	1413	1416	1419
CLKB	DOB1	1413	1416	1419	1413	1416	1419
CLKB	DOB10	1413	1416	1419	1413	1416	1419
CLKB	DOB11	1413	1416	1419	1413	1416	1419
CLKB	DOB12	1413	1416	1419	1413	1416	1419
CLKB	DOB13	1413	1416	1419	1413	1416	1419
CLKB	DOB14	1413	1416	1419	1413	1416	1419
CLKB	DOB15	1413	1416	1419	1413	1416	1419
CLKB	DOB16	1413	1416	1419	1413	1416	1419
CLKB	DOB17	1413	1416	1419	1413	1416	1419
CLKB	DOB2	1413	1416	1419	1413	1416	1419
CLKB	DOB3	1413	1416	1419	1413	1416	1419
CLKB	DOB4	1413	1416	1419	1413	1416	1419
CLKB	DOB5	1413	1416	1419	1413	1416	1419
CLKB	DOB6	1413	1416	1419	1413	1416	1419
CLKB	DOB7	1413	1416	1419	1413	1416	1419
CLKB	DOB8	1413	1416	1419	1413	1416	1419
CLKB	DOB9	1413	1416	1419	1413	1416	1419

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	67	67	67	1	1	1
ADA1	posedge CLKA	67	67	67	1	1	1
ADA10	posedge CLKA	67	67	67	1	1	1
ADA11	posedge CLKA	67	67	67	1	1	1
ADA12	posedge CLKA	67	67	67	1	1	1
ADA13	posedge CLKA	67	67	67	1	1	1
ADA2	posedge CLKA	67	67	67	1	1	1
ADA3	posedge CLKA	67	67	67	1	1	1
ADA4	posedge CLKA	67	67	67	1	1	1
ADA5	posedge CLKA	67	67	67	1	1	1
ADA6	posedge CLKA	67	67	67	1	1	1
ADA7	posedge CLKA	67	67	67	1	1	1
ADA8	posedge CLKA	67	67	67	1	1	1
ADA9	posedge CLKA	67	67	67	1	1	1
ADB0	posedge CLKB	57	57	57	28	28	28
ADB1	posedge CLKB	57	57	57	28	28	28
ADB10	posedge CLKB	57	57	57	28	28	28
ADB11	posedge CLKB	57	57	57	28	28	28
ADB12	posedge CLKB	57	57	57	28	28	28
ADB13	posedge CLKB	57	57	57	28	28	28
ADB2	posedge CLKB	57	57	57	28	28	28
ADB3	posedge CLKB	57	57	57	28	28	28
ADB4	posedge CLKB	57	57	57	28	28	28
ADB5	posedge CLKB	57	57	57	28	28	28
ADB6	posedge CLKB	57	57	57	28	28	28
ADB7	posedge CLKB	57	57	57	28	28	28
ADB8	posedge CLKB	57	57	57	28	28	28
ADB9	posedge CLKB	57	57	57	28	28	28
CEA	posedge CLKA	52	52	52	24	24	24
CEB	posedge CLKB	85	85	85	23	23	23
CSA0	posedge CLKA	8	8	8	51	51	51
CSA1	posedge CLKA	8	8	8	51	51	51
CSA2	posedge CLKA	8	8	8	51	51	51
CSB0	posedge CLKB	0	0	0	98	98	98
CSB1	posedge CLKB	0	0	0	98	98	98
CSB2	posedge CLKB	0	0	0	98	98	98
DIA0	posedge CLKA	59	59	59	9	9	9
DIA1	posedge CLKA	59	59	59	9	9	9
DIA10	posedge CLKA	59	59	59	9	9	9
DIA11	posedge CLKA	59	59	59	9	9	9
DIA12	posedge CLKA	59	59	59	9	9	9
DIA13	posedge CLKA	59	59	59	9	9	9
DIA14	posedge CLKA	59	59	59	9	9	9
DIA15	posedge CLKA	59	59	59	9	9	9
DIA16	posedge CLKA	59	59	59	9	9	9
DIA17	posedge CLKA	59	59	59	9	9	9
DIA2	posedge CLKA	59	59	59	9	9	9
DIA3	posedge CLKA	59	59	59	9	9	9
DIA4	posedge CLKA	59	59	59	9	9	9
DIA5	posedge CLKA	59	59	59	9	9	9
DIA6	posedge CLKA	59	59	59	9	9	9
DIA7	posedge CLKA	59	59	59	9	9	9
DIA8	posedge CLKA	59	59	59	9	9	9
DIA9	posedge CLKA	59	59	59	9	9	9
DIB0	posedge CLKB	42	42	42	65	65	65
DIB1	posedge CLKB	42	42	42	65	65	65
DIB10	posedge CLKB	42	42	42	65	65	65
DIB11	posedge CLKB	42	42	42	65	65	65
DIB12	posedge CLKB	42	42	42	65	65	65
DIB13	posedge CLKB	42	42	42	65	65	65
DIB14	posedge CLKB	42	42	42	65	65	65
DIB15	posedge CLKB	42	42	42	65	65	65
DIB16	posedge CLKB	42	42	42	65	65	65
DIB17	posedge CLKB	42	42	42	65	65	65
DIB2	posedge CLKB	42	42	42	65	65	65
DIB3	posedge CLKB	42	42	42	65	65	65
DIB4	posedge CLKB	42	42	42	65	65	65
DIB5	posedge CLKB	42	42	42	65	65	65
DIB6	posedge CLKB	42	42	42	65	65	65
DIB7	posedge CLKB	42	42	42	65	65	65
DIB8	posedge CLKB	42	42	42	65	65	65
DIB9	posedge CLKB	42	42	42	65	65	65
OCEA	posedge CLKA	62	62	62	0	0	0
OCEB	posedge CLKB	65	65	65	0	0	0
RSTA	posedge CLKA	147	147	147	0	0	0
RSTB	posedge CLKB	149	149	149	0	0	0
WEA	posedge CLKA	42	42	42	29	29	29
WEB	posedge CLKB	0	0	0	107	107	107

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	613	613	613	816	816	816
negedge CLKB	613	613	613	816	816	816
posedge CLKA	613	613	613	816	816	816
posedge CLKB	613	613	613	816	816	816

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	1356	1360	1364	1356	1360	1364
CLKA	DOA1	1356	1360	1364	1356	1360	1364
CLKA	DOA10	1356	1360	1364	1356	1360	1364
CLKA	DOA11	1356	1360	1364	1356	1360	1364
CLKA	DOA12	1356	1360	1364	1356	1360	1364
CLKA	DOA13	1356	1360	1364	1356	1360	1364
CLKA	DOA14	1356	1360	1364	1356	1360	1364
CLKA	DOA15	1356	1360	1364	1356	1360	1364
CLKA	DOA16	1356	1360	1364	1356	1360	1364
CLKA	DOA17	1356	1360	1364	1356	1360	1364
CLKA	DOA2	1356	1360	1364	1356	1360	1364
CLKA	DOA3	1356	1360	1364	1356	1360	1364
CLKA	DOA4	1356	1360	1364	1356	1360	1364
CLKA	DOA5	1356	1360	1364	1356	1360	1364
CLKA	DOA6	1356	1360	1364	1356	1360	1364
CLKA	DOA7	1356	1360	1364	1356	1360	1364
CLKA	DOA8	1356	1360	1364	1356	1360	1364
CLKA	DOA9	1356	1360	1364	1356	1360	1364
CLKB	DOB0	226	232	239	226	232	239
CLKB	DOB1	226	232	239	226	232	239
CLKB	DOB10	226	232	239	226	232	239
CLKB	DOB11	226	232	239	226	232	239
CLKB	DOB12	226	232	239	226	232	239
CLKB	DOB13	226	232	239	226	232	239
CLKB	DOB14	226	232	239	226	232	239
CLKB	DOB15	226	232	239	226	232	239
CLKB	DOB16	226	232	239	226	232	239
CLKB	DOB17	226	232	239	226	232	239
CLKB	DOB2	226	232	239	226	232	239
CLKB	DOB3	226	232	239	226	232	239
CLKB	DOB4	226	232	239	226	232	239
CLKB	DOB5	226	232	239	226	232	239
CLKB	DOB6	226	232	239	226	232	239
CLKB	DOB7	226	232	239	226	232	239
CLKB	DOB8	226	232	239	226	232	239
CLKB	DOB9	226	232	239	226	232	239

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	67	67	67	1	1	1
ADA1	posedge CLKA	67	67	67	1	1	1
ADA10	posedge CLKA	67	67	67	1	1	1
ADA11	posedge CLKA	67	67	67	1	1	1
ADA12	posedge CLKA	67	67	67	1	1	1
ADA13	posedge CLKA	67	67	67	1	1	1
ADA2	posedge CLKA	67	67	67	1	1	1
ADA3	posedge CLKA	67	67	67	1	1	1
ADA4	posedge CLKA	67	67	67	1	1	1
ADA5	posedge CLKA	67	67	67	1	1	1
ADA6	posedge CLKA	67	67	67	1	1	1
ADA7	posedge CLKA	67	67	67	1	1	1
ADA8	posedge CLKA	67	67	67	1	1	1
ADA9	posedge CLKA	67	67	67	1	1	1
ADB0	posedge CLKB	57	57	57	28	28	28
ADB1	posedge CLKB	57	57	57	28	28	28
ADB10	posedge CLKB	57	57	57	28	28	28
ADB11	posedge CLKB	57	57	57	28	28	28
ADB12	posedge CLKB	57	57	57	28	28	28
ADB13	posedge CLKB	57	57	57	28	28	28
ADB2	posedge CLKB	57	57	57	28	28	28
ADB3	posedge CLKB	57	57	57	28	28	28
ADB4	posedge CLKB	57	57	57	28	28	28
ADB5	posedge CLKB	57	57	57	28	28	28
ADB6	posedge CLKB	57	57	57	28	28	28
ADB7	posedge CLKB	57	57	57	28	28	28
ADB8	posedge CLKB	57	57	57	28	28	28
ADB9	posedge CLKB	57	57	57	28	28	28
CEA	posedge CLKA	52	52	52	24	24	24
CEB	posedge CLKB	85	85	85	23	23	23
CSA0	posedge CLKA	8	8	8	51	51	51
CSA1	posedge CLKA	8	8	8	51	51	51
CSA2	posedge CLKA	8	8	8	51	51	51
CSB0	posedge CLKB	0	0	0	98	98	98
CSB1	posedge CLKB	0	0	0	98	98	98
CSB2	posedge CLKB	0	0	0	98	98	98
DIA0	posedge CLKA	59	59	59	9	9	9
DIA1	posedge CLKA	59	59	59	9	9	9
DIA10	posedge CLKA	59	59	59	9	9	9
DIA11	posedge CLKA	59	59	59	9	9	9
DIA12	posedge CLKA	59	59	59	9	9	9
DIA13	posedge CLKA	59	59	59	9	9	9
DIA14	posedge CLKA	59	59	59	9	9	9
DIA15	posedge CLKA	59	59	59	9	9	9
DIA16	posedge CLKA	59	59	59	9	9	9
DIA17	posedge CLKA	59	59	59	9	9	9
DIA2	posedge CLKA	59	59	59	9	9	9
DIA3	posedge CLKA	59	59	59	9	9	9
DIA4	posedge CLKA	59	59	59	9	9	9
DIA5	posedge CLKA	59	59	59	9	9	9
DIA6	posedge CLKA	59	59	59	9	9	9
DIA7	posedge CLKA	59	59	59	9	9	9
DIA8	posedge CLKA	59	59	59	9	9	9
DIA9	posedge CLKA	59	59	59	9	9	9
DIB0	posedge CLKB	42	42	42	65	65	65
DIB1	posedge CLKB	42	42	42	65	65	65
DIB10	posedge CLKB	42	42	42	65	65	65
DIB11	posedge CLKB	42	42	42	65	65	65
DIB12	posedge CLKB	42	42	42	65	65	65
DIB13	posedge CLKB	42	42	42	65	65	65
DIB14	posedge CLKB	42	42	42	65	65	65
DIB15	posedge CLKB	42	42	42	65	65	65
DIB16	posedge CLKB	42	42	42	65	65	65
DIB17	posedge CLKB	42	42	42	65	65	65
DIB2	posedge CLKB	42	42	42	65	65	65
DIB3	posedge CLKB	42	42	42	65	65	65
DIB4	posedge CLKB	42	42	42	65	65	65
DIB5	posedge CLKB	42	42	42	65	65	65
DIB6	posedge CLKB	42	42	42	65	65	65
DIB7	posedge CLKB	42	42	42	65	65	65
DIB8	posedge CLKB	42	42	42	65	65	65
DIB9	posedge CLKB	42	42	42	65	65	65
OCEA	posedge CLKA	62	62	62	0	0	0
OCEB	posedge CLKB	65	65	65	0	0	0
RSTA	posedge CLKA	147	147	147	0	0	0
RSTB	posedge CLKB	149	149	149	0	0	0
WEA	posedge CLKA	42	42	42	29	29	29
WEB	posedge CLKB	0	0	0	107	107	107

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	613	613	613	816	816	816
negedge CLKB	613	613	613	816	816	816
posedge CLKA	613	613	613	816	816	816
posedge CLKB	613	613	613	816	816	816

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	232	238	245	232	238	245
CLKA	DOA1	232	238	245	232	238	245
CLKA	DOA10	232	238	245	232	238	245
CLKA	DOA11	232	238	245	232	238	245
CLKA	DOA12	232	238	245	232	238	245
CLKA	DOA13	232	238	245	232	238	245
CLKA	DOA14	232	238	245	232	238	245
CLKA	DOA15	232	238	245	232	238	245
CLKA	DOA16	232	238	245	232	238	245
CLKA	DOA17	232	238	245	232	238	245
CLKA	DOA2	232	238	245	232	238	245
CLKA	DOA3	232	238	245	232	238	245
CLKA	DOA4	232	238	245	232	238	245
CLKA	DOA5	232	238	245	232	238	245
CLKA	DOA6	232	238	245	232	238	245
CLKA	DOA7	232	238	245	232	238	245
CLKA	DOA8	232	238	245	232	238	245
CLKA	DOA9	232	238	245	232	238	245
CLKB	DOB0	1413	1416	1419	1413	1416	1419
CLKB	DOB1	1413	1416	1419	1413	1416	1419
CLKB	DOB10	1413	1416	1419	1413	1416	1419
CLKB	DOB11	1413	1416	1419	1413	1416	1419
CLKB	DOB12	1413	1416	1419	1413	1416	1419
CLKB	DOB13	1413	1416	1419	1413	1416	1419
CLKB	DOB14	1413	1416	1419	1413	1416	1419
CLKB	DOB15	1413	1416	1419	1413	1416	1419
CLKB	DOB16	1413	1416	1419	1413	1416	1419
CLKB	DOB17	1413	1416	1419	1413	1416	1419
CLKB	DOB2	1413	1416	1419	1413	1416	1419
CLKB	DOB3	1413	1416	1419	1413	1416	1419
CLKB	DOB4	1413	1416	1419	1413	1416	1419
CLKB	DOB5	1413	1416	1419	1413	1416	1419
CLKB	DOB6	1413	1416	1419	1413	1416	1419
CLKB	DOB7	1413	1416	1419	1413	1416	1419
CLKB	DOB8	1413	1416	1419	1413	1416	1419
CLKB	DOB9	1413	1416	1419	1413	1416	1419

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	67	67	67	1	1	1
ADA1	posedge CLKA	67	67	67	1	1	1
ADA10	posedge CLKA	67	67	67	1	1	1
ADA11	posedge CLKA	67	67	67	1	1	1
ADA12	posedge CLKA	67	67	67	1	1	1
ADA13	posedge CLKA	67	67	67	1	1	1
ADA2	posedge CLKA	67	67	67	1	1	1
ADA3	posedge CLKA	67	67	67	1	1	1
ADA4	posedge CLKA	67	67	67	1	1	1
ADA5	posedge CLKA	67	67	67	1	1	1
ADA6	posedge CLKA	67	67	67	1	1	1
ADA7	posedge CLKA	67	67	67	1	1	1
ADA8	posedge CLKA	67	67	67	1	1	1
ADA9	posedge CLKA	67	67	67	1	1	1
ADB0	posedge CLKB	57	57	57	28	28	28
ADB1	posedge CLKB	57	57	57	28	28	28
ADB10	posedge CLKB	57	57	57	28	28	28
ADB11	posedge CLKB	57	57	57	28	28	28
ADB12	posedge CLKB	57	57	57	28	28	28
ADB13	posedge CLKB	57	57	57	28	28	28
ADB2	posedge CLKB	57	57	57	28	28	28
ADB3	posedge CLKB	57	57	57	28	28	28
ADB4	posedge CLKB	57	57	57	28	28	28
ADB5	posedge CLKB	57	57	57	28	28	28
ADB6	posedge CLKB	57	57	57	28	28	28
ADB7	posedge CLKB	57	57	57	28	28	28
ADB8	posedge CLKB	57	57	57	28	28	28
ADB9	posedge CLKB	57	57	57	28	28	28
CEA	posedge CLKA	52	52	52	24	24	24
CEB	posedge CLKB	85	85	85	23	23	23
CSA0	posedge CLKA	8	8	8	51	51	51
CSA1	posedge CLKA	8	8	8	51	51	51
CSA2	posedge CLKA	8	8	8	51	51	51
CSB0	posedge CLKB	0	0	0	98	98	98
CSB1	posedge CLKB	0	0	0	98	98	98
CSB2	posedge CLKB	0	0	0	98	98	98
DIA0	posedge CLKA	59	59	59	9	9	9
DIA1	posedge CLKA	59	59	59	9	9	9
DIA10	posedge CLKA	59	59	59	9	9	9
DIA11	posedge CLKA	59	59	59	9	9	9
DIA12	posedge CLKA	59	59	59	9	9	9
DIA13	posedge CLKA	59	59	59	9	9	9
DIA14	posedge CLKA	59	59	59	9	9	9
DIA15	posedge CLKA	59	59	59	9	9	9
DIA16	posedge CLKA	59	59	59	9	9	9
DIA17	posedge CLKA	59	59	59	9	9	9
DIA2	posedge CLKA	59	59	59	9	9	9
DIA3	posedge CLKA	59	59	59	9	9	9
DIA4	posedge CLKA	59	59	59	9	9	9
DIA5	posedge CLKA	59	59	59	9	9	9
DIA6	posedge CLKA	59	59	59	9	9	9
DIA7	posedge CLKA	59	59	59	9	9	9
DIA8	posedge CLKA	59	59	59	9	9	9
DIA9	posedge CLKA	59	59	59	9	9	9
DIB0	posedge CLKB	42	42	42	65	65	65
DIB1	posedge CLKB	42	42	42	65	65	65
DIB10	posedge CLKB	42	42	42	65	65	65
DIB11	posedge CLKB	42	42	42	65	65	65
DIB12	posedge CLKB	42	42	42	65	65	65
DIB13	posedge CLKB	42	42	42	65	65	65
DIB14	posedge CLKB	42	42	42	65	65	65
DIB15	posedge CLKB	42	42	42	65	65	65
DIB16	posedge CLKB	42	42	42	65	65	65
DIB17	posedge CLKB	42	42	42	65	65	65
DIB2	posedge CLKB	42	42	42	65	65	65
DIB3	posedge CLKB	42	42	42	65	65	65
DIB4	posedge CLKB	42	42	42	65	65	65
DIB5	posedge CLKB	42	42	42	65	65	65
DIB6	posedge CLKB	42	42	42	65	65	65
DIB7	posedge CLKB	42	42	42	65	65	65
DIB8	posedge CLKB	42	42	42	65	65	65
DIB9	posedge CLKB	42	42	42	65	65	65
OCEA	posedge CLKA	62	62	62	0	0	0
OCEB	posedge CLKB	65	65	65	0	0	0
RSTA	posedge CLKA	147	147	147	0	0	0
RSTB	posedge CLKB	149	149	149	0	0	0
WEA	posedge CLKA	42	42	42	29	29	29
WEB	posedge CLKB	0	0	0	107	107	107

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	613	613	613	816	816	816
negedge CLKB	613	613	613	816	816	816
posedge CLKA	613	613	613	816	816	816
posedge CLKB	613	613	613	816	816	816

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	232	238	245	232	238	245
CLKA	DOA1	232	238	245	232	238	245
CLKA	DOA10	232	238	245	232	238	245
CLKA	DOA11	232	238	245	232	238	245
CLKA	DOA12	232	238	245	232	238	245
CLKA	DOA13	232	238	245	232	238	245
CLKA	DOA14	232	238	245	232	238	245
CLKA	DOA15	232	238	245	232	238	245
CLKA	DOA16	232	238	245	232	238	245
CLKA	DOA17	232	238	245	232	238	245
CLKA	DOA2	232	238	245	232	238	245
CLKA	DOA3	232	238	245	232	238	245
CLKA	DOA4	232	238	245	232	238	245
CLKA	DOA5	232	238	245	232	238	245
CLKA	DOA6	232	238	245	232	238	245
CLKA	DOA7	232	238	245	232	238	245
CLKA	DOA8	232	238	245	232	238	245
CLKA	DOA9	232	238	245	232	238	245
CLKB	DOB0	226	232	239	226	232	239
CLKB	DOB1	226	232	239	226	232	239
CLKB	DOB10	226	232	239	226	232	239
CLKB	DOB11	226	232	239	226	232	239
CLKB	DOB12	226	232	239	226	232	239
CLKB	DOB13	226	232	239	226	232	239
CLKB	DOB14	226	232	239	226	232	239
CLKB	DOB15	226	232	239	226	232	239
CLKB	DOB16	226	232	239	226	232	239
CLKB	DOB17	226	232	239	226	232	239
CLKB	DOB2	226	232	239	226	232	239
CLKB	DOB3	226	232	239	226	232	239
CLKB	DOB4	226	232	239	226	232	239
CLKB	DOB5	226	232	239	226	232	239
CLKB	DOB6	226	232	239	226	232	239
CLKB	DOB7	226	232	239	226	232	239
CLKB	DOB8	226	232	239	226	232	239
CLKB	DOB9	226	232	239	226	232	239

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	67	67	67	1	1	1
ADA1	posedge CLKA	67	67	67	1	1	1
ADA10	posedge CLKA	67	67	67	1	1	1
ADA11	posedge CLKA	67	67	67	1	1	1
ADA12	posedge CLKA	67	67	67	1	1	1
ADA13	posedge CLKA	67	67	67	1	1	1
ADA2	posedge CLKA	67	67	67	1	1	1
ADA3	posedge CLKA	67	67	67	1	1	1
ADA4	posedge CLKA	67	67	67	1	1	1
ADA5	posedge CLKA	67	67	67	1	1	1
ADA6	posedge CLKA	67	67	67	1	1	1
ADA7	posedge CLKA	67	67	67	1	1	1
ADA8	posedge CLKA	67	67	67	1	1	1
ADA9	posedge CLKA	67	67	67	1	1	1
ADB0	posedge CLKB	57	57	57	28	28	28
ADB1	posedge CLKB	57	57	57	28	28	28
ADB10	posedge CLKB	57	57	57	28	28	28
ADB11	posedge CLKB	57	57	57	28	28	28
ADB12	posedge CLKB	57	57	57	28	28	28
ADB13	posedge CLKB	57	57	57	28	28	28
ADB2	posedge CLKB	57	57	57	28	28	28
ADB3	posedge CLKB	57	57	57	28	28	28
ADB4	posedge CLKB	57	57	57	28	28	28
ADB5	posedge CLKB	57	57	57	28	28	28
ADB6	posedge CLKB	57	57	57	28	28	28
ADB7	posedge CLKB	57	57	57	28	28	28
ADB8	posedge CLKB	57	57	57	28	28	28
ADB9	posedge CLKB	57	57	57	28	28	28
CEA	posedge CLKA	52	52	52	24	24	24
CEB	posedge CLKB	85	85	85	23	23	23
CSA0	posedge CLKA	8	8	8	51	51	51
CSA1	posedge CLKA	8	8	8	51	51	51
CSA2	posedge CLKA	8	8	8	51	51	51
CSB0	posedge CLKB	0	0	0	98	98	98
CSB1	posedge CLKB	0	0	0	98	98	98
CSB2	posedge CLKB	0	0	0	98	98	98
DIA0	posedge CLKA	59	59	59	9	9	9
DIA1	posedge CLKA	59	59	59	9	9	9
DIA10	posedge CLKA	59	59	59	9	9	9
DIA11	posedge CLKA	59	59	59	9	9	9
DIA12	posedge CLKA	59	59	59	9	9	9
DIA13	posedge CLKA	59	59	59	9	9	9
DIA14	posedge CLKA	59	59	59	9	9	9
DIA15	posedge CLKA	59	59	59	9	9	9
DIA16	posedge CLKA	59	59	59	9	9	9
DIA17	posedge CLKA	59	59	59	9	9	9
DIA2	posedge CLKA	59	59	59	9	9	9
DIA3	posedge CLKA	59	59	59	9	9	9
DIA4	posedge CLKA	59	59	59	9	9	9
DIA5	posedge CLKA	59	59	59	9	9	9
DIA6	posedge CLKA	59	59	59	9	9	9
DIA7	posedge CLKA	59	59	59	9	9	9
DIA8	posedge CLKA	59	59	59	9	9	9
DIA9	posedge CLKA	59	59	59	9	9	9
DIB0	posedge CLKB	42	42	42	65	65	65
DIB1	posedge CLKB	42	42	42	65	65	65
DIB10	posedge CLKB	42	42	42	65	65	65
DIB11	posedge CLKB	42	42	42	65	65	65
DIB12	posedge CLKB	42	42	42	65	65	65
DIB13	posedge CLKB	42	42	42	65	65	65
DIB14	posedge CLKB	42	42	42	65	65	65
DIB15	posedge CLKB	42	42	42	65	65	65
DIB16	posedge CLKB	42	42	42	65	65	65
DIB17	posedge CLKB	42	42	42	65	65	65
DIB2	posedge CLKB	42	42	42	65	65	65
DIB3	posedge CLKB	42	42	42	65	65	65
DIB4	posedge CLKB	42	42	42	65	65	65
DIB5	posedge CLKB	42	42	42	65	65	65
DIB6	posedge CLKB	42	42	42	65	65	65
DIB7	posedge CLKB	42	42	42	65	65	65
DIB8	posedge CLKB	42	42	42	65	65	65
DIB9	posedge CLKB	42	42	42	65	65	65
OCEA	posedge CLKA	62	62	62	0	0	0
OCEB	posedge CLKB	65	65	65	0	0	0
RSTA	posedge CLKA	147	147	147	0	0	0
RSTB	posedge CLKB	149	149	149	0	0	0
WEA	posedge CLKA	42	42	42	29	29	29
WEB	posedge CLKB	0	0	0	107	107	107

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	613	613	613	816	816	816
negedge CLKB	613	613	613	816	816	816
posedge CLKA	613	613	613	816	816	816
posedge CLKB	613	613	613	816	816	816

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	1356	1360	1364	1356	1360	1364
CLKA	DOA1	1356	1360	1364	1356	1360	1364
CLKA	DOA10	1356	1360	1364	1356	1360	1364
CLKA	DOA11	1356	1360	1364	1356	1360	1364
CLKA	DOA12	1356	1360	1364	1356	1360	1364
CLKA	DOA13	1356	1360	1364	1356	1360	1364
CLKA	DOA14	1356	1360	1364	1356	1360	1364
CLKA	DOA15	1356	1360	1364	1356	1360	1364
CLKA	DOA16	1356	1360	1364	1356	1360	1364
CLKA	DOA17	1356	1360	1364	1356	1360	1364
CLKA	DOA2	1356	1360	1364	1356	1360	1364
CLKA	DOA3	1356	1360	1364	1356	1360	1364
CLKA	DOA4	1356	1360	1364	1356	1360	1364
CLKA	DOA5	1356	1360	1364	1356	1360	1364
CLKA	DOA6	1356	1360	1364	1356	1360	1364
CLKA	DOA7	1356	1360	1364	1356	1360	1364
CLKA	DOA8	1356	1360	1364	1356	1360	1364
CLKA	DOA9	1356	1360	1364	1356	1360	1364
CLKB	DOB0	1413	1416	1419	1413	1416	1419
CLKB	DOB1	1413	1416	1419	1413	1416	1419
CLKB	DOB10	1413	1416	1419	1413	1416	1419
CLKB	DOB11	1413	1416	1419	1413	1416	1419
CLKB	DOB12	1413	1416	1419	1413	1416	1419
CLKB	DOB13	1413	1416	1419	1413	1416	1419
CLKB	DOB14	1413	1416	1419	1413	1416	1419
CLKB	DOB15	1413	1416	1419	1413	1416	1419
CLKB	DOB16	1413	1416	1419	1413	1416	1419
CLKB	DOB17	1413	1416	1419	1413	1416	1419
CLKB	DOB2	1413	1416	1419	1413	1416	1419
CLKB	DOB3	1413	1416	1419	1413	1416	1419
CLKB	DOB4	1413	1416	1419	1413	1416	1419
CLKB	DOB5	1413	1416	1419	1413	1416	1419
CLKB	DOB6	1413	1416	1419	1413	1416	1419
CLKB	DOB7	1413	1416	1419	1413	1416	1419
CLKB	DOB8	1413	1416	1419	1413	1416	1419
CLKB	DOB9	1413	1416	1419	1413	1416	1419

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	67	67	67	1	1	1
ADA1	posedge CLKA	67	67	67	1	1	1
ADA10	posedge CLKA	67	67	67	1	1	1
ADA11	posedge CLKA	67	67	67	1	1	1
ADA12	posedge CLKA	67	67	67	1	1	1
ADA13	posedge CLKA	67	67	67	1	1	1
ADA2	posedge CLKA	67	67	67	1	1	1
ADA3	posedge CLKA	67	67	67	1	1	1
ADA4	posedge CLKA	67	67	67	1	1	1
ADA5	posedge CLKA	67	67	67	1	1	1
ADA6	posedge CLKA	67	67	67	1	1	1
ADA7	posedge CLKA	67	67	67	1	1	1
ADA8	posedge CLKA	67	67	67	1	1	1
ADA9	posedge CLKA	67	67	67	1	1	1
ADB0	posedge CLKB	57	57	57	28	28	28
ADB1	posedge CLKB	57	57	57	28	28	28
ADB10	posedge CLKB	57	57	57	28	28	28
ADB11	posedge CLKB	57	57	57	28	28	28
ADB12	posedge CLKB	57	57	57	28	28	28
ADB13	posedge CLKB	57	57	57	28	28	28
ADB2	posedge CLKB	57	57	57	28	28	28
ADB3	posedge CLKB	57	57	57	28	28	28
ADB4	posedge CLKB	57	57	57	28	28	28
ADB5	posedge CLKB	57	57	57	28	28	28
ADB6	posedge CLKB	57	57	57	28	28	28
ADB7	posedge CLKB	57	57	57	28	28	28
ADB8	posedge CLKB	57	57	57	28	28	28
ADB9	posedge CLKB	57	57	57	28	28	28
CEA	posedge CLKA	52	52	52	24	24	24
CEB	posedge CLKB	85	85	85	23	23	23
CSA0	posedge CLKA	8	8	8	51	51	51
CSA1	posedge CLKA	8	8	8	51	51	51
CSA2	posedge CLKA	8	8	8	51	51	51
CSB0	posedge CLKB	0	0	0	98	98	98
CSB1	posedge CLKB	0	0	0	98	98	98
CSB2	posedge CLKB	0	0	0	98	98	98
DIA0	posedge CLKA	59	59	59	9	9	9
DIA1	posedge CLKA	59	59	59	9	9	9
DIA10	posedge CLKA	59	59	59	9	9	9
DIA11	posedge CLKA	59	59	59	9	9	9
DIA12	posedge CLKA	59	59	59	9	9	9
DIA13	posedge CLKA	59	59	59	9	9	9
DIA14	posedge CLKA	59	59	59	9	9	9
DIA15	posedge CLKA	59	59	59	9	9	9
DIA16	posedge CLKA	59	59	59	9	9	9
DIA17	posedge CLKA	59	59	59	9	9	9
DIA2	posedge CLKA	59	59	59	9	9	9
DIA3	posedge CLKA	59	59	59	9	9	9
DIA4	posedge CLKA	59	59	59	9	9	9
DIA5	posedge CLKA	59	59	59	9	9	9
DIA6	posedge CLKA	59	59	59	9	9	9
DIA7	posedge CLKA	59	59	59	9	9	9
DIA8	posedge CLKA	59	59	59	9	9	9
DIA9	posedge CLKA	59	59	59	9	9	9
DIB0	posedge CLKB	42	42	42	65	65	65
DIB1	posedge CLKB	42	42	42	65	65	65
DIB10	posedge CLKB	42	42	42	65	65	65
DIB11	posedge CLKB	42	42	42	65	65	65
DIB12	posedge CLKB	42	42	42	65	65	65
DIB13	posedge CLKB	42	42	42	65	65	65
DIB14	posedge CLKB	42	42	42	65	65	65
DIB15	posedge CLKB	42	42	42	65	65	65
DIB16	posedge CLKB	42	42	42	65	65	65
DIB17	posedge CLKB	42	42	42	65	65	65
DIB2	posedge CLKB	42	42	42	65	65	65
DIB3	posedge CLKB	42	42	42	65	65	65
DIB4	posedge CLKB	42	42	42	65	65	65
DIB5	posedge CLKB	42	42	42	65	65	65
DIB6	posedge CLKB	42	42	42	65	65	65
DIB7	posedge CLKB	42	42	42	65	65	65
DIB8	posedge CLKB	42	42	42	65	65	65
DIB9	posedge CLKB	42	42	42	65	65	65
OCEA	posedge CLKA	62	62	62	0	0	0
OCEB	posedge CLKB	65	65	65	0	0	0
RSTA	posedge CLKA	147	147	147	0	0	0
RSTB	posedge CLKB	149	149	149	0	0	0
WEA	posedge CLKA	42	42	42	29	29	29
WEB	posedge CLKB	0	0	0	107	107	107

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	613	613	613	816	816	816
negedge CLKB	613	613	613	816	816	816
posedge CLKA	613	613	613	816	816	816
posedge CLKB	613	613	613	816	816	816

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	1356	1360	1364	1356	1360	1364
CLKA	DOA1	1356	1360	1364	1356	1360	1364
CLKA	DOA10	1356	1360	1364	1356	1360	1364
CLKA	DOA11	1356	1360	1364	1356	1360	1364
CLKA	DOA12	1356	1360	1364	1356	1360	1364
CLKA	DOA13	1356	1360	1364	1356	1360	1364
CLKA	DOA14	1356	1360	1364	1356	1360	1364
CLKA	DOA15	1356	1360	1364	1356	1360	1364
CLKA	DOA16	1356	1360	1364	1356	1360	1364
CLKA	DOA17	1356	1360	1364	1356	1360	1364
CLKA	DOA2	1356	1360	1364	1356	1360	1364
CLKA	DOA3	1356	1360	1364	1356	1360	1364
CLKA	DOA4	1356	1360	1364	1356	1360	1364
CLKA	DOA5	1356	1360	1364	1356	1360	1364
CLKA	DOA6	1356	1360	1364	1356	1360	1364
CLKA	DOA7	1356	1360	1364	1356	1360	1364
CLKA	DOA8	1356	1360	1364	1356	1360	1364
CLKA	DOA9	1356	1360	1364	1356	1360	1364
CLKB	DOB0	1414	1417	1420	1414	1417	1420
CLKB	DOB1	1414	1417	1420	1414	1417	1420
CLKB	DOB10	1414	1417	1420	1414	1417	1420
CLKB	DOB11	1414	1417	1420	1414	1417	1420
CLKB	DOB12	1414	1417	1420	1414	1417	1420
CLKB	DOB13	1414	1417	1420	1414	1417	1420
CLKB	DOB14	1414	1417	1420	1414	1417	1420
CLKB	DOB15	1414	1417	1420	1414	1417	1420
CLKB	DOB16	1414	1417	1420	1414	1417	1420
CLKB	DOB17	1414	1417	1420	1414	1417	1420
CLKB	DOB2	1414	1417	1420	1414	1417	1420
CLKB	DOB3	1414	1417	1420	1414	1417	1420
CLKB	DOB4	1414	1417	1420	1414	1417	1420
CLKB	DOB5	1414	1417	1420	1414	1417	1420
CLKB	DOB6	1414	1417	1420	1414	1417	1420
CLKB	DOB7	1414	1417	1420	1414	1417	1420
CLKB	DOB8	1414	1417	1420	1414	1417	1420
CLKB	DOB9	1414	1417	1420	1414	1417	1420

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	67	67	67	1	1	1
ADA1	posedge CLKA	67	67	67	1	1	1
ADA10	posedge CLKA	67	67	67	1	1	1
ADA11	posedge CLKA	67	67	67	1	1	1
ADA12	posedge CLKA	67	67	67	1	1	1
ADA13	posedge CLKA	67	67	67	1	1	1
ADA2	posedge CLKA	67	67	67	1	1	1
ADA3	posedge CLKA	67	67	67	1	1	1
ADA4	posedge CLKA	67	67	67	1	1	1
ADA5	posedge CLKA	67	67	67	1	1	1
ADA6	posedge CLKA	67	67	67	1	1	1
ADA7	posedge CLKA	67	67	67	1	1	1
ADA8	posedge CLKA	67	67	67	1	1	1
ADA9	posedge CLKA	67	67	67	1	1	1
ADB0	posedge CLKB	57	57	57	28	28	28
ADB1	posedge CLKB	57	57	57	28	28	28
ADB10	posedge CLKB	57	57	57	28	28	28
ADB11	posedge CLKB	57	57	57	28	28	28
ADB12	posedge CLKB	57	57	57	28	28	28
ADB13	posedge CLKB	57	57	57	28	28	28
ADB2	posedge CLKB	57	57	57	28	28	28
ADB3	posedge CLKB	57	57	57	28	28	28
ADB4	posedge CLKB	57	57	57	28	28	28
ADB5	posedge CLKB	57	57	57	28	28	28
ADB6	posedge CLKB	57	57	57	28	28	28
ADB7	posedge CLKB	57	57	57	28	28	28
ADB8	posedge CLKB	57	57	57	28	28	28
ADB9	posedge CLKB	57	57	57	28	28	28
CEA	posedge CLKA	52	52	52	24	24	24
CEB	posedge CLKB	85	85	85	23	23	23
CSA0	posedge CLKA	8	8	8	51	51	51
CSA1	posedge CLKA	8	8	8	51	51	51
CSA2	posedge CLKA	8	8	8	51	51	51
CSB0	posedge CLKB	0	0	0	98	98	98
CSB1	posedge CLKB	0	0	0	98	98	98
CSB2	posedge CLKB	0	0	0	98	98	98
DIA0	posedge CLKA	59	59	59	9	9	9
DIA1	posedge CLKA	59	59	59	9	9	9
DIA10	posedge CLKA	59	59	59	9	9	9
DIA11	posedge CLKA	59	59	59	9	9	9
DIA12	posedge CLKA	59	59	59	9	9	9
DIA13	posedge CLKA	59	59	59	9	9	9
DIA14	posedge CLKA	59	59	59	9	9	9
DIA15	posedge CLKA	59	59	59	9	9	9
DIA16	posedge CLKA	59	59	59	9	9	9
DIA17	posedge CLKA	59	59	59	9	9	9
DIA2	posedge CLKA	59	59	59	9	9	9
DIA3	posedge CLKA	59	59	59	9	9	9
DIA4	posedge CLKA	59	59	59	9	9	9
DIA5	posedge CLKA	59	59	59	9	9	9
DIA6	posedge CLKA	59	59	59	9	9	9
DIA7	posedge CLKA	59	59	59	9	9	9
DIA8	posedge CLKA	59	59	59	9	9	9
DIA9	posedge CLKA	59	59	59	9	9	9
DIB0	posedge CLKB	42	42	42	65	65	65
DIB1	posedge CLKB	42	42	42	65	65	65
DIB10	posedge CLKB	42	42	42	65	65	65
DIB11	posedge CLKB	42	42	42	65	65	65
DIB12	posedge CLKB	42	42	42	65	65	65
DIB13	posedge CLKB	42	42	42	65	65	65
DIB14	posedge CLKB	42	42	42	65	65	65
DIB15	posedge CLKB	42	42	42	65	65	65
DIB16	posedge CLKB	42	42	42	65	65	65
DIB17	posedge CLKB	42	42	42	65	65	65
DIB2	posedge CLKB	42	42	42	65	65	65
DIB3	posedge CLKB	42	42	42	65	65	65
DIB4	posedge CLKB	42	42	42	65	65	65
DIB5	posedge CLKB	42	42	42	65	65	65
DIB6	posedge CLKB	42	42	42	65	65	65
DIB7	posedge CLKB	42	42	42	65	65	65
DIB8	posedge CLKB	42	42	42	65	65	65
DIB9	posedge CLKB	42	42	42	65	65	65
OCEA	posedge CLKA	62	62	62	0	0	0
OCEB	posedge CLKB	65	65	65	0	0	0
RSTA	posedge CLKA	147	147	147	0	0	0
RSTB	posedge CLKB	149	149	149	0	0	0
WEA	posedge CLKA	42	42	42	29	29	29
WEB	posedge CLKB	0	0	0	107	107	107

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	613	613	613	816	816	816
negedge CLKB	777	777	777	644	644	644
posedge CLKA	613	613	613	816	816	816
posedge CLKB	777	777	777	644	644	644

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	1356	1360	1364	1356	1360	1364
CLKA	DOA1	1356	1360	1364	1356	1360	1364
CLKA	DOA10	1356	1360	1364	1356	1360	1364
CLKA	DOA11	1356	1360	1364	1356	1360	1364
CLKA	DOA12	1356	1360	1364	1356	1360	1364
CLKA	DOA13	1356	1360	1364	1356	1360	1364
CLKA	DOA14	1356	1360	1364	1356	1360	1364
CLKA	DOA15	1356	1360	1364	1356	1360	1364
CLKA	DOA16	1356	1360	1364	1356	1360	1364
CLKA	DOA17	1356	1360	1364	1356	1360	1364
CLKA	DOA2	1356	1360	1364	1356	1360	1364
CLKA	DOA3	1356	1360	1364	1356	1360	1364
CLKA	DOA4	1356	1360	1364	1356	1360	1364
CLKA	DOA5	1356	1360	1364	1356	1360	1364
CLKA	DOA6	1356	1360	1364	1356	1360	1364
CLKA	DOA7	1356	1360	1364	1356	1360	1364
CLKA	DOA8	1356	1360	1364	1356	1360	1364
CLKA	DOA9	1356	1360	1364	1356	1360	1364
CLKB	DOB0	1414	1417	1420	1414	1417	1420
CLKB	DOB1	1414	1417	1420	1414	1417	1420
CLKB	DOB10	1414	1417	1420	1414	1417	1420
CLKB	DOB11	1414	1417	1420	1414	1417	1420
CLKB	DOB12	1414	1417	1420	1414	1417	1420
CLKB	DOB13	1414	1417	1420	1414	1417	1420
CLKB	DOB14	1414	1417	1420	1414	1417	1420
CLKB	DOB15	1414	1417	1420	1414	1417	1420
CLKB	DOB16	1414	1417	1420	1414	1417	1420
CLKB	DOB17	1414	1417	1420	1414	1417	1420
CLKB	DOB2	1414	1417	1420	1414	1417	1420
CLKB	DOB3	1414	1417	1420	1414	1417	1420
CLKB	DOB4	1414	1417	1420	1414	1417	1420
CLKB	DOB5	1414	1417	1420	1414	1417	1420
CLKB	DOB6	1414	1417	1420	1414	1417	1420
CLKB	DOB7	1414	1417	1420	1414	1417	1420
CLKB	DOB8	1414	1417	1420	1414	1417	1420
CLKB	DOB9	1414	1417	1420	1414	1417	1420

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	67	67	67	1	1	1
ADA1	posedge CLKA	67	67	67	1	1	1
ADA10	posedge CLKA	67	67	67	1	1	1
ADA11	posedge CLKA	67	67	67	1	1	1
ADA12	posedge CLKA	67	67	67	1	1	1
ADA13	posedge CLKA	67	67	67	1	1	1
ADA2	posedge CLKA	67	67	67	1	1	1
ADA3	posedge CLKA	67	67	67	1	1	1
ADA4	posedge CLKA	67	67	67	1	1	1
ADA5	posedge CLKA	67	67	67	1	1	1
ADA6	posedge CLKA	67	67	67	1	1	1
ADA7	posedge CLKA	67	67	67	1	1	1
ADA8	posedge CLKA	67	67	67	1	1	1
ADA9	posedge CLKA	67	67	67	1	1	1
ADB0	posedge CLKB	57	57	57	28	28	28
ADB1	posedge CLKB	57	57	57	28	28	28
ADB10	posedge CLKB	57	57	57	28	28	28
ADB11	posedge CLKB	57	57	57	28	28	28
ADB12	posedge CLKB	57	57	57	28	28	28
ADB13	posedge CLKB	57	57	57	28	28	28
ADB2	posedge CLKB	57	57	57	28	28	28
ADB3	posedge CLKB	57	57	57	28	28	28
ADB4	posedge CLKB	57	57	57	28	28	28
ADB5	posedge CLKB	57	57	57	28	28	28
ADB6	posedge CLKB	57	57	57	28	28	28
ADB7	posedge CLKB	57	57	57	28	28	28
ADB8	posedge CLKB	57	57	57	28	28	28
ADB9	posedge CLKB	57	57	57	28	28	28
CEA	posedge CLKA	52	52	52	24	24	24
CEB	posedge CLKB	85	85	85	23	23	23
CSA0	posedge CLKA	8	8	8	51	51	51
CSA1	posedge CLKA	8	8	8	51	51	51
CSA2	posedge CLKA	8	8	8	51	51	51
CSB0	posedge CLKB	0	0	0	98	98	98
CSB1	posedge CLKB	0	0	0	98	98	98
CSB2	posedge CLKB	0	0	0	98	98	98
DIA0	posedge CLKA	59	59	59	9	9	9
DIA1	posedge CLKA	59	59	59	9	9	9
DIA10	posedge CLKA	59	59	59	9	9	9
DIA11	posedge CLKA	59	59	59	9	9	9
DIA12	posedge CLKA	59	59	59	9	9	9
DIA13	posedge CLKA	59	59	59	9	9	9
DIA14	posedge CLKA	59	59	59	9	9	9
DIA15	posedge CLKA	59	59	59	9	9	9
DIA16	posedge CLKA	59	59	59	9	9	9
DIA17	posedge CLKA	59	59	59	9	9	9
DIA2	posedge CLKA	59	59	59	9	9	9
DIA3	posedge CLKA	59	59	59	9	9	9
DIA4	posedge CLKA	59	59	59	9	9	9
DIA5	posedge CLKA	59	59	59	9	9	9
DIA6	posedge CLKA	59	59	59	9	9	9
DIA7	posedge CLKA	59	59	59	9	9	9
DIA8	posedge CLKA	59	59	59	9	9	9
DIA9	posedge CLKA	59	59	59	9	9	9
DIB0	posedge CLKB	42	42	42	65	65	65
DIB1	posedge CLKB	42	42	42	65	65	65
DIB10	posedge CLKB	42	42	42	65	65	65
DIB11	posedge CLKB	42	42	42	65	65	65
DIB12	posedge CLKB	42	42	42	65	65	65
DIB13	posedge CLKB	42	42	42	65	65	65
DIB14	posedge CLKB	42	42	42	65	65	65
DIB15	posedge CLKB	42	42	42	65	65	65
DIB16	posedge CLKB	42	42	42	65	65	65
DIB17	posedge CLKB	42	42	42	65	65	65
DIB2	posedge CLKB	42	42	42	65	65	65
DIB3	posedge CLKB	42	42	42	65	65	65
DIB4	posedge CLKB	42	42	42	65	65	65
DIB5	posedge CLKB	42	42	42	65	65	65
DIB6	posedge CLKB	42	42	42	65	65	65
DIB7	posedge CLKB	42	42	42	65	65	65
DIB8	posedge CLKB	42	42	42	65	65	65
DIB9	posedge CLKB	42	42	42	65	65	65
OCEA	posedge CLKA	62	62	62	0	0	0
OCEB	posedge CLKB	65	65	65	0	0	0
RSTA	posedge CLKA	147	147	147	0	0	0
RSTB	posedge CLKB	149	149	149	0	0	0
WEA	posedge CLKA	42	42	42	29	29	29
WEB	posedge CLKB	0	0	0	107	107	107

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	613	613	613	816	816	816
negedge CLKB	609	609	609	821	821	821
posedge CLKA	613	613	613	816	816	816
posedge CLKB	609	609	609	821	821	821

IOLOGIC:MODE=IDDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	232	232	232	232	232	232
CLK	RXDATA1	232	232	232	232	232	232

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge CLK	254	254	254	164	164	164

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=IDDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	291	291	291	291	291	291
CLK	RXDATA1	291	291	291	291	291	291
CLK	RXDATA2	291	291	291	291	291	291
CLK	RXDATA3	291	291	291	291	291	291

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge ECLK	236	236	236	81	81	81
posedge ECLK	posedge CLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1250	1250	1250	400	400	400
posedge ECLK	1250	1250	1250	400	400	400

IOLOGIC:MODE=IREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	INFF	301	301	301	301	301	301

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	51	51	51
DI	posedge CLK	264	264	264	215	215	215
LSR	posedge CLK	66	66	66	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1351	1351	1351	370	370	370
posedge CLK	1351	1351	1351	370	370	370

IOLOGIC:MODE=ODDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	611	612	614	611	612	614

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=ODDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
ECLK	IOLDO	804	805	807	804	805	807

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
TXDATA0	posedge CLK	76	76	76	0	0	0
TXDATA1	posedge CLK	76	76	76	0	0	0
TXDATA2	posedge CLK	76	76	76	0	0	0
TXDATA3	posedge CLK	76	76	76	0	0	0
posedge CLK	posedge ECLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1250	1250	1250	400	400	400
posedge ECLK	1250	1250	1250	400	400	400

IOLOGIC:MODE=OREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	841	841	841	841	841	841

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	48	48	48
LSR	posedge CLK	76	76	76	0	0	0
TXDATA0	posedge CLK	93	93	93	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1351	1351	1351	370	370	370
posedge CLK	1351	1351	1351	370	370	370

IOLOGIC:MODE=TSREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLTO	631	631	631	631	631	631

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	48	48	48
LSR	posedge CLK	76	76	76	0	0	0
TSDATA0	posedge CLK	128	128	128	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1351	1351	1351	370	370	370
posedge CLK	1351	1351	1351	370	370	370

MULT18X18D:REGS=ALL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	399	438	478	399	438	478

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	17	25	34	0	4	26
B	posedge CLK0	17	25	34	0	4	26
CE0	posedge CLK0	121	147	173	0	0	17
RST0	posedge CLK0	69	82	96	34	43	52
SIGNEDA	posedge CLK0	0	0	0	104	112	121
SIGNEDB	posedge CLK0	0	0	0	104	112	121

MULT18X18D:REGS=INPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	1912	2216	2521	1912	2216	2521

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	17	25	34	0	4	26
B	posedge CLK0	17	25	34	0	4	26
CE0	posedge CLK0	121	147	173	0	0	17
RST0	posedge CLK0	69	82	96	34	43	52
SIGNEDA	posedge CLK0	0	0	0	104	112	121
SIGNEDB	posedge CLK0	0	0	0	104	112	121

MULT18X18D:REGS=NONE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A	P	1930	2234	2538	1930	2234	2538
B	P	1930	2234	2538	1930	2234	2538
SIGNEDA	P	1825	2120	2416	1825	2120	2416
SIGNEDB	P	1825	2120	2416	1825	2120	2416

MULT18X18D:REGS=OUTPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	399	438	478	399	438	478

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	1956	2068	2181	0	0	0
B	posedge CLK0	1956	2068	2181	0	0	0
CE0	posedge CLK0	121	147	173	0	0	17
RST0	posedge CLK0	69	82	96	34	43	52
SIGNEDA	posedge CLK0	1851	1955	2060	0	0	0
SIGNEDB	posedge CLK0	1851	1955	2060	0	0	0

MULT18X18D:REGS=PIPELINE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	895	908	921	895	908	921

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	1521	1582	1643	0	0	0
B	posedge CLK0	1521	1582	1643	0	0	0
CE0	posedge CLK0	121	147	173	0	0	17
RST0	posedge CLK0	69	82	96	34	43	52
SIGNEDA	posedge CLK0	1417	1469	1521	0	0	0
SIGNEDB	posedge CLK0	1417	1469	1521	0	0	0

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	594	610	626	594	610	626
PADDO	PAD	1347	1513	1679	1347	1513	1679
PADDT	PAD	1554	1800	2047	1554	1800	2047

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1464	1474	1484	1464	1474	1484
PADDO	PAD	1396	1553	1711	1396	1553	1711
PADDT	PAD	1553	1734	1915	1553	1734	1915

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1145	1191	1237	1145	1191	1237
PADDO	PAD	1441	1587	1734	1441	1587	1734
PADDT	PAD	1750	1888	2027	1750	1888	2027

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	826	851	876	826	851	876
PADDO	PAD	1736	1751	1766	1736	1751	1766
PADDT	PAD	1747	1843	1940	1747	1843	1940

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	921	945	970	921	945	970
PADDO	PAD	1819	2006	2193	1819	2006	2193
PADDT	PAD	2113	2327	2542	2113	2327	2542

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	437	437	437	437	437	437
PADDO	PAD	957	958	959	957	958	959

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	403	413	424	403	413	424
PADDO	PAD	1758	1862	1966	1758	1862	1966
PADDT	PAD	1821	2419	3017	1821	2419	3017

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	403	413	424	403	413	424
PADDO	PAD	1678	1752	1827	1678	1752	1827
PADDT	PAD	1661	2432	3203	1661	2432	3203

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	399	411	423	399	411	423
PADDO	PAD	1818	1913	2008	1818	1913	2008
PADDT	PAD	1954	2379	2805	1954	2379	2805

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	399	411	423	399	411	423
PADDO	PAD	1584	1648	1712	1584	1648	1712
PADDT	PAD	1519	2431	3344	1519	2431	3344

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

SCCU2C

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	119	130	141	119	130	141
A0	F1	352	372	392	352	372	392
A0	FCO	112	195	278	112	195	278
A1	F1	119	130	141	119	130	141
A1	FCO	112	195	278	112	195	278
B0	F0	119	130	141	119	130	141
B0	F1	352	372	392	352	372	392
B0	FCO	112	195	278	112	195	278
B1	F1	119	130	141	119	130	141
B1	FCO	112	195	278	112	195	278
C0	F0	119	130	141	119	130	141
C0	F1	352	372	392	352	372	392
C0	FCO	112	195	278	112	195	278
C1	F1	119	130	141	119	130	141
C1	FCO	112	195	278	112	195	278
CLK	Q0	257	283	309	257	283	309
CLK	Q1	257	282	308	257	282	308
D0	F0	119	130	141	119	130	141
D0	F1	352	372	392	352	372	392
D0	FCO	112	195	278	112	195	278
D1	F1	119	130	141	119	130	141
D1	FCO	112	195	278	112	195	278
FCI	F0	140	198	257	140	198	257
FCI	F1	201	237	273	201	237	273
FCI	FCO	39	41	43	39	41	43

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	88	89	90
DI0	posedge CLK	0	0	0	166	173	181
DI0	posedge CLK	0	0	0	167	174	181
DI1	posedge CLK	0	0	0	166	173	181
LSR	posedge CLK	146	185	224	0	0	0
LSR	posedge CLK	146	185	225	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	889	889	889	562	562	562
negedge LSR	444	444	444	1126	1126	1126
posedge CLK	889	889	889	562	562	562
posedge LSR	444	444	444	1126	1126	1126

SDPRAME

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	Q0	257	283	309	257	283	309
CLK	Q1	257	282	308	257	282	308
RAD0	F0	119	130	141	119	130	141
RAD0	F1	119	130	141	119	130	141
RAD1	F0	119	130	141	119	130	141
RAD1	F1	119	130	141	119	130	141
RAD2	F0	119	130	141	119	130	141
RAD2	F1	119	130	141	119	130	141
RAD3	F0	119	130	141	119	130	141
RAD3	F1	119	130	141	119	130	141
WCK	F0	553	556	559	553	556	559
WCK	F1	555	558	562	555	558	562

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI0	posedge CLK	0	0	0	166	173	181
DI1	posedge CLK	0	0	0	166	173	181
WAD0	posedge WCK	0	0	0	175	194	213
WAD1	posedge WCK	0	0	0	181	199	217
WAD2	posedge WCK	0	0	0	169	189	209
WAD3	posedge WCK	0	0	0	179	197	215
WD0	posedge WCK	0	0	0	132	153	175
WD1	posedge WCK	0	0	0	134	154	174
WRE	posedge WCK	143	175	208	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	889	889	889	562	562	562
negedge WCK	444	444	444	1126	1126	1126
posedge CLK	889	889	889	562	562	562
posedge WCK	444	444	444	1126	1126	1126

SLOGICB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	119	130	141	119	130	141
A0	OFX0	156	197	239	156	197	239
A1	F1	119	130	141	119	130	141
A1	OFX0	156	197	239	156	197	239
B0	F0	119	130	141	119	130	141
B0	OFX0	156	197	239	156	197	239
B1	F1	119	130	141	119	130	141
B1	OFX0	156	197	239	156	197	239
C0	F0	119	130	141	119	130	141
C0	OFX0	156	197	239	156	197	239
C1	F1	119	130	141	119	130	141
C1	OFX0	156	197	239	156	197	239
CLK	Q0	257	283	309	257	283	309
CLK	Q1	257	282	308	257	282	308
D0	F0	119	130	141	119	130	141
D0	OFX0	156	197	239	156	197	239
D1	F1	119	130	141	119	130	141
D1	OFX0	156	197	239	156	197	239
FXA	OFX1	111	125	140	111	125	140
FXB	OFX1	111	126	141	111	126	141
M0	OFX0	113	132	151	113	132	151
M1	OFX1	113	130	148	113	130	148

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	88	89	90
DI0	posedge CLK	0	0	0	166	173	181
DI0	posedge CLK	0	0	0	167	174	181
DI1	posedge CLK	0	0	0	166	173	181
LSR	posedge CLK	146	185	225	0	0	0
M0	posedge CLK	0	0	0	153	167	181
M1	posedge CLK	0	0	0	153	167	181

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	889	889	889	562	562	562
negedge LSR	444	444	444	1126	1126	1126
posedge CLK	889	889	889	562	562	562
posedge LSR	444	444	444	1126	1126	1126

SRAMWB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	WADO3	0	0	0	0	0	0
A1	WDO1	0	0	0	0	0	0
B0	WADO1	0	0	0	0	0	0
B1	WDO3	0	0	0	0	0	0
C0	WADO2	0	0	0	0	0	0
C1	WDO0	0	0	0	0	0	0
D0	WADO0	0	0	0	0	0	0
D1	WDO2	0	0	0	0	0	0

ECP5 Speed Grade -8_5G Cell Timings

Contents

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX1F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=ODDRX1F

Propagation Delays

Width Checks

IOLOGIC:MODE=ODDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=OREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=TSREG

Propagation Delays

Setup/Hold Checks

Width Checks

MULT18X18D:REGS=ALL

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=INPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=NONE

Propagation Delays

MULT18X18D:REGS=OUTPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=PIPELINE

Propagation Delays

Setup/Hold Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks