ECP5 Speed Grade -8 Cell Timings

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
IOLOGIC:MODE=IDDRX1F
IOLOGIC:MODE=IDDRX2F
IOLOGIC:MODE=IREG
IOLOGIC:MODE=ODDRX1F
IOLOGIC:MODE=ODDRX2F
IOLOGIC:MODE=OREG
IOLOGIC:MODE=TSREG
MULT18X18D:REGS=ALL
MULT18X18D:REGS=INPUT
MULT18X18D:REGS=NONE
MULT18X18D:REGS=OUTPUT
MULT18X18D:REGS=PIPELINE
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SCCU2C
SDPRAME
SLOGICB
SRAMWB

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4074	4086	4099	4074	4086	4099
CLKA	DOA1	4074	4086	4099	4074	4086	4099
CLKA	DOA10	4074	4086	4099	4074	4086	4099
CLKA	DOA11	4074	4086	4099	4074	4086	4099
CLKA	DOA12	4074	4086	4099	4074	4086	4099
CLKA	DOA13	4074	4086	4099	4074	4086	4099
CLKA	DOA14	4074	4086	4099	4074	4086	4099
CLKA	DOA15	4074	4086	4099	4074	4086	4099
CLKA	DOA16	4074	4086	4099	4074	4086	4099
CLKA	DOA17	4074	4086	4099	4074	4086	4099
CLKA	DOA2	4074	4086	4099	4074	4086	4099
CLKA	DOA3	4074	4086	4099	4074	4086	4099
CLKA	DOA4	4074	4086	4099	4074	4086	4099
CLKA	DOA5	4074	4086	4099	4074	4086	4099
CLKA	DOA6	4074	4086	4099	4074	4086	4099
CLKA	DOA7	4074	4086	4099	4074	4086	4099
CLKA	DOA8	4074	4086	4099	4074	4086	4099
CLKA	DOA9	4074	4086	4099	4074	4086	4099
CLKB	DOB0	4246	4254	4263	4246	4254	4263
CLKB	DOB1	4246	4254	4263	4246	4254	4263
CLKB	DOB10	4246	4254	4263	4246	4254	4263
CLKB	DOB11	4246	4254	4263	4246	4254	4263
CLKB	DOB12	4246	4254	4263	4246	4254	4263
CLKB	DOB13	4246	4254	4263	4246	4254	4263
CLKB	DOB14	4246	4254	4263	4246	4254	4263
CLKB	DOB15	4246	4254	4263	4246	4254	4263
CLKB	DOB16	4246	4254	4263	4246	4254	4263
CLKB	DOB17	4246	4254	4263	4246	4254	4263
CLKB	DOB2	4246	4254	4263	4246	4254	4263
CLKB	DOB3	4246	4254	4263	4246	4254	4263
CLKB	DOB4	4246	4254	4263	4246	4254	4263
CLKB	DOB5	4246	4254	4263	4246	4254	4263
CLKB	DOB6	4246	4254	4263	4246	4254	4263
CLKB	DOB7	4246	4254	4263	4246	4254	4263
CLKB	DOB8	4246	4254	4263	4246	4254	4263
CLKB	DOB9	4246	4254	4263	4246	4254	4263

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	202	202	202	5	5	5
ADA1	posedge CLKA	202	202	202	5	5	5
ADA10	posedge CLKA	202	202	202	5	5	5
ADA11	posedge CLKA	202	202	202	5	5	5
ADA12	posedge CLKA	202	202	202	5	5	5
ADA13	posedge CLKA	202	202	202	5	5	5
ADA2	posedge CLKA	202	202	202	5	5	5
ADA3	posedge CLKA	202	202	202	5	5	5
ADA4	posedge CLKA	202	202	202	5	5	5
ADA5	posedge CLKA	202	202	202	5	5	5
ADA6	posedge CLKA	202	202	202	5	5	5
ADA7	posedge CLKA	202	202	202	5	5	5
ADA8	posedge CLKA	202	202	202	5	5	5
ADA9	posedge CLKA	202	202	202	5	5	5
ADB0	posedge CLKB	174	174	174	86	86	86
ADB1	posedge CLKB	174	174	174	86	86	86
ADB10	posedge CLKB	174	174	174	86	86	86
ADB11	posedge CLKB	174	174	174	86	86	86
ADB12	posedge CLKB	174	174	174	86	86	86
ADB13	posedge CLKB	174	174	174	86	86	86
ADB2	posedge CLKB	174	174	174	86	86	86
ADB3	posedge CLKB	174	174	174	86	86	86
ADB4	posedge CLKB	174	174	174	86	86	86
ADB5	posedge CLKB	174	174	174	86	86	86
ADB6	posedge CLKB	174	174	174	86	86	86
ADB7	posedge CLKB	174	174	174	86	86	86
ADB8	posedge CLKB	174	174	174	86	86	86
ADB9	posedge CLKB	174	174	174	86	86	86
CEA	posedge CLKA	158	158	158	74	74	74
CEB	posedge CLKB	256	256	256	71	71	71
CSA0	posedge CLKA	27	27	27	154	154	154
CSA1	posedge CLKA	27	27	27	154	154	154
CSA2	posedge CLKA	27	27	27	154	154	154
CSB0	posedge CLKB	0	0	0	297	297	297
CSB1	posedge CLKB	0	0	0	297	297	297
CSB2	posedge CLKB	0	0	0	297	297	297
DIA0	posedge CLKA	179	179	179	30	30	30
DIA1	posedge CLKA	179	179	179	30	30	30
DIA10	posedge CLKA	179	179	179	30	30	30
DIA11	posedge CLKA	179	179	179	30	30	30
DIA12	posedge CLKA	179	179	179	30	30	30
DIA13	posedge CLKA	179	179	179	30	30	30
DIA14	posedge CLKA	179	179	179	30	30	30
DIA15	posedge CLKA	179	179	179	30	30	30
DIA16	posedge CLKA	179	179	179	30	30	30
DIA17	posedge CLKA	179	179	179	30	30	30
DIA2	posedge CLKA	179	179	179	30	30	30
DIA3	posedge CLKA	179	179	179	30	30	30
DIA4	posedge CLKA	179	179	179	30	30	30
DIA5	posedge CLKA	179	179	179	30	30	30
DIA6	posedge CLKA	179	179	179	30	30	30
DIA7	posedge CLKA	179	179	179	30	30	30
DIA8	posedge CLKA	179	179	179	30	30	30
DIA9	posedge CLKA	179	179	179	30	30	30
DIB0	posedge CLKB	129	129	129	197	197	197
DIB1	posedge CLKB	129	129	129	197	197	197
DIB10	posedge CLKB	129	129	129	197	197	197
DIB11	posedge CLKB	129	129	129	197	197	197
DIB12	posedge CLKB	129	129	129	197	197	197
DIB13	posedge CLKB	129	129	129	197	197	197
DIB14	posedge CLKB	129	129	129	197	197	197
DIB15	posedge CLKB	129	129	129	197	197	197
DIB16	posedge CLKB	129	129	129	197	197	197
DIB17	posedge CLKB	129	129	129	197	197	197
DIB2	posedge CLKB	129	129	129	197	197	197
DIB3	posedge CLKB	129	129	129	197	197	197
DIB4	posedge CLKB	129	129	129	197	197	197
DIB5	posedge CLKB	129	129	129	197	197	197
DIB6	posedge CLKB	129	129	129	197	197	197
DIB7	posedge CLKB	129	129	129	197	197	197
DIB8	posedge CLKB	129	129	129	197	197	197
DIB9	posedge CLKB	129	129	129	197	197	197
OCEA	posedge CLKA	188	188	188	0	0	0
OCEB	posedge CLKB	196	196	196	0	0	0
RSTA	posedge CLKA	444	444	444	0	0	0
RSTB	posedge CLKB	449	449	449	0	0	0
WEA	posedge CLKA	129	129	129	88	88	88
WEB	posedge CLKB	0	0	0	323	323	323

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1842	1842	1842	271	271	271
negedge CLKB	1842	1842	1842	271	271	271
posedge CLKA	1842	1842	1842	271	271	271
posedge CLKB	1842	1842	1842	271	271	271

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4074	4086	4099	4074	4086	4099
CLKA	DOA1	4074	4086	4099	4074	4086	4099
CLKA	DOA10	4074	4086	4099	4074	4086	4099
CLKA	DOA11	4074	4086	4099	4074	4086	4099
CLKA	DOA12	4074	4086	4099	4074	4086	4099
CLKA	DOA13	4074	4086	4099	4074	4086	4099
CLKA	DOA14	4074	4086	4099	4074	4086	4099
CLKA	DOA15	4074	4086	4099	4074	4086	4099
CLKA	DOA16	4074	4086	4099	4074	4086	4099
CLKA	DOA17	4074	4086	4099	4074	4086	4099
CLKA	DOA2	4074	4086	4099	4074	4086	4099
CLKA	DOA3	4074	4086	4099	4074	4086	4099
CLKA	DOA4	4074	4086	4099	4074	4086	4099
CLKA	DOA5	4074	4086	4099	4074	4086	4099
CLKA	DOA6	4074	4086	4099	4074	4086	4099
CLKA	DOA7	4074	4086	4099	4074	4086	4099
CLKA	DOA8	4074	4086	4099	4074	4086	4099
CLKA	DOA9	4074	4086	4099	4074	4086	4099
CLKB	DOB0	679	698	718	679	698	718
CLKB	DOB1	679	698	718	679	698	718
CLKB	DOB10	679	698	718	679	698	718
CLKB	DOB11	679	698	718	679	698	718
CLKB	DOB12	679	698	718	679	698	718
CLKB	DOB13	679	698	718	679	698	718
CLKB	DOB14	679	698	718	679	698	718
CLKB	DOB15	679	698	718	679	698	718
CLKB	DOB16	679	698	718	679	698	718
CLKB	DOB17	679	698	718	679	698	718
CLKB	DOB2	679	698	718	679	698	718
CLKB	DOB3	679	698	718	679	698	718
CLKB	DOB4	679	698	718	679	698	718
CLKB	DOB5	679	698	718	679	698	718
CLKB	DOB6	679	698	718	679	698	718
CLKB	DOB7	679	698	718	679	698	718
CLKB	DOB8	679	698	718	679	698	718
CLKB	DOB9	679	698	718	679	698	718

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	202	202	202	5	5	5
ADA1	posedge CLKA	202	202	202	5	5	5
ADA10	posedge CLKA	202	202	202	5	5	5
ADA11	posedge CLKA	202	202	202	5	5	5
ADA12	posedge CLKA	202	202	202	5	5	5
ADA13	posedge CLKA	202	202	202	5	5	5
ADA2	posedge CLKA	202	202	202	5	5	5
ADA3	posedge CLKA	202	202	202	5	5	5
ADA4	posedge CLKA	202	202	202	5	5	5
ADA5	posedge CLKA	202	202	202	5	5	5
ADA6	posedge CLKA	202	202	202	5	5	5
ADA7	posedge CLKA	202	202	202	5	5	5
ADA8	posedge CLKA	202	202	202	5	5	5
ADA9	posedge CLKA	202	202	202	5	5	5
ADB0	posedge CLKB	174	174	174	86	86	86
ADB1	posedge CLKB	174	174	174	86	86	86
ADB10	posedge CLKB	174	174	174	86	86	86
ADB11	posedge CLKB	174	174	174	86	86	86
ADB12	posedge CLKB	174	174	174	86	86	86
ADB13	posedge CLKB	174	174	174	86	86	86
ADB2	posedge CLKB	174	174	174	86	86	86
ADB3	posedge CLKB	174	174	174	86	86	86
ADB4	posedge CLKB	174	174	174	86	86	86
ADB5	posedge CLKB	174	174	174	86	86	86
ADB6	posedge CLKB	174	174	174	86	86	86
ADB7	posedge CLKB	174	174	174	86	86	86
ADB8	posedge CLKB	174	174	174	86	86	86
ADB9	posedge CLKB	174	174	174	86	86	86
CEA	posedge CLKA	158	158	158	74	74	74
CEB	posedge CLKB	256	256	256	71	71	71
CSA0	posedge CLKA	27	27	27	154	154	154
CSA1	posedge CLKA	27	27	27	154	154	154
CSA2	posedge CLKA	27	27	27	154	154	154
CSB0	posedge CLKB	0	0	0	297	297	297
CSB1	posedge CLKB	0	0	0	297	297	297
CSB2	posedge CLKB	0	0	0	297	297	297
DIA0	posedge CLKA	179	179	179	30	30	30
DIA1	posedge CLKA	179	179	179	30	30	30
DIA10	posedge CLKA	179	179	179	30	30	30
DIA11	posedge CLKA	179	179	179	30	30	30
DIA12	posedge CLKA	179	179	179	30	30	30
DIA13	posedge CLKA	179	179	179	30	30	30
DIA14	posedge CLKA	179	179	179	30	30	30
DIA15	posedge CLKA	179	179	179	30	30	30
DIA16	posedge CLKA	179	179	179	30	30	30
DIA17	posedge CLKA	179	179	179	30	30	30
DIA2	posedge CLKA	179	179	179	30	30	30
DIA3	posedge CLKA	179	179	179	30	30	30
DIA4	posedge CLKA	179	179	179	30	30	30
DIA5	posedge CLKA	179	179	179	30	30	30
DIA6	posedge CLKA	179	179	179	30	30	30
DIA7	posedge CLKA	179	179	179	30	30	30
DIA8	posedge CLKA	179	179	179	30	30	30
DIA9	posedge CLKA	179	179	179	30	30	30
DIB0	posedge CLKB	129	129	129	197	197	197
DIB1	posedge CLKB	129	129	129	197	197	197
DIB10	posedge CLKB	129	129	129	197	197	197
DIB11	posedge CLKB	129	129	129	197	197	197
DIB12	posedge CLKB	129	129	129	197	197	197
DIB13	posedge CLKB	129	129	129	197	197	197
DIB14	posedge CLKB	129	129	129	197	197	197
DIB15	posedge CLKB	129	129	129	197	197	197
DIB16	posedge CLKB	129	129	129	197	197	197
DIB17	posedge CLKB	129	129	129	197	197	197
DIB2	posedge CLKB	129	129	129	197	197	197
DIB3	posedge CLKB	129	129	129	197	197	197
DIB4	posedge CLKB	129	129	129	197	197	197
DIB5	posedge CLKB	129	129	129	197	197	197
DIB6	posedge CLKB	129	129	129	197	197	197
DIB7	posedge CLKB	129	129	129	197	197	197
DIB8	posedge CLKB	129	129	129	197	197	197
DIB9	posedge CLKB	129	129	129	197	197	197
OCEA	posedge CLKA	188	188	188	0	0	0
OCEB	posedge CLKB	196	196	196	0	0	0
RSTA	posedge CLKA	444	444	444	0	0	0
RSTB	posedge CLKB	449	449	449	0	0	0
WEA	posedge CLKA	129	129	129	88	88	88
WEB	posedge CLKB	0	0	0	323	323	323

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1842	1842	1842	271	271	271
negedge CLKB	1842	1842	1842	271	271	271
posedge CLKA	1842	1842	1842	271	271	271
posedge CLKB	1842	1842	1842	271	271	271

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	698	718	738	698	718	738
CLKA	DOA1	698	718	738	698	718	738
CLKA	DOA10	698	718	738	698	718	738
CLKA	DOA11	698	718	738	698	718	738
CLKA	DOA12	698	718	738	698	718	738
CLKA	DOA13	698	718	738	698	718	738
CLKA	DOA14	698	718	738	698	718	738
CLKA	DOA15	698	718	738	698	718	738
CLKA	DOA16	698	718	738	698	718	738
CLKA	DOA17	698	718	738	698	718	738
CLKA	DOA2	698	718	738	698	718	738
CLKA	DOA3	698	718	738	698	718	738
CLKA	DOA4	698	718	738	698	718	738
CLKA	DOA5	698	718	738	698	718	738
CLKA	DOA6	698	718	738	698	718	738
CLKA	DOA7	698	718	738	698	718	738
CLKA	DOA8	698	718	738	698	718	738
CLKA	DOA9	698	718	738	698	718	738
CLKB	DOB0	4246	4254	4263	4246	4254	4263
CLKB	DOB1	4246	4254	4263	4246	4254	4263
CLKB	DOB10	4246	4254	4263	4246	4254	4263
CLKB	DOB11	4246	4254	4263	4246	4254	4263
CLKB	DOB12	4246	4254	4263	4246	4254	4263
CLKB	DOB13	4246	4254	4263	4246	4254	4263
CLKB	DOB14	4246	4254	4263	4246	4254	4263
CLKB	DOB15	4246	4254	4263	4246	4254	4263
CLKB	DOB16	4246	4254	4263	4246	4254	4263
CLKB	DOB17	4246	4254	4263	4246	4254	4263
CLKB	DOB2	4246	4254	4263	4246	4254	4263
CLKB	DOB3	4246	4254	4263	4246	4254	4263
CLKB	DOB4	4246	4254	4263	4246	4254	4263
CLKB	DOB5	4246	4254	4263	4246	4254	4263
CLKB	DOB6	4246	4254	4263	4246	4254	4263
CLKB	DOB7	4246	4254	4263	4246	4254	4263
CLKB	DOB8	4246	4254	4263	4246	4254	4263
CLKB	DOB9	4246	4254	4263	4246	4254	4263

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	202	202	202	5	5	5
ADA1	posedge CLKA	202	202	202	5	5	5
ADA10	posedge CLKA	202	202	202	5	5	5
ADA11	posedge CLKA	202	202	202	5	5	5
ADA12	posedge CLKA	202	202	202	5	5	5
ADA13	posedge CLKA	202	202	202	5	5	5
ADA2	posedge CLKA	202	202	202	5	5	5
ADA3	posedge CLKA	202	202	202	5	5	5
ADA4	posedge CLKA	202	202	202	5	5	5
ADA5	posedge CLKA	202	202	202	5	5	5
ADA6	posedge CLKA	202	202	202	5	5	5
ADA7	posedge CLKA	202	202	202	5	5	5
ADA8	posedge CLKA	202	202	202	5	5	5
ADA9	posedge CLKA	202	202	202	5	5	5
ADB0	posedge CLKB	174	174	174	86	86	86
ADB1	posedge CLKB	174	174	174	86	86	86
ADB10	posedge CLKB	174	174	174	86	86	86
ADB11	posedge CLKB	174	174	174	86	86	86
ADB12	posedge CLKB	174	174	174	86	86	86
ADB13	posedge CLKB	174	174	174	86	86	86
ADB2	posedge CLKB	174	174	174	86	86	86
ADB3	posedge CLKB	174	174	174	86	86	86
ADB4	posedge CLKB	174	174	174	86	86	86
ADB5	posedge CLKB	174	174	174	86	86	86
ADB6	posedge CLKB	174	174	174	86	86	86
ADB7	posedge CLKB	174	174	174	86	86	86
ADB8	posedge CLKB	174	174	174	86	86	86
ADB9	posedge CLKB	174	174	174	86	86	86
CEA	posedge CLKA	158	158	158	74	74	74
CEB	posedge CLKB	256	256	256	71	71	71
CSA0	posedge CLKA	27	27	27	154	154	154
CSA1	posedge CLKA	27	27	27	154	154	154
CSA2	posedge CLKA	27	27	27	154	154	154
CSB0	posedge CLKB	0	0	0	297	297	297
CSB1	posedge CLKB	0	0	0	297	297	297
CSB2	posedge CLKB	0	0	0	297	297	297
DIA0	posedge CLKA	179	179	179	30	30	30
DIA1	posedge CLKA	179	179	179	30	30	30
DIA10	posedge CLKA	179	179	179	30	30	30
DIA11	posedge CLKA	179	179	179	30	30	30
DIA12	posedge CLKA	179	179	179	30	30	30
DIA13	posedge CLKA	179	179	179	30	30	30
DIA14	posedge CLKA	179	179	179	30	30	30
DIA15	posedge CLKA	179	179	179	30	30	30
DIA16	posedge CLKA	179	179	179	30	30	30
DIA17	posedge CLKA	179	179	179	30	30	30
DIA2	posedge CLKA	179	179	179	30	30	30
DIA3	posedge CLKA	179	179	179	30	30	30
DIA4	posedge CLKA	179	179	179	30	30	30
DIA5	posedge CLKA	179	179	179	30	30	30
DIA6	posedge CLKA	179	179	179	30	30	30
DIA7	posedge CLKA	179	179	179	30	30	30
DIA8	posedge CLKA	179	179	179	30	30	30
DIA9	posedge CLKA	179	179	179	30	30	30
DIB0	posedge CLKB	129	129	129	197	197	197
DIB1	posedge CLKB	129	129	129	197	197	197
DIB10	posedge CLKB	129	129	129	197	197	197
DIB11	posedge CLKB	129	129	129	197	197	197
DIB12	posedge CLKB	129	129	129	197	197	197
DIB13	posedge CLKB	129	129	129	197	197	197
DIB14	posedge CLKB	129	129	129	197	197	197
DIB15	posedge CLKB	129	129	129	197	197	197
DIB16	posedge CLKB	129	129	129	197	197	197
DIB17	posedge CLKB	129	129	129	197	197	197
DIB2	posedge CLKB	129	129	129	197	197	197
DIB3	posedge CLKB	129	129	129	197	197	197
DIB4	posedge CLKB	129	129	129	197	197	197
DIB5	posedge CLKB	129	129	129	197	197	197
DIB6	posedge CLKB	129	129	129	197	197	197
DIB7	posedge CLKB	129	129	129	197	197	197
DIB8	posedge CLKB	129	129	129	197	197	197
DIB9	posedge CLKB	129	129	129	197	197	197
OCEA	posedge CLKA	188	188	188	0	0	0
OCEB	posedge CLKB	196	196	196	0	0	0
RSTA	posedge CLKA	444	444	444	0	0	0
RSTB	posedge CLKB	449	449	449	0	0	0
WEA	posedge CLKA	129	129	129	88	88	88
WEB	posedge CLKB	0	0	0	323	323	323

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1842	1842	1842	271	271	271
negedge CLKB	1842	1842	1842	271	271	271
posedge CLKA	1842	1842	1842	271	271	271
posedge CLKB	1842	1842	1842	271	271	271

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	698	718	738	698	718	738
CLKA	DOA1	698	718	738	698	718	738
CLKA	DOA10	698	718	738	698	718	738
CLKA	DOA11	698	718	738	698	718	738
CLKA	DOA12	698	718	738	698	718	738
CLKA	DOA13	698	718	738	698	718	738
CLKA	DOA14	698	718	738	698	718	738
CLKA	DOA15	698	718	738	698	718	738
CLKA	DOA16	698	718	738	698	718	738
CLKA	DOA17	698	718	738	698	718	738
CLKA	DOA2	698	718	738	698	718	738
CLKA	DOA3	698	718	738	698	718	738
CLKA	DOA4	698	718	738	698	718	738
CLKA	DOA5	698	718	738	698	718	738
CLKA	DOA6	698	718	738	698	718	738
CLKA	DOA7	698	718	738	698	718	738
CLKA	DOA8	698	718	738	698	718	738
CLKA	DOA9	698	718	738	698	718	738
CLKB	DOB0	679	698	718	679	698	718
CLKB	DOB1	679	698	718	679	698	718
CLKB	DOB10	679	698	718	679	698	718
CLKB	DOB11	679	698	718	679	698	718
CLKB	DOB12	679	698	718	679	698	718
CLKB	DOB13	679	698	718	679	698	718
CLKB	DOB14	679	698	718	679	698	718
CLKB	DOB15	679	698	718	679	698	718
CLKB	DOB16	679	698	718	679	698	718
CLKB	DOB17	679	698	718	679	698	718
CLKB	DOB2	679	698	718	679	698	718
CLKB	DOB3	679	698	718	679	698	718
CLKB	DOB4	679	698	718	679	698	718
CLKB	DOB5	679	698	718	679	698	718
CLKB	DOB6	679	698	718	679	698	718
CLKB	DOB7	679	698	718	679	698	718
CLKB	DOB8	679	698	718	679	698	718
CLKB	DOB9	679	698	718	679	698	718

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	202	202	202	5	5	5
ADA1	posedge CLKA	202	202	202	5	5	5
ADA10	posedge CLKA	202	202	202	5	5	5
ADA11	posedge CLKA	202	202	202	5	5	5
ADA12	posedge CLKA	202	202	202	5	5	5
ADA13	posedge CLKA	202	202	202	5	5	5
ADA2	posedge CLKA	202	202	202	5	5	5
ADA3	posedge CLKA	202	202	202	5	5	5
ADA4	posedge CLKA	202	202	202	5	5	5
ADA5	posedge CLKA	202	202	202	5	5	5
ADA6	posedge CLKA	202	202	202	5	5	5
ADA7	posedge CLKA	202	202	202	5	5	5
ADA8	posedge CLKA	202	202	202	5	5	5
ADA9	posedge CLKA	202	202	202	5	5	5
ADB0	posedge CLKB	174	174	174	86	86	86
ADB1	posedge CLKB	174	174	174	86	86	86
ADB10	posedge CLKB	174	174	174	86	86	86
ADB11	posedge CLKB	174	174	174	86	86	86
ADB12	posedge CLKB	174	174	174	86	86	86
ADB13	posedge CLKB	174	174	174	86	86	86
ADB2	posedge CLKB	174	174	174	86	86	86
ADB3	posedge CLKB	174	174	174	86	86	86
ADB4	posedge CLKB	174	174	174	86	86	86
ADB5	posedge CLKB	174	174	174	86	86	86
ADB6	posedge CLKB	174	174	174	86	86	86
ADB7	posedge CLKB	174	174	174	86	86	86
ADB8	posedge CLKB	174	174	174	86	86	86
ADB9	posedge CLKB	174	174	174	86	86	86
CEA	posedge CLKA	158	158	158	74	74	74
CEB	posedge CLKB	256	256	256	71	71	71
CSA0	posedge CLKA	27	27	27	154	154	154
CSA1	posedge CLKA	27	27	27	154	154	154
CSA2	posedge CLKA	27	27	27	154	154	154
CSB0	posedge CLKB	0	0	0	297	297	297
CSB1	posedge CLKB	0	0	0	297	297	297
CSB2	posedge CLKB	0	0	0	297	297	297
DIA0	posedge CLKA	179	179	179	30	30	30
DIA1	posedge CLKA	179	179	179	30	30	30
DIA10	posedge CLKA	179	179	179	30	30	30
DIA11	posedge CLKA	179	179	179	30	30	30
DIA12	posedge CLKA	179	179	179	30	30	30
DIA13	posedge CLKA	179	179	179	30	30	30
DIA14	posedge CLKA	179	179	179	30	30	30
DIA15	posedge CLKA	179	179	179	30	30	30
DIA16	posedge CLKA	179	179	179	30	30	30
DIA17	posedge CLKA	179	179	179	30	30	30
DIA2	posedge CLKA	179	179	179	30	30	30
DIA3	posedge CLKA	179	179	179	30	30	30
DIA4	posedge CLKA	179	179	179	30	30	30
DIA5	posedge CLKA	179	179	179	30	30	30
DIA6	posedge CLKA	179	179	179	30	30	30
DIA7	posedge CLKA	179	179	179	30	30	30
DIA8	posedge CLKA	179	179	179	30	30	30
DIA9	posedge CLKA	179	179	179	30	30	30
DIB0	posedge CLKB	129	129	129	197	197	197
DIB1	posedge CLKB	129	129	129	197	197	197
DIB10	posedge CLKB	129	129	129	197	197	197
DIB11	posedge CLKB	129	129	129	197	197	197
DIB12	posedge CLKB	129	129	129	197	197	197
DIB13	posedge CLKB	129	129	129	197	197	197
DIB14	posedge CLKB	129	129	129	197	197	197
DIB15	posedge CLKB	129	129	129	197	197	197
DIB16	posedge CLKB	129	129	129	197	197	197
DIB17	posedge CLKB	129	129	129	197	197	197
DIB2	posedge CLKB	129	129	129	197	197	197
DIB3	posedge CLKB	129	129	129	197	197	197
DIB4	posedge CLKB	129	129	129	197	197	197
DIB5	posedge CLKB	129	129	129	197	197	197
DIB6	posedge CLKB	129	129	129	197	197	197
DIB7	posedge CLKB	129	129	129	197	197	197
DIB8	posedge CLKB	129	129	129	197	197	197
DIB9	posedge CLKB	129	129	129	197	197	197
OCEA	posedge CLKA	188	188	188	0	0	0
OCEB	posedge CLKB	196	196	196	0	0	0
RSTA	posedge CLKA	444	444	444	0	0	0
RSTB	posedge CLKB	449	449	449	0	0	0
WEA	posedge CLKA	129	129	129	88	88	88
WEB	posedge CLKB	0	0	0	323	323	323

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1842	1842	1842	271	271	271
negedge CLKB	1842	1842	1842	271	271	271
posedge CLKA	1842	1842	1842	271	271	271
posedge CLKB	1842	1842	1842	271	271	271

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4074	4086	4099	4074	4086	4099
CLKA	DOA1	4074	4086	4099	4074	4086	4099
CLKA	DOA10	4074	4086	4099	4074	4086	4099
CLKA	DOA11	4074	4086	4099	4074	4086	4099
CLKA	DOA12	4074	4086	4099	4074	4086	4099
CLKA	DOA13	4074	4086	4099	4074	4086	4099
CLKA	DOA14	4074	4086	4099	4074	4086	4099
CLKA	DOA15	4074	4086	4099	4074	4086	4099
CLKA	DOA16	4074	4086	4099	4074	4086	4099
CLKA	DOA17	4074	4086	4099	4074	4086	4099
CLKA	DOA2	4074	4086	4099	4074	4086	4099
CLKA	DOA3	4074	4086	4099	4074	4086	4099
CLKA	DOA4	4074	4086	4099	4074	4086	4099
CLKA	DOA5	4074	4086	4099	4074	4086	4099
CLKA	DOA6	4074	4086	4099	4074	4086	4099
CLKA	DOA7	4074	4086	4099	4074	4086	4099
CLKA	DOA8	4074	4086	4099	4074	4086	4099
CLKA	DOA9	4074	4086	4099	4074	4086	4099
CLKB	DOB0	4246	4254	4263	4246	4254	4263
CLKB	DOB1	4246	4254	4263	4246	4254	4263
CLKB	DOB10	4246	4254	4263	4246	4254	4263
CLKB	DOB11	4246	4254	4263	4246	4254	4263
CLKB	DOB12	4246	4254	4263	4246	4254	4263
CLKB	DOB13	4246	4254	4263	4246	4254	4263
CLKB	DOB14	4246	4254	4263	4246	4254	4263
CLKB	DOB15	4246	4254	4263	4246	4254	4263
CLKB	DOB16	4246	4254	4263	4246	4254	4263
CLKB	DOB17	4246	4254	4263	4246	4254	4263
CLKB	DOB2	4246	4254	4263	4246	4254	4263
CLKB	DOB3	4246	4254	4263	4246	4254	4263
CLKB	DOB4	4246	4254	4263	4246	4254	4263
CLKB	DOB5	4246	4254	4263	4246	4254	4263
CLKB	DOB6	4246	4254	4263	4246	4254	4263
CLKB	DOB7	4246	4254	4263	4246	4254	4263
CLKB	DOB8	4246	4254	4263	4246	4254	4263
CLKB	DOB9	4246	4254	4263	4246	4254	4263

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	202	202	202	5	5	5
ADA1	posedge CLKA	202	202	202	5	5	5
ADA10	posedge CLKA	202	202	202	5	5	5
ADA11	posedge CLKA	202	202	202	5	5	5
ADA12	posedge CLKA	202	202	202	5	5	5
ADA13	posedge CLKA	202	202	202	5	5	5
ADA2	posedge CLKA	202	202	202	5	5	5
ADA3	posedge CLKA	202	202	202	5	5	5
ADA4	posedge CLKA	202	202	202	5	5	5
ADA5	posedge CLKA	202	202	202	5	5	5
ADA6	posedge CLKA	202	202	202	5	5	5
ADA7	posedge CLKA	202	202	202	5	5	5
ADA8	posedge CLKA	202	202	202	5	5	5
ADA9	posedge CLKA	202	202	202	5	5	5
ADB0	posedge CLKB	174	174	174	86	86	86
ADB1	posedge CLKB	174	174	174	86	86	86
ADB10	posedge CLKB	174	174	174	86	86	86
ADB11	posedge CLKB	174	174	174	86	86	86
ADB12	posedge CLKB	174	174	174	86	86	86
ADB13	posedge CLKB	174	174	174	86	86	86
ADB2	posedge CLKB	174	174	174	86	86	86
ADB3	posedge CLKB	174	174	174	86	86	86
ADB4	posedge CLKB	174	174	174	86	86	86
ADB5	posedge CLKB	174	174	174	86	86	86
ADB6	posedge CLKB	174	174	174	86	86	86
ADB7	posedge CLKB	174	174	174	86	86	86
ADB8	posedge CLKB	174	174	174	86	86	86
ADB9	posedge CLKB	174	174	174	86	86	86
CEA	posedge CLKA	158	158	158	74	74	74
CEB	posedge CLKB	256	256	256	71	71	71
CSA0	posedge CLKA	27	27	27	154	154	154
CSA1	posedge CLKA	27	27	27	154	154	154
CSA2	posedge CLKA	27	27	27	154	154	154
CSB0	posedge CLKB	0	0	0	297	297	297
CSB1	posedge CLKB	0	0	0	297	297	297
CSB2	posedge CLKB	0	0	0	297	297	297
DIA0	posedge CLKA	179	179	179	30	30	30
DIA1	posedge CLKA	179	179	179	30	30	30
DIA10	posedge CLKA	179	179	179	30	30	30
DIA11	posedge CLKA	179	179	179	30	30	30
DIA12	posedge CLKA	179	179	179	30	30	30
DIA13	posedge CLKA	179	179	179	30	30	30
DIA14	posedge CLKA	179	179	179	30	30	30
DIA15	posedge CLKA	179	179	179	30	30	30
DIA16	posedge CLKA	179	179	179	30	30	30
DIA17	posedge CLKA	179	179	179	30	30	30
DIA2	posedge CLKA	179	179	179	30	30	30
DIA3	posedge CLKA	179	179	179	30	30	30
DIA4	posedge CLKA	179	179	179	30	30	30
DIA5	posedge CLKA	179	179	179	30	30	30
DIA6	posedge CLKA	179	179	179	30	30	30
DIA7	posedge CLKA	179	179	179	30	30	30
DIA8	posedge CLKA	179	179	179	30	30	30
DIA9	posedge CLKA	179	179	179	30	30	30
DIB0	posedge CLKB	129	129	129	197	197	197
DIB1	posedge CLKB	129	129	129	197	197	197
DIB10	posedge CLKB	129	129	129	197	197	197
DIB11	posedge CLKB	129	129	129	197	197	197
DIB12	posedge CLKB	129	129	129	197	197	197
DIB13	posedge CLKB	129	129	129	197	197	197
DIB14	posedge CLKB	129	129	129	197	197	197
DIB15	posedge CLKB	129	129	129	197	197	197
DIB16	posedge CLKB	129	129	129	197	197	197
DIB17	posedge CLKB	129	129	129	197	197	197
DIB2	posedge CLKB	129	129	129	197	197	197
DIB3	posedge CLKB	129	129	129	197	197	197
DIB4	posedge CLKB	129	129	129	197	197	197
DIB5	posedge CLKB	129	129	129	197	197	197
DIB6	posedge CLKB	129	129	129	197	197	197
DIB7	posedge CLKB	129	129	129	197	197	197
DIB8	posedge CLKB	129	129	129	197	197	197
DIB9	posedge CLKB	129	129	129	197	197	197
OCEA	posedge CLKA	188	188	188	0	0	0
OCEB	posedge CLKB	196	196	196	0	0	0
RSTA	posedge CLKA	444	444	444	0	0	0
RSTB	posedge CLKB	449	449	449	0	0	0
WEA	posedge CLKA	129	129	129	88	88	88
WEB	posedge CLKB	0	0	0	323	323	323

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1842	1842	1842	271	271	271
negedge CLKB	1842	1842	1842	271	271	271
posedge CLKA	1842	1842	1842	271	271	271
posedge CLKB	1842	1842	1842	271	271	271

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4074	4086	4099	4074	4086	4099
CLKA	DOA1	4074	4086	4099	4074	4086	4099
CLKA	DOA10	4074	4086	4099	4074	4086	4099
CLKA	DOA11	4074	4086	4099	4074	4086	4099
CLKA	DOA12	4074	4086	4099	4074	4086	4099
CLKA	DOA13	4074	4086	4099	4074	4086	4099
CLKA	DOA14	4074	4086	4099	4074	4086	4099
CLKA	DOA15	4074	4086	4099	4074	4086	4099
CLKA	DOA16	4074	4086	4099	4074	4086	4099
CLKA	DOA17	4074	4086	4099	4074	4086	4099
CLKA	DOA2	4074	4086	4099	4074	4086	4099
CLKA	DOA3	4074	4086	4099	4074	4086	4099
CLKA	DOA4	4074	4086	4099	4074	4086	4099
CLKA	DOA5	4074	4086	4099	4074	4086	4099
CLKA	DOA6	4074	4086	4099	4074	4086	4099
CLKA	DOA7	4074	4086	4099	4074	4086	4099
CLKA	DOA8	4074	4086	4099	4074	4086	4099
CLKA	DOA9	4074	4086	4099	4074	4086	4099
CLKB	DOB0	4248	4257	4266	4248	4257	4266
CLKB	DOB1	4248	4257	4266	4248	4257	4266
CLKB	DOB10	4248	4257	4266	4248	4257	4266
CLKB	DOB11	4248	4257	4266	4248	4257	4266
CLKB	DOB12	4248	4257	4266	4248	4257	4266
CLKB	DOB13	4248	4257	4266	4248	4257	4266
CLKB	DOB14	4248	4257	4266	4248	4257	4266
CLKB	DOB15	4248	4257	4266	4248	4257	4266
CLKB	DOB16	4248	4257	4266	4248	4257	4266
CLKB	DOB17	4248	4257	4266	4248	4257	4266
CLKB	DOB2	4248	4257	4266	4248	4257	4266
CLKB	DOB3	4248	4257	4266	4248	4257	4266
CLKB	DOB4	4248	4257	4266	4248	4257	4266
CLKB	DOB5	4248	4257	4266	4248	4257	4266
CLKB	DOB6	4248	4257	4266	4248	4257	4266
CLKB	DOB7	4248	4257	4266	4248	4257	4266
CLKB	DOB8	4248	4257	4266	4248	4257	4266
CLKB	DOB9	4248	4257	4266	4248	4257	4266

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	202	202	202	5	5	5
ADA1	posedge CLKA	202	202	202	5	5	5
ADA10	posedge CLKA	202	202	202	5	5	5
ADA11	posedge CLKA	202	202	202	5	5	5
ADA12	posedge CLKA	202	202	202	5	5	5
ADA13	posedge CLKA	202	202	202	5	5	5
ADA2	posedge CLKA	202	202	202	5	5	5
ADA3	posedge CLKA	202	202	202	5	5	5
ADA4	posedge CLKA	202	202	202	5	5	5
ADA5	posedge CLKA	202	202	202	5	5	5
ADA6	posedge CLKA	202	202	202	5	5	5
ADA7	posedge CLKA	202	202	202	5	5	5
ADA8	posedge CLKA	202	202	202	5	5	5
ADA9	posedge CLKA	202	202	202	5	5	5
ADB0	posedge CLKB	174	174	174	86	86	86
ADB1	posedge CLKB	174	174	174	86	86	86
ADB10	posedge CLKB	174	174	174	86	86	86
ADB11	posedge CLKB	174	174	174	86	86	86
ADB12	posedge CLKB	174	174	174	86	86	86
ADB13	posedge CLKB	174	174	174	86	86	86
ADB2	posedge CLKB	174	174	174	86	86	86
ADB3	posedge CLKB	174	174	174	86	86	86
ADB4	posedge CLKB	174	174	174	86	86	86
ADB5	posedge CLKB	174	174	174	86	86	86
ADB6	posedge CLKB	174	174	174	86	86	86
ADB7	posedge CLKB	174	174	174	86	86	86
ADB8	posedge CLKB	174	174	174	86	86	86
ADB9	posedge CLKB	174	174	174	86	86	86
CEA	posedge CLKA	158	158	158	74	74	74
CEB	posedge CLKB	256	256	256	71	71	71
CSA0	posedge CLKA	27	27	27	154	154	154
CSA1	posedge CLKA	27	27	27	154	154	154
CSA2	posedge CLKA	27	27	27	154	154	154
CSB0	posedge CLKB	0	0	0	297	297	297
CSB1	posedge CLKB	0	0	0	297	297	297
CSB2	posedge CLKB	0	0	0	297	297	297
DIA0	posedge CLKA	179	179	179	30	30	30
DIA1	posedge CLKA	179	179	179	30	30	30
DIA10	posedge CLKA	179	179	179	30	30	30
DIA11	posedge CLKA	179	179	179	30	30	30
DIA12	posedge CLKA	179	179	179	30	30	30
DIA13	posedge CLKA	179	179	179	30	30	30
DIA14	posedge CLKA	179	179	179	30	30	30
DIA15	posedge CLKA	179	179	179	30	30	30
DIA16	posedge CLKA	179	179	179	30	30	30
DIA17	posedge CLKA	179	179	179	30	30	30
DIA2	posedge CLKA	179	179	179	30	30	30
DIA3	posedge CLKA	179	179	179	30	30	30
DIA4	posedge CLKA	179	179	179	30	30	30
DIA5	posedge CLKA	179	179	179	30	30	30
DIA6	posedge CLKA	179	179	179	30	30	30
DIA7	posedge CLKA	179	179	179	30	30	30
DIA8	posedge CLKA	179	179	179	30	30	30
DIA9	posedge CLKA	179	179	179	30	30	30
DIB0	posedge CLKB	129	129	129	197	197	197
DIB1	posedge CLKB	129	129	129	197	197	197
DIB10	posedge CLKB	129	129	129	197	197	197
DIB11	posedge CLKB	129	129	129	197	197	197
DIB12	posedge CLKB	129	129	129	197	197	197
DIB13	posedge CLKB	129	129	129	197	197	197
DIB14	posedge CLKB	129	129	129	197	197	197
DIB15	posedge CLKB	129	129	129	197	197	197
DIB16	posedge CLKB	129	129	129	197	197	197
DIB17	posedge CLKB	129	129	129	197	197	197
DIB2	posedge CLKB	129	129	129	197	197	197
DIB3	posedge CLKB	129	129	129	197	197	197
DIB4	posedge CLKB	129	129	129	197	197	197
DIB5	posedge CLKB	129	129	129	197	197	197
DIB6	posedge CLKB	129	129	129	197	197	197
DIB7	posedge CLKB	129	129	129	197	197	197
DIB8	posedge CLKB	129	129	129	197	197	197
DIB9	posedge CLKB	129	129	129	197	197	197
OCEA	posedge CLKA	188	188	188	0	0	0
OCEB	posedge CLKB	196	196	196	0	0	0
RSTA	posedge CLKA	444	444	444	0	0	0
RSTB	posedge CLKB	449	449	449	0	0	0
WEA	posedge CLKA	129	129	129	88	88	88
WEB	posedge CLKB	0	0	0	323	323	323

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1842	1842	1842	271	271	271
negedge CLKB	2335	2335	2335	214	214	214
posedge CLKA	1842	1842	1842	271	271	271
posedge CLKB	2335	2335	2335	214	214	214

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4074	4086	4099	4074	4086	4099
CLKA	DOA1	4074	4086	4099	4074	4086	4099
CLKA	DOA10	4074	4086	4099	4074	4086	4099
CLKA	DOA11	4074	4086	4099	4074	4086	4099
CLKA	DOA12	4074	4086	4099	4074	4086	4099
CLKA	DOA13	4074	4086	4099	4074	4086	4099
CLKA	DOA14	4074	4086	4099	4074	4086	4099
CLKA	DOA15	4074	4086	4099	4074	4086	4099
CLKA	DOA16	4074	4086	4099	4074	4086	4099
CLKA	DOA17	4074	4086	4099	4074	4086	4099
CLKA	DOA2	4074	4086	4099	4074	4086	4099
CLKA	DOA3	4074	4086	4099	4074	4086	4099
CLKA	DOA4	4074	4086	4099	4074	4086	4099
CLKA	DOA5	4074	4086	4099	4074	4086	4099
CLKA	DOA6	4074	4086	4099	4074	4086	4099
CLKA	DOA7	4074	4086	4099	4074	4086	4099
CLKA	DOA8	4074	4086	4099	4074	4086	4099
CLKA	DOA9	4074	4086	4099	4074	4086	4099
CLKB	DOB0	4247	4256	4266	4247	4256	4266
CLKB	DOB1	4247	4256	4266	4247	4256	4266
CLKB	DOB10	4247	4256	4266	4247	4256	4266
CLKB	DOB11	4247	4256	4266	4247	4256	4266
CLKB	DOB12	4247	4256	4266	4247	4256	4266
CLKB	DOB13	4247	4256	4266	4247	4256	4266
CLKB	DOB14	4247	4256	4266	4247	4256	4266
CLKB	DOB15	4247	4256	4266	4247	4256	4266
CLKB	DOB16	4247	4256	4266	4247	4256	4266
CLKB	DOB17	4247	4256	4266	4247	4256	4266
CLKB	DOB2	4247	4256	4266	4247	4256	4266
CLKB	DOB3	4247	4256	4266	4247	4256	4266
CLKB	DOB4	4247	4256	4266	4247	4256	4266
CLKB	DOB5	4247	4256	4266	4247	4256	4266
CLKB	DOB6	4247	4256	4266	4247	4256	4266
CLKB	DOB7	4247	4256	4266	4247	4256	4266
CLKB	DOB8	4247	4256	4266	4247	4256	4266
CLKB	DOB9	4247	4256	4266	4247	4256	4266

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	202	202	202	5	5	5
ADA1	posedge CLKA	202	202	202	5	5	5
ADA10	posedge CLKA	202	202	202	5	5	5
ADA11	posedge CLKA	202	202	202	5	5	5
ADA12	posedge CLKA	202	202	202	5	5	5
ADA13	posedge CLKA	202	202	202	5	5	5
ADA2	posedge CLKA	202	202	202	5	5	5
ADA3	posedge CLKA	202	202	202	5	5	5
ADA4	posedge CLKA	202	202	202	5	5	5
ADA5	posedge CLKA	202	202	202	5	5	5
ADA6	posedge CLKA	202	202	202	5	5	5
ADA7	posedge CLKA	202	202	202	5	5	5
ADA8	posedge CLKA	202	202	202	5	5	5
ADA9	posedge CLKA	202	202	202	5	5	5
ADB0	posedge CLKB	174	174	174	86	86	86
ADB1	posedge CLKB	174	174	174	86	86	86
ADB10	posedge CLKB	174	174	174	86	86	86
ADB11	posedge CLKB	174	174	174	86	86	86
ADB12	posedge CLKB	174	174	174	86	86	86
ADB13	posedge CLKB	174	174	174	86	86	86
ADB2	posedge CLKB	174	174	174	86	86	86
ADB3	posedge CLKB	174	174	174	86	86	86
ADB4	posedge CLKB	174	174	174	86	86	86
ADB5	posedge CLKB	174	174	174	86	86	86
ADB6	posedge CLKB	174	174	174	86	86	86
ADB7	posedge CLKB	174	174	174	86	86	86
ADB8	posedge CLKB	174	174	174	86	86	86
ADB9	posedge CLKB	174	174	174	86	86	86
CEA	posedge CLKA	158	158	158	74	74	74
CEB	posedge CLKB	256	256	256	71	71	71
CSA0	posedge CLKA	27	27	27	154	154	154
CSA1	posedge CLKA	27	27	27	154	154	154
CSA2	posedge CLKA	27	27	27	154	154	154
CSB0	posedge CLKB	0	0	0	297	297	297
CSB1	posedge CLKB	0	0	0	297	297	297
CSB2	posedge CLKB	0	0	0	297	297	297
DIA0	posedge CLKA	179	179	179	30	30	30
DIA1	posedge CLKA	179	179	179	30	30	30
DIA10	posedge CLKA	179	179	179	30	30	30
DIA11	posedge CLKA	179	179	179	30	30	30
DIA12	posedge CLKA	179	179	179	30	30	30
DIA13	posedge CLKA	179	179	179	30	30	30
DIA14	posedge CLKA	179	179	179	30	30	30
DIA15	posedge CLKA	179	179	179	30	30	30
DIA16	posedge CLKA	179	179	179	30	30	30
DIA17	posedge CLKA	179	179	179	30	30	30
DIA2	posedge CLKA	179	179	179	30	30	30
DIA3	posedge CLKA	179	179	179	30	30	30
DIA4	posedge CLKA	179	179	179	30	30	30
DIA5	posedge CLKA	179	179	179	30	30	30
DIA6	posedge CLKA	179	179	179	30	30	30
DIA7	posedge CLKA	179	179	179	30	30	30
DIA8	posedge CLKA	179	179	179	30	30	30
DIA9	posedge CLKA	179	179	179	30	30	30
DIB0	posedge CLKB	129	129	129	197	197	197
DIB1	posedge CLKB	129	129	129	197	197	197
DIB10	posedge CLKB	129	129	129	197	197	197
DIB11	posedge CLKB	129	129	129	197	197	197
DIB12	posedge CLKB	129	129	129	197	197	197
DIB13	posedge CLKB	129	129	129	197	197	197
DIB14	posedge CLKB	129	129	129	197	197	197
DIB15	posedge CLKB	129	129	129	197	197	197
DIB16	posedge CLKB	129	129	129	197	197	197
DIB17	posedge CLKB	129	129	129	197	197	197
DIB2	posedge CLKB	129	129	129	197	197	197
DIB3	posedge CLKB	129	129	129	197	197	197
DIB4	posedge CLKB	129	129	129	197	197	197
DIB5	posedge CLKB	129	129	129	197	197	197
DIB6	posedge CLKB	129	129	129	197	197	197
DIB7	posedge CLKB	129	129	129	197	197	197
DIB8	posedge CLKB	129	129	129	197	197	197
DIB9	posedge CLKB	129	129	129	197	197	197
OCEA	posedge CLKA	188	188	188	0	0	0
OCEB	posedge CLKB	196	196	196	0	0	0
RSTA	posedge CLKA	444	444	444	0	0	0
RSTB	posedge CLKB	449	449	449	0	0	0
WEA	posedge CLKA	129	129	129	88	88	88
WEB	posedge CLKB	0	0	0	323	323	323

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1842	1842	1842	271	271	271
negedge CLKB	1831	1831	1831	273	273	273
posedge CLKA	1842	1842	1842	271	271	271
posedge CLKB	1831	1831	1831	273	273	273

IOLOGIC:MODE=IDDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	281	281	281	281	281	281
CLK	RXDATA1	281	281	281	281	281	281

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge CLK	305	305	305	197	197	197

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=IDDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	353	353	353	353	353	353
CLK	RXDATA1	353	353	353	353	353	353
CLK	RXDATA2	353	353	353	353	353	353
CLK	RXDATA3	353	353	353	353	353	353

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge ECLK	284	284	284	98	98	98
posedge ECLK	posedge CLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1250	1250	1250	400	400	400
posedge ECLK	1250	1250	1250	400	400	400

IOLOGIC:MODE=IREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	INFF	364	364	364	364	364	364

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	62	62	62
DI	posedge CLK	317	317	317	258	258	258
LSR	posedge CLK	81	81	81	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1351	1351	1351	370	370	370
posedge CLK	1351	1351	1351	370	370	370

IOLOGIC:MODE=ODDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	739	741	743	739	741	743

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=ODDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
ECLK	IOLDO	973	975	977	973	975	977

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
TXDATA0	posedge CLK	92	92	92	0	0	0
TXDATA1	posedge CLK	92	92	92	0	0	0
TXDATA2	posedge CLK	92	92	92	0	0	0
TXDATA3	posedge CLK	92	92	92	0	0	0
posedge CLK	posedge ECLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1250	1250	1250	400	400	400
posedge ECLK	1250	1250	1250	400	400	400

IOLOGIC:MODE=OREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	1018	1018	1018	1018	1018	1018

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	59	59	59
LSR	posedge CLK	92	92	92	0	0	0
TXDATA0	posedge CLK	113	113	113	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1351	1351	1351	370	370	370
posedge CLK	1351	1351	1351	370	370	370

IOLOGIC:MODE=TSREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLTO	763	763	763	763	763	763

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	59	59	59
LSR	posedge CLK	92	92	92	0	0	0
TSDATA0	posedge CLK	155	155	155	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1351	1351	1351	370	370	370
posedge CLK	1351	1351	1351	370	370	370

MULT18X18D:REGS=ALL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	483	530	578	483	530	578

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	21	31	42	0	5	32
B	posedge CLK0	21	31	42	0	5	32
CE0	posedge CLK0	147	178	210	0	0	21
RST0	posedge CLK0	84	100	116	42	52	63
SIGNEDA	posedge CLK0	0	0	0	126	136	147
SIGNEDB	posedge CLK0	0	0	0	126	136	147

MULT18X18D:REGS=INPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	2310	2677	3045	2310	2677	3045

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	21	31	42	0	5	32
B	posedge CLK0	21	31	42	0	5	32
CE0	posedge CLK0	147	178	210	0	0	21
RST0	posedge CLK0	84	100	116	42	52	63
SIGNEDA	posedge CLK0	0	0	0	126	136	147
SIGNEDB	posedge CLK0	0	0	0	126	136	147

MULT18X18D:REGS=NONE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A	P	2331	2698	3066	2331	2698	3066
B	P	2331	2698	3066	2331	2698	3066
SIGNEDA	P	2205	2562	2919	2205	2562	2919
SIGNEDB	P	2205	2562	2919	2205	2562	2919

MULT18X18D:REGS=OUTPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	483	530	578	483	530	578

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	2363	2499	2635	0	0	0
B	posedge CLK0	2363	2499	2635	0	0	0
CE0	posedge CLK0	147	178	210	0	0	21
RST0	posedge CLK0	84	100	116	42	52	63
SIGNEDA	posedge CLK0	2236	2362	2489	0	0	0
SIGNEDB	posedge CLK0	2236	2362	2489	0	0	0

MULT18X18D:REGS=PIPELINE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	1082	1097	1113	1082	1097	1113

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	1838	1911	1985	0	0	0
B	posedge CLK0	1838	1911	1985	0	0	0
CE0	posedge CLK0	147	178	210	0	0	21
RST0	posedge CLK0	84	100	116	42	52	63
SIGNEDA	posedge CLK0	1712	1775	1838	0	0	0
SIGNEDB	posedge CLK0	1712	1775	1838	0	0	0

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	594	610	626	594	610	626
PADDO	PAD	1347	1513	1679	1347	1513	1679
PADDT	PAD	1554	1800	2047	1554	1800	2047

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1464	1474	1484	1464	1474	1484
PADDO	PAD	1396	1553	1711	1396	1553	1711
PADDT	PAD	1553	1734	1915	1553	1734	1915

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1145	1191	1237	1145	1191	1237
PADDO	PAD	1441	1587	1734	1441	1587	1734
PADDT	PAD	1750	1888	2027	1750	1888	2027

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	826	851	876	826	851	876
PADDO	PAD	1736	1751	1766	1736	1751	1766
PADDT	PAD	1747	1843	1940	1747	1843	1940

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	921	945	970	921	945	970
PADDO	PAD	1819	2006	2193	1819	2006	2193
PADDT	PAD	2113	2327	2542	2113	2327	2542

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	437	437	437	437	437	437
PADDO	PAD	957	958	959	957	958	959

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	403	413	424	403	413	424
PADDO	PAD	1758	1862	1966	1758	1862	1966
PADDT	PAD	1821	2419	3017	1821	2419	3017

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	403	413	424	403	413	424
PADDO	PAD	1678	1752	1827	1678	1752	1827
PADDT	PAD	1661	2432	3203	1661	2432	3203

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	399	411	423	399	411	423
PADDO	PAD	1818	1913	2008	1818	1913	2008
PADDT	PAD	1954	2379	2805	1954	2379	2805

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	399	411	423	399	411	423
PADDO	PAD	1584	1648	1712	1584	1648	1712
PADDT	PAD	1519	2431	3344	1519	2431	3344

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

SCCU2C

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	153	166	180	153	166	180
A0	F1	449	474	500	449	474	500
A0	FCO	144	249	355	144	249	355
A1	F1	153	166	180	153	166	180
A1	FCO	144	249	355	144	249	355
B0	F0	153	166	180	153	166	180
B0	F1	449	474	500	449	474	500
B0	FCO	144	249	355	144	249	355
B1	F1	153	166	180	153	166	180
B1	FCO	144	249	355	144	249	355
C0	F0	153	166	180	153	166	180
C0	F1	449	474	500	449	474	500
C0	FCO	144	249	355	144	249	355
C1	F1	153	166	180	153	166	180
C1	FCO	144	249	355	144	249	355
CLK	Q0	329	362	395	329	362	395
CLK	Q1	328	360	393	328	360	393
D0	F0	153	166	180	153	166	180
D0	F1	449	474	500	449	474	500
D0	FCO	144	249	355	144	249	355
D1	F1	153	166	180	153	166	180
D1	FCO	144	249	355	144	249	355
FCI	F0	179	253	328	179	253	328
FCI	F1	257	303	349	257	303	349
FCI	FCO	50	53	56	50	53	56

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	113	114	116
DI0	posedge CLK	0	0	0	213	222	232
DI0	posedge CLK	0	0	0	214	223	232
DI1	posedge CLK	0	0	0	213	222	232
LSR	posedge CLK	187	236	286	0	0	0
LSR	posedge CLK	187	237	287	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1134	1134	1134	441	441	441
negedge LSR	567	567	567	882	882	882
posedge CLK	1134	1134	1134	441	441	441
posedge LSR	567	567	567	882	882	882

SDPRAME

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	Q0	329	362	395	329	362	395
CLK	Q1	328	360	393	328	360	393
RAD0	F0	153	166	180	153	166	180
RAD0	F1	153	166	180	153	166	180
RAD1	F0	153	166	180	153	166	180
RAD1	F1	153	166	180	153	166	180
RAD2	F0	153	166	180	153	166	180
RAD2	F1	153	166	180	153	166	180
RAD3	F0	153	166	180	153	166	180
RAD3	F1	153	166	180	153	166	180
WCK	F0	706	710	714	706	710	714
WCK	F1	708	712	717	708	712	717

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI0	posedge CLK	0	0	0	213	222	232
DI1	posedge CLK	0	0	0	213	222	232
WAD0	posedge WCK	0	0	0	224	248	272
WAD1	posedge WCK	0	0	0	232	255	278
WAD2	posedge WCK	0	0	0	216	241	267
WAD3	posedge WCK	0	0	0	229	252	275
WD0	posedge WCK	0	0	0	169	196	224
WD1	posedge WCK	0	0	0	172	197	223
WRE	posedge WCK	183	224	266	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1134	1134	1134	441	441	441
negedge WCK	567	567	567	882	882	882
posedge CLK	1134	1134	1134	441	441	441
posedge WCK	567	567	567	882	882	882

SLOGICB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	153	166	180	153	166	180
A0	OFX0	200	253	306	200	253	306
A1	F1	153	166	180	153	166	180
A1	OFX0	200	253	306	200	253	306
B0	F0	153	166	180	153	166	180
B0	OFX0	200	253	306	200	253	306
B1	F1	153	166	180	153	166	180
B1	OFX0	200	253	306	200	253	306
C0	F0	153	166	180	153	166	180
C0	OFX0	200	253	306	200	253	306
C1	F1	153	166	180	153	166	180
C1	OFX0	200	253	306	200	253	306
CLK	Q0	329	362	395	329	362	395
CLK	Q1	328	360	393	328	360	393
D0	F0	153	166	180	153	166	180
D0	OFX0	200	253	306	200	253	306
D1	F1	153	166	180	153	166	180
D1	OFX0	200	253	306	200	253	306
FXA	OFX1	142	160	179	142	160	179
FXB	OFX1	142	161	180	142	161	180
M0	OFX0	145	169	193	145	169	193
M1	OFX1	145	167	190	145	167	190

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	113	114	116
DI0	posedge CLK	0	0	0	213	222	232
DI0	posedge CLK	0	0	0	214	223	232
DI1	posedge CLK	0	0	0	213	222	232
LSR	posedge CLK	187	237	287	0	0	0
M0	posedge CLK	0	0	0	196	213	231
M1	posedge CLK	0	0	0	196	214	232

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1134	1134	1134	441	441	441
negedge LSR	567	567	567	882	882	882
posedge CLK	1134	1134	1134	441	441	441
posedge LSR	567	567	567	882	882	882

SRAMWB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	WADO3	0	0	0	0	0	0
A1	WDO1	0	0	0	0	0	0
B0	WADO1	0	0	0	0	0	0
B1	WDO3	0	0	0	0	0	0
C0	WADO2	0	0	0	0	0	0
C1	WDO0	0	0	0	0	0	0
D0	WADO0	0	0	0	0	0	0
D1	WDO2	0	0	0	0	0	0

ECP5 Speed Grade -8 Cell Timings

Contents

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX1F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=ODDRX1F

Propagation Delays

Width Checks

IOLOGIC:MODE=ODDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=OREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=TSREG

Propagation Delays

Setup/Hold Checks

Width Checks

MULT18X18D:REGS=ALL

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=INPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=NONE

Propagation Delays

MULT18X18D:REGS=OUTPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=PIPELINE

Propagation Delays

Setup/Hold Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks