ECP5 Speed Grade -7 Cell Timings

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
IOLOGIC:MODE=IDDRX1F
IOLOGIC:MODE=IDDRX2F
IOLOGIC:MODE=IREG
IOLOGIC:MODE=ODDRX1F
IOLOGIC:MODE=ODDRX2F
IOLOGIC:MODE=OREG
IOLOGIC:MODE=TSREG
MULT18X18D:REGS=ALL
MULT18X18D:REGS=INPUT
MULT18X18D:REGS=NONE
MULT18X18D:REGS=OUTPUT
MULT18X18D:REGS=PIPELINE
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SCCU2C
SDPRAME
SLOGICB
SRAMWB

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4804	4829	4854	4804	4829	4854
CLKA	DOA1	4804	4829	4854	4804	4829	4854
CLKA	DOA10	4804	4829	4854	4804	4829	4854
CLKA	DOA11	4804	4829	4854	4804	4829	4854
CLKA	DOA12	4804	4829	4854	4804	4829	4854
CLKA	DOA13	4804	4829	4854	4804	4829	4854
CLKA	DOA14	4804	4829	4854	4804	4829	4854
CLKA	DOA15	4804	4829	4854	4804	4829	4854
CLKA	DOA16	4804	4829	4854	4804	4829	4854
CLKA	DOA17	4804	4829	4854	4804	4829	4854
CLKA	DOA2	4804	4829	4854	4804	4829	4854
CLKA	DOA3	4804	4829	4854	4804	4829	4854
CLKA	DOA4	4804	4829	4854	4804	4829	4854
CLKA	DOA5	4804	4829	4854	4804	4829	4854
CLKA	DOA6	4804	4829	4854	4804	4829	4854
CLKA	DOA7	4804	4829	4854	4804	4829	4854
CLKA	DOA8	4804	4829	4854	4804	4829	4854
CLKA	DOA9	4804	4829	4854	4804	4829	4854
CLKB	DOB0	5020	5033	5046	5020	5033	5046
CLKB	DOB1	5020	5033	5046	5020	5033	5046
CLKB	DOB10	5020	5033	5046	5020	5033	5046
CLKB	DOB11	5020	5033	5046	5020	5033	5046
CLKB	DOB12	5020	5033	5046	5020	5033	5046
CLKB	DOB13	5020	5033	5046	5020	5033	5046
CLKB	DOB14	5020	5033	5046	5020	5033	5046
CLKB	DOB15	5020	5033	5046	5020	5033	5046
CLKB	DOB16	5020	5033	5046	5020	5033	5046
CLKB	DOB17	5020	5033	5046	5020	5033	5046
CLKB	DOB2	5020	5033	5046	5020	5033	5046
CLKB	DOB3	5020	5033	5046	5020	5033	5046
CLKB	DOB4	5020	5033	5046	5020	5033	5046
CLKB	DOB5	5020	5033	5046	5020	5033	5046
CLKB	DOB6	5020	5033	5046	5020	5033	5046
CLKB	DOB7	5020	5033	5046	5020	5033	5046
CLKB	DOB8	5020	5033	5046	5020	5033	5046
CLKB	DOB9	5020	5033	5046	5020	5033	5046

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	226	226	226	3	3	3
ADA1	posedge CLKA	226	226	226	3	3	3
ADA10	posedge CLKA	226	226	226	3	3	3
ADA11	posedge CLKA	226	226	226	3	3	3
ADA12	posedge CLKA	226	226	226	3	3	3
ADA13	posedge CLKA	226	226	226	3	3	3
ADA2	posedge CLKA	226	226	226	3	3	3
ADA3	posedge CLKA	226	226	226	3	3	3
ADA4	posedge CLKA	226	226	226	3	3	3
ADA5	posedge CLKA	226	226	226	3	3	3
ADA6	posedge CLKA	226	226	226	3	3	3
ADA7	posedge CLKA	226	226	226	3	3	3
ADA8	posedge CLKA	226	226	226	3	3	3
ADA9	posedge CLKA	226	226	226	3	3	3
ADB0	posedge CLKB	189	189	189	93	93	93
ADB1	posedge CLKB	189	189	189	93	93	93
ADB10	posedge CLKB	189	189	189	93	93	93
ADB11	posedge CLKB	189	189	189	93	93	93
ADB12	posedge CLKB	189	189	189	93	93	93
ADB13	posedge CLKB	189	189	189	93	93	93
ADB2	posedge CLKB	189	189	189	93	93	93
ADB3	posedge CLKB	189	189	189	93	93	93
ADB4	posedge CLKB	189	189	189	93	93	93
ADB5	posedge CLKB	189	189	189	93	93	93
ADB6	posedge CLKB	189	189	189	93	93	93
ADB7	posedge CLKB	189	189	189	93	93	93
ADB8	posedge CLKB	189	189	189	93	93	93
ADB9	posedge CLKB	189	189	189	93	93	93
CEA	posedge CLKA	184	184	184	61	61	61
CEB	posedge CLKB	298	298	298	65	65	65
CSA0	posedge CLKA	24	24	24	178	178	178
CSA1	posedge CLKA	24	24	24	178	178	178
CSA2	posedge CLKA	24	24	24	178	178	178
CSB0	posedge CLKB	0	0	0	350	350	350
CSB1	posedge CLKB	0	0	0	350	350	350
CSB2	posedge CLKB	0	0	0	350	350	350
DIA0	posedge CLKA	198	198	198	28	28	28
DIA1	posedge CLKA	198	198	198	28	28	28
DIA10	posedge CLKA	198	198	198	28	28	28
DIA11	posedge CLKA	198	198	198	28	28	28
DIA12	posedge CLKA	198	198	198	28	28	28
DIA13	posedge CLKA	198	198	198	28	28	28
DIA14	posedge CLKA	198	198	198	28	28	28
DIA15	posedge CLKA	198	198	198	28	28	28
DIA16	posedge CLKA	198	198	198	28	28	28
DIA17	posedge CLKA	198	198	198	28	28	28
DIA2	posedge CLKA	198	198	198	28	28	28
DIA3	posedge CLKA	198	198	198	28	28	28
DIA4	posedge CLKA	198	198	198	28	28	28
DIA5	posedge CLKA	198	198	198	28	28	28
DIA6	posedge CLKA	198	198	198	28	28	28
DIA7	posedge CLKA	198	198	198	28	28	28
DIA8	posedge CLKA	198	198	198	28	28	28
DIA9	posedge CLKA	198	198	198	28	28	28
DIB0	posedge CLKB	132	132	132	228	228	228
DIB1	posedge CLKB	132	132	132	228	228	228
DIB10	posedge CLKB	132	132	132	228	228	228
DIB11	posedge CLKB	132	132	132	228	228	228
DIB12	posedge CLKB	132	132	132	228	228	228
DIB13	posedge CLKB	132	132	132	228	228	228
DIB14	posedge CLKB	132	132	132	228	228	228
DIB15	posedge CLKB	132	132	132	228	228	228
DIB16	posedge CLKB	132	132	132	228	228	228
DIB17	posedge CLKB	132	132	132	228	228	228
DIB2	posedge CLKB	132	132	132	228	228	228
DIB3	posedge CLKB	132	132	132	228	228	228
DIB4	posedge CLKB	132	132	132	228	228	228
DIB5	posedge CLKB	132	132	132	228	228	228
DIB6	posedge CLKB	132	132	132	228	228	228
DIB7	posedge CLKB	132	132	132	228	228	228
DIB8	posedge CLKB	132	132	132	228	228	228
DIB9	posedge CLKB	132	132	132	228	228	228
OCEA	posedge CLKA	207	207	207	0	0	0
OCEB	posedge CLKB	225	225	225	0	0	0
RSTA	posedge CLKA	511	511	511	0	0	0
RSTB	posedge CLKB	518	518	518	0	0	0
WEA	posedge CLKA	134	134	134	95	95	95
WEB	posedge CLKB	0	0	0	357	357	357

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1967	1967	1967	254	254	254
negedge CLKB	1967	1967	1967	254	254	254
posedge CLKA	1967	1967	1967	254	254	254
posedge CLKB	1967	1967	1967	254	254	254

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4804	4829	4854	4804	4829	4854
CLKA	DOA1	4804	4829	4854	4804	4829	4854
CLKA	DOA10	4804	4829	4854	4804	4829	4854
CLKA	DOA11	4804	4829	4854	4804	4829	4854
CLKA	DOA12	4804	4829	4854	4804	4829	4854
CLKA	DOA13	4804	4829	4854	4804	4829	4854
CLKA	DOA14	4804	4829	4854	4804	4829	4854
CLKA	DOA15	4804	4829	4854	4804	4829	4854
CLKA	DOA16	4804	4829	4854	4804	4829	4854
CLKA	DOA17	4804	4829	4854	4804	4829	4854
CLKA	DOA2	4804	4829	4854	4804	4829	4854
CLKA	DOA3	4804	4829	4854	4804	4829	4854
CLKA	DOA4	4804	4829	4854	4804	4829	4854
CLKA	DOA5	4804	4829	4854	4804	4829	4854
CLKA	DOA6	4804	4829	4854	4804	4829	4854
CLKA	DOA7	4804	4829	4854	4804	4829	4854
CLKA	DOA8	4804	4829	4854	4804	4829	4854
CLKA	DOA9	4804	4829	4854	4804	4829	4854
CLKB	DOB0	781	809	837	781	809	837
CLKB	DOB1	781	809	837	781	809	837
CLKB	DOB10	781	809	837	781	809	837
CLKB	DOB11	781	809	837	781	809	837
CLKB	DOB12	781	809	837	781	809	837
CLKB	DOB13	781	809	837	781	809	837
CLKB	DOB14	781	809	837	781	809	837
CLKB	DOB15	781	809	837	781	809	837
CLKB	DOB16	781	809	837	781	809	837
CLKB	DOB17	781	809	837	781	809	837
CLKB	DOB2	781	809	837	781	809	837
CLKB	DOB3	781	809	837	781	809	837
CLKB	DOB4	781	809	837	781	809	837
CLKB	DOB5	781	809	837	781	809	837
CLKB	DOB6	781	809	837	781	809	837
CLKB	DOB7	781	809	837	781	809	837
CLKB	DOB8	781	809	837	781	809	837
CLKB	DOB9	781	809	837	781	809	837

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	226	226	226	3	3	3
ADA1	posedge CLKA	226	226	226	3	3	3
ADA10	posedge CLKA	226	226	226	3	3	3
ADA11	posedge CLKA	226	226	226	3	3	3
ADA12	posedge CLKA	226	226	226	3	3	3
ADA13	posedge CLKA	226	226	226	3	3	3
ADA2	posedge CLKA	226	226	226	3	3	3
ADA3	posedge CLKA	226	226	226	3	3	3
ADA4	posedge CLKA	226	226	226	3	3	3
ADA5	posedge CLKA	226	226	226	3	3	3
ADA6	posedge CLKA	226	226	226	3	3	3
ADA7	posedge CLKA	226	226	226	3	3	3
ADA8	posedge CLKA	226	226	226	3	3	3
ADA9	posedge CLKA	226	226	226	3	3	3
ADB0	posedge CLKB	189	189	189	93	93	93
ADB1	posedge CLKB	189	189	189	93	93	93
ADB10	posedge CLKB	189	189	189	93	93	93
ADB11	posedge CLKB	189	189	189	93	93	93
ADB12	posedge CLKB	189	189	189	93	93	93
ADB13	posedge CLKB	189	189	189	93	93	93
ADB2	posedge CLKB	189	189	189	93	93	93
ADB3	posedge CLKB	189	189	189	93	93	93
ADB4	posedge CLKB	189	189	189	93	93	93
ADB5	posedge CLKB	189	189	189	93	93	93
ADB6	posedge CLKB	189	189	189	93	93	93
ADB7	posedge CLKB	189	189	189	93	93	93
ADB8	posedge CLKB	189	189	189	93	93	93
ADB9	posedge CLKB	189	189	189	93	93	93
CEA	posedge CLKA	184	184	184	61	61	61
CEB	posedge CLKB	298	298	298	65	65	65
CSA0	posedge CLKA	24	24	24	178	178	178
CSA1	posedge CLKA	24	24	24	178	178	178
CSA2	posedge CLKA	24	24	24	178	178	178
CSB0	posedge CLKB	0	0	0	350	350	350
CSB1	posedge CLKB	0	0	0	350	350	350
CSB2	posedge CLKB	0	0	0	350	350	350
DIA0	posedge CLKA	198	198	198	28	28	28
DIA1	posedge CLKA	198	198	198	28	28	28
DIA10	posedge CLKA	198	198	198	28	28	28
DIA11	posedge CLKA	198	198	198	28	28	28
DIA12	posedge CLKA	198	198	198	28	28	28
DIA13	posedge CLKA	198	198	198	28	28	28
DIA14	posedge CLKA	198	198	198	28	28	28
DIA15	posedge CLKA	198	198	198	28	28	28
DIA16	posedge CLKA	198	198	198	28	28	28
DIA17	posedge CLKA	198	198	198	28	28	28
DIA2	posedge CLKA	198	198	198	28	28	28
DIA3	posedge CLKA	198	198	198	28	28	28
DIA4	posedge CLKA	198	198	198	28	28	28
DIA5	posedge CLKA	198	198	198	28	28	28
DIA6	posedge CLKA	198	198	198	28	28	28
DIA7	posedge CLKA	198	198	198	28	28	28
DIA8	posedge CLKA	198	198	198	28	28	28
DIA9	posedge CLKA	198	198	198	28	28	28
DIB0	posedge CLKB	132	132	132	228	228	228
DIB1	posedge CLKB	132	132	132	228	228	228
DIB10	posedge CLKB	132	132	132	228	228	228
DIB11	posedge CLKB	132	132	132	228	228	228
DIB12	posedge CLKB	132	132	132	228	228	228
DIB13	posedge CLKB	132	132	132	228	228	228
DIB14	posedge CLKB	132	132	132	228	228	228
DIB15	posedge CLKB	132	132	132	228	228	228
DIB16	posedge CLKB	132	132	132	228	228	228
DIB17	posedge CLKB	132	132	132	228	228	228
DIB2	posedge CLKB	132	132	132	228	228	228
DIB3	posedge CLKB	132	132	132	228	228	228
DIB4	posedge CLKB	132	132	132	228	228	228
DIB5	posedge CLKB	132	132	132	228	228	228
DIB6	posedge CLKB	132	132	132	228	228	228
DIB7	posedge CLKB	132	132	132	228	228	228
DIB8	posedge CLKB	132	132	132	228	228	228
DIB9	posedge CLKB	132	132	132	228	228	228
OCEA	posedge CLKA	207	207	207	0	0	0
OCEB	posedge CLKB	225	225	225	0	0	0
RSTA	posedge CLKA	511	511	511	0	0	0
RSTB	posedge CLKB	517	517	517	0	0	0
WEA	posedge CLKA	134	134	134	95	95	95
WEB	posedge CLKB	0	0	0	357	357	357

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1967	1967	1967	254	254	254
negedge CLKB	1967	1967	1967	254	254	254
posedge CLKA	1967	1967	1967	254	254	254
posedge CLKB	1967	1967	1967	254	254	254

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	800	828	856	800	828	856
CLKA	DOA1	800	828	856	800	828	856
CLKA	DOA10	800	828	856	800	828	856
CLKA	DOA11	800	828	856	800	828	856
CLKA	DOA12	800	828	856	800	828	856
CLKA	DOA13	800	828	856	800	828	856
CLKA	DOA14	800	828	856	800	828	856
CLKA	DOA15	800	828	856	800	828	856
CLKA	DOA16	800	828	856	800	828	856
CLKA	DOA17	800	828	856	800	828	856
CLKA	DOA2	800	828	856	800	828	856
CLKA	DOA3	800	828	856	800	828	856
CLKA	DOA4	800	828	856	800	828	856
CLKA	DOA5	800	828	856	800	828	856
CLKA	DOA6	800	828	856	800	828	856
CLKA	DOA7	800	828	856	800	828	856
CLKA	DOA8	800	828	856	800	828	856
CLKA	DOA9	800	828	856	800	828	856
CLKB	DOB0	5020	5033	5046	5020	5033	5046
CLKB	DOB1	5020	5033	5046	5020	5033	5046
CLKB	DOB10	5020	5033	5046	5020	5033	5046
CLKB	DOB11	5020	5033	5046	5020	5033	5046
CLKB	DOB12	5020	5033	5046	5020	5033	5046
CLKB	DOB13	5020	5033	5046	5020	5033	5046
CLKB	DOB14	5020	5033	5046	5020	5033	5046
CLKB	DOB15	5020	5033	5046	5020	5033	5046
CLKB	DOB16	5020	5033	5046	5020	5033	5046
CLKB	DOB17	5020	5033	5046	5020	5033	5046
CLKB	DOB2	5020	5033	5046	5020	5033	5046
CLKB	DOB3	5020	5033	5046	5020	5033	5046
CLKB	DOB4	5020	5033	5046	5020	5033	5046
CLKB	DOB5	5020	5033	5046	5020	5033	5046
CLKB	DOB6	5020	5033	5046	5020	5033	5046
CLKB	DOB7	5020	5033	5046	5020	5033	5046
CLKB	DOB8	5020	5033	5046	5020	5033	5046
CLKB	DOB9	5020	5033	5046	5020	5033	5046

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	226	226	226	3	3	3
ADA1	posedge CLKA	226	226	226	3	3	3
ADA10	posedge CLKA	226	226	226	3	3	3
ADA11	posedge CLKA	226	226	226	3	3	3
ADA12	posedge CLKA	226	226	226	3	3	3
ADA13	posedge CLKA	226	226	226	3	3	3
ADA2	posedge CLKA	226	226	226	3	3	3
ADA3	posedge CLKA	226	226	226	3	3	3
ADA4	posedge CLKA	226	226	226	3	3	3
ADA5	posedge CLKA	226	226	226	3	3	3
ADA6	posedge CLKA	226	226	226	3	3	3
ADA7	posedge CLKA	226	226	226	3	3	3
ADA8	posedge CLKA	226	226	226	3	3	3
ADA9	posedge CLKA	226	226	226	3	3	3
ADB0	posedge CLKB	189	189	189	93	93	93
ADB1	posedge CLKB	189	189	189	93	93	93
ADB10	posedge CLKB	189	189	189	93	93	93
ADB11	posedge CLKB	189	189	189	93	93	93
ADB12	posedge CLKB	189	189	189	93	93	93
ADB13	posedge CLKB	189	189	189	93	93	93
ADB2	posedge CLKB	189	189	189	93	93	93
ADB3	posedge CLKB	189	189	189	93	93	93
ADB4	posedge CLKB	189	189	189	93	93	93
ADB5	posedge CLKB	189	189	189	93	93	93
ADB6	posedge CLKB	189	189	189	93	93	93
ADB7	posedge CLKB	189	189	189	93	93	93
ADB8	posedge CLKB	189	189	189	93	93	93
ADB9	posedge CLKB	189	189	189	93	93	93
CEA	posedge CLKA	184	184	184	61	61	61
CEB	posedge CLKB	298	298	298	65	65	65
CSA0	posedge CLKA	24	24	24	178	178	178
CSA1	posedge CLKA	24	24	24	178	178	178
CSA2	posedge CLKA	24	24	24	178	178	178
CSB0	posedge CLKB	0	0	0	350	350	350
CSB1	posedge CLKB	0	0	0	350	350	350
CSB2	posedge CLKB	0	0	0	350	350	350
DIA0	posedge CLKA	198	198	198	28	28	28
DIA1	posedge CLKA	198	198	198	28	28	28
DIA10	posedge CLKA	198	198	198	28	28	28
DIA11	posedge CLKA	198	198	198	28	28	28
DIA12	posedge CLKA	198	198	198	28	28	28
DIA13	posedge CLKA	198	198	198	28	28	28
DIA14	posedge CLKA	198	198	198	28	28	28
DIA15	posedge CLKA	198	198	198	28	28	28
DIA16	posedge CLKA	198	198	198	28	28	28
DIA17	posedge CLKA	198	198	198	28	28	28
DIA2	posedge CLKA	198	198	198	28	28	28
DIA3	posedge CLKA	198	198	198	28	28	28
DIA4	posedge CLKA	198	198	198	28	28	28
DIA5	posedge CLKA	198	198	198	28	28	28
DIA6	posedge CLKA	198	198	198	28	28	28
DIA7	posedge CLKA	198	198	198	28	28	28
DIA8	posedge CLKA	198	198	198	28	28	28
DIA9	posedge CLKA	198	198	198	28	28	28
DIB0	posedge CLKB	132	132	132	228	228	228
DIB1	posedge CLKB	132	132	132	228	228	228
DIB10	posedge CLKB	132	132	132	228	228	228
DIB11	posedge CLKB	132	132	132	228	228	228
DIB12	posedge CLKB	132	132	132	228	228	228
DIB13	posedge CLKB	132	132	132	228	228	228
DIB14	posedge CLKB	132	132	132	228	228	228
DIB15	posedge CLKB	132	132	132	228	228	228
DIB16	posedge CLKB	132	132	132	228	228	228
DIB17	posedge CLKB	132	132	132	228	228	228
DIB2	posedge CLKB	132	132	132	228	228	228
DIB3	posedge CLKB	132	132	132	228	228	228
DIB4	posedge CLKB	132	132	132	228	228	228
DIB5	posedge CLKB	132	132	132	228	228	228
DIB6	posedge CLKB	132	132	132	228	228	228
DIB7	posedge CLKB	132	132	132	228	228	228
DIB8	posedge CLKB	132	132	132	228	228	228
DIB9	posedge CLKB	132	132	132	228	228	228
OCEA	posedge CLKA	207	207	207	0	0	0
OCEB	posedge CLKB	225	225	225	0	0	0
RSTA	posedge CLKA	510	510	510	0	0	0
RSTB	posedge CLKB	518	518	518	0	0	0
WEA	posedge CLKA	134	134	134	95	95	95
WEB	posedge CLKB	0	0	0	357	357	357

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1967	1967	1967	254	254	254
negedge CLKB	1967	1967	1967	254	254	254
posedge CLKA	1967	1967	1967	254	254	254
posedge CLKB	1967	1967	1967	254	254	254

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	800	828	856	800	828	856
CLKA	DOA1	800	828	856	800	828	856
CLKA	DOA10	800	828	856	800	828	856
CLKA	DOA11	800	828	856	800	828	856
CLKA	DOA12	800	828	856	800	828	856
CLKA	DOA13	800	828	856	800	828	856
CLKA	DOA14	800	828	856	800	828	856
CLKA	DOA15	800	828	856	800	828	856
CLKA	DOA16	800	828	856	800	828	856
CLKA	DOA17	800	828	856	800	828	856
CLKA	DOA2	800	828	856	800	828	856
CLKA	DOA3	800	828	856	800	828	856
CLKA	DOA4	800	828	856	800	828	856
CLKA	DOA5	800	828	856	800	828	856
CLKA	DOA6	800	828	856	800	828	856
CLKA	DOA7	800	828	856	800	828	856
CLKA	DOA8	800	828	856	800	828	856
CLKA	DOA9	800	828	856	800	828	856
CLKB	DOB0	781	809	837	781	809	837
CLKB	DOB1	781	809	837	781	809	837
CLKB	DOB10	781	809	837	781	809	837
CLKB	DOB11	781	809	837	781	809	837
CLKB	DOB12	781	809	837	781	809	837
CLKB	DOB13	781	809	837	781	809	837
CLKB	DOB14	781	809	837	781	809	837
CLKB	DOB15	781	809	837	781	809	837
CLKB	DOB16	781	809	837	781	809	837
CLKB	DOB17	781	809	837	781	809	837
CLKB	DOB2	781	809	837	781	809	837
CLKB	DOB3	781	809	837	781	809	837
CLKB	DOB4	781	809	837	781	809	837
CLKB	DOB5	781	809	837	781	809	837
CLKB	DOB6	781	809	837	781	809	837
CLKB	DOB7	781	809	837	781	809	837
CLKB	DOB8	781	809	837	781	809	837
CLKB	DOB9	781	809	837	781	809	837

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	226	226	226	3	3	3
ADA1	posedge CLKA	226	226	226	3	3	3
ADA10	posedge CLKA	226	226	226	3	3	3
ADA11	posedge CLKA	226	226	226	3	3	3
ADA12	posedge CLKA	226	226	226	3	3	3
ADA13	posedge CLKA	226	226	226	3	3	3
ADA2	posedge CLKA	226	226	226	3	3	3
ADA3	posedge CLKA	226	226	226	3	3	3
ADA4	posedge CLKA	226	226	226	3	3	3
ADA5	posedge CLKA	226	226	226	3	3	3
ADA6	posedge CLKA	226	226	226	3	3	3
ADA7	posedge CLKA	226	226	226	3	3	3
ADA8	posedge CLKA	226	226	226	3	3	3
ADA9	posedge CLKA	226	226	226	3	3	3
ADB0	posedge CLKB	189	189	189	93	93	93
ADB1	posedge CLKB	189	189	189	93	93	93
ADB10	posedge CLKB	189	189	189	93	93	93
ADB11	posedge CLKB	189	189	189	93	93	93
ADB12	posedge CLKB	189	189	189	93	93	93
ADB13	posedge CLKB	189	189	189	93	93	93
ADB2	posedge CLKB	189	189	189	93	93	93
ADB3	posedge CLKB	189	189	189	93	93	93
ADB4	posedge CLKB	189	189	189	93	93	93
ADB5	posedge CLKB	189	189	189	93	93	93
ADB6	posedge CLKB	189	189	189	93	93	93
ADB7	posedge CLKB	189	189	189	93	93	93
ADB8	posedge CLKB	189	189	189	93	93	93
ADB9	posedge CLKB	189	189	189	93	93	93
CEA	posedge CLKA	184	184	184	61	61	61
CEB	posedge CLKB	298	298	298	65	65	65
CSA0	posedge CLKA	24	24	24	178	178	178
CSA1	posedge CLKA	24	24	24	178	178	178
CSA2	posedge CLKA	24	24	24	178	178	178
CSB0	posedge CLKB	0	0	0	350	350	350
CSB1	posedge CLKB	0	0	0	350	350	350
CSB2	posedge CLKB	0	0	0	350	350	350
DIA0	posedge CLKA	198	198	198	28	28	28
DIA1	posedge CLKA	198	198	198	28	28	28
DIA10	posedge CLKA	198	198	198	28	28	28
DIA11	posedge CLKA	198	198	198	28	28	28
DIA12	posedge CLKA	198	198	198	28	28	28
DIA13	posedge CLKA	198	198	198	28	28	28
DIA14	posedge CLKA	198	198	198	28	28	28
DIA15	posedge CLKA	198	198	198	28	28	28
DIA16	posedge CLKA	198	198	198	28	28	28
DIA17	posedge CLKA	198	198	198	28	28	28
DIA2	posedge CLKA	198	198	198	28	28	28
DIA3	posedge CLKA	198	198	198	28	28	28
DIA4	posedge CLKA	198	198	198	28	28	28
DIA5	posedge CLKA	198	198	198	28	28	28
DIA6	posedge CLKA	198	198	198	28	28	28
DIA7	posedge CLKA	198	198	198	28	28	28
DIA8	posedge CLKA	198	198	198	28	28	28
DIA9	posedge CLKA	198	198	198	28	28	28
DIB0	posedge CLKB	132	132	132	228	228	228
DIB1	posedge CLKB	132	132	132	228	228	228
DIB10	posedge CLKB	132	132	132	228	228	228
DIB11	posedge CLKB	132	132	132	228	228	228
DIB12	posedge CLKB	132	132	132	228	228	228
DIB13	posedge CLKB	132	132	132	228	228	228
DIB14	posedge CLKB	132	132	132	228	228	228
DIB15	posedge CLKB	132	132	132	228	228	228
DIB16	posedge CLKB	132	132	132	228	228	228
DIB17	posedge CLKB	132	132	132	228	228	228
DIB2	posedge CLKB	132	132	132	228	228	228
DIB3	posedge CLKB	132	132	132	228	228	228
DIB4	posedge CLKB	132	132	132	228	228	228
DIB5	posedge CLKB	132	132	132	228	228	228
DIB6	posedge CLKB	132	132	132	228	228	228
DIB7	posedge CLKB	132	132	132	228	228	228
DIB8	posedge CLKB	132	132	132	228	228	228
DIB9	posedge CLKB	132	132	132	228	228	228
OCEA	posedge CLKA	207	207	207	0	0	0
OCEB	posedge CLKB	225	225	225	0	0	0
RSTA	posedge CLKA	510	510	510	0	0	0
RSTB	posedge CLKB	517	517	517	0	0	0
WEA	posedge CLKA	134	134	134	95	95	95
WEB	posedge CLKB	0	0	0	357	357	357

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1967	1967	1967	254	254	254
negedge CLKB	1967	1967	1967	254	254	254
posedge CLKA	1967	1967	1967	254	254	254
posedge CLKB	1967	1967	1967	254	254	254

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4804	4829	4854	4804	4829	4854
CLKA	DOA1	4804	4829	4854	4804	4829	4854
CLKA	DOA10	4804	4829	4854	4804	4829	4854
CLKA	DOA11	4804	4829	4854	4804	4829	4854
CLKA	DOA12	4804	4829	4854	4804	4829	4854
CLKA	DOA13	4804	4829	4854	4804	4829	4854
CLKA	DOA14	4804	4829	4854	4804	4829	4854
CLKA	DOA15	4804	4829	4854	4804	4829	4854
CLKA	DOA16	4804	4829	4854	4804	4829	4854
CLKA	DOA17	4804	4829	4854	4804	4829	4854
CLKA	DOA2	4804	4829	4854	4804	4829	4854
CLKA	DOA3	4804	4829	4854	4804	4829	4854
CLKA	DOA4	4804	4829	4854	4804	4829	4854
CLKA	DOA5	4804	4829	4854	4804	4829	4854
CLKA	DOA6	4804	4829	4854	4804	4829	4854
CLKA	DOA7	4804	4829	4854	4804	4829	4854
CLKA	DOA8	4804	4829	4854	4804	4829	4854
CLKA	DOA9	4804	4829	4854	4804	4829	4854
CLKB	DOB0	5020	5033	5046	5020	5033	5046
CLKB	DOB1	5020	5033	5046	5020	5033	5046
CLKB	DOB10	5020	5033	5046	5020	5033	5046
CLKB	DOB11	5020	5033	5046	5020	5033	5046
CLKB	DOB12	5020	5033	5046	5020	5033	5046
CLKB	DOB13	5020	5033	5046	5020	5033	5046
CLKB	DOB14	5020	5033	5046	5020	5033	5046
CLKB	DOB15	5020	5033	5046	5020	5033	5046
CLKB	DOB16	5020	5033	5046	5020	5033	5046
CLKB	DOB17	5020	5033	5046	5020	5033	5046
CLKB	DOB2	5020	5033	5046	5020	5033	5046
CLKB	DOB3	5020	5033	5046	5020	5033	5046
CLKB	DOB4	5020	5033	5046	5020	5033	5046
CLKB	DOB5	5020	5033	5046	5020	5033	5046
CLKB	DOB6	5020	5033	5046	5020	5033	5046
CLKB	DOB7	5020	5033	5046	5020	5033	5046
CLKB	DOB8	5020	5033	5046	5020	5033	5046
CLKB	DOB9	5020	5033	5046	5020	5033	5046

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	226	226	226	3	3	3
ADA1	posedge CLKA	226	226	226	3	3	3
ADA10	posedge CLKA	226	226	226	3	3	3
ADA11	posedge CLKA	226	226	226	3	3	3
ADA12	posedge CLKA	226	226	226	3	3	3
ADA13	posedge CLKA	226	226	226	3	3	3
ADA2	posedge CLKA	226	226	226	3	3	3
ADA3	posedge CLKA	226	226	226	3	3	3
ADA4	posedge CLKA	226	226	226	3	3	3
ADA5	posedge CLKA	226	226	226	3	3	3
ADA6	posedge CLKA	226	226	226	3	3	3
ADA7	posedge CLKA	226	226	226	3	3	3
ADA8	posedge CLKA	226	226	226	3	3	3
ADA9	posedge CLKA	226	226	226	3	3	3
ADB0	posedge CLKB	189	189	189	93	93	93
ADB1	posedge CLKB	189	189	189	93	93	93
ADB10	posedge CLKB	189	189	189	93	93	93
ADB11	posedge CLKB	189	189	189	93	93	93
ADB12	posedge CLKB	189	189	189	93	93	93
ADB13	posedge CLKB	189	189	189	93	93	93
ADB2	posedge CLKB	189	189	189	93	93	93
ADB3	posedge CLKB	189	189	189	93	93	93
ADB4	posedge CLKB	189	189	189	93	93	93
ADB5	posedge CLKB	189	189	189	93	93	93
ADB6	posedge CLKB	189	189	189	93	93	93
ADB7	posedge CLKB	189	189	189	93	93	93
ADB8	posedge CLKB	189	189	189	93	93	93
ADB9	posedge CLKB	189	189	189	93	93	93
CEA	posedge CLKA	184	184	184	61	61	61
CEB	posedge CLKB	298	298	298	65	65	65
CSA0	posedge CLKA	24	24	24	178	178	178
CSA1	posedge CLKA	24	24	24	178	178	178
CSA2	posedge CLKA	24	24	24	178	178	178
CSB0	posedge CLKB	0	0	0	350	350	350
CSB1	posedge CLKB	0	0	0	350	350	350
CSB2	posedge CLKB	0	0	0	350	350	350
DIA0	posedge CLKA	198	198	198	28	28	28
DIA1	posedge CLKA	198	198	198	28	28	28
DIA10	posedge CLKA	198	198	198	28	28	28
DIA11	posedge CLKA	198	198	198	28	28	28
DIA12	posedge CLKA	198	198	198	28	28	28
DIA13	posedge CLKA	198	198	198	28	28	28
DIA14	posedge CLKA	198	198	198	28	28	28
DIA15	posedge CLKA	198	198	198	28	28	28
DIA16	posedge CLKA	198	198	198	28	28	28
DIA17	posedge CLKA	198	198	198	28	28	28
DIA2	posedge CLKA	198	198	198	28	28	28
DIA3	posedge CLKA	198	198	198	28	28	28
DIA4	posedge CLKA	198	198	198	28	28	28
DIA5	posedge CLKA	198	198	198	28	28	28
DIA6	posedge CLKA	198	198	198	28	28	28
DIA7	posedge CLKA	198	198	198	28	28	28
DIA8	posedge CLKA	198	198	198	28	28	28
DIA9	posedge CLKA	198	198	198	28	28	28
DIB0	posedge CLKB	132	132	132	228	228	228
DIB1	posedge CLKB	132	132	132	228	228	228
DIB10	posedge CLKB	132	132	132	228	228	228
DIB11	posedge CLKB	132	132	132	228	228	228
DIB12	posedge CLKB	132	132	132	228	228	228
DIB13	posedge CLKB	132	132	132	228	228	228
DIB14	posedge CLKB	132	132	132	228	228	228
DIB15	posedge CLKB	132	132	132	228	228	228
DIB16	posedge CLKB	132	132	132	228	228	228
DIB17	posedge CLKB	132	132	132	228	228	228
DIB2	posedge CLKB	132	132	132	228	228	228
DIB3	posedge CLKB	132	132	132	228	228	228
DIB4	posedge CLKB	132	132	132	228	228	228
DIB5	posedge CLKB	132	132	132	228	228	228
DIB6	posedge CLKB	132	132	132	228	228	228
DIB7	posedge CLKB	132	132	132	228	228	228
DIB8	posedge CLKB	132	132	132	228	228	228
DIB9	posedge CLKB	132	132	132	228	228	228
OCEA	posedge CLKA	207	207	207	0	0	0
OCEB	posedge CLKB	225	225	225	0	0	0
RSTA	posedge CLKA	511	511	511	0	0	0
RSTB	posedge CLKB	518	518	518	0	0	0
WEA	posedge CLKA	134	134	134	95	95	95
WEB	posedge CLKB	0	0	0	357	357	357

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1967	1967	1967	254	254	254
negedge CLKB	1967	1967	1967	254	254	254
posedge CLKA	1967	1967	1967	254	254	254
posedge CLKB	1967	1967	1967	254	254	254

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4804	4829	4854	4804	4829	4854
CLKA	DOA1	4804	4829	4854	4804	4829	4854
CLKA	DOA10	4804	4829	4854	4804	4829	4854
CLKA	DOA11	4804	4829	4854	4804	4829	4854
CLKA	DOA12	4804	4829	4854	4804	4829	4854
CLKA	DOA13	4804	4829	4854	4804	4829	4854
CLKA	DOA14	4804	4829	4854	4804	4829	4854
CLKA	DOA15	4804	4829	4854	4804	4829	4854
CLKA	DOA16	4804	4829	4854	4804	4829	4854
CLKA	DOA17	4804	4829	4854	4804	4829	4854
CLKA	DOA2	4804	4829	4854	4804	4829	4854
CLKA	DOA3	4804	4829	4854	4804	4829	4854
CLKA	DOA4	4804	4829	4854	4804	4829	4854
CLKA	DOA5	4804	4829	4854	4804	4829	4854
CLKA	DOA6	4804	4829	4854	4804	4829	4854
CLKA	DOA7	4804	4829	4854	4804	4829	4854
CLKA	DOA8	4804	4829	4854	4804	4829	4854
CLKA	DOA9	4804	4829	4854	4804	4829	4854
CLKB	DOB0	4982	4986	4990	4982	4986	4990
CLKB	DOB1	4982	4986	4990	4982	4986	4990
CLKB	DOB10	4982	4986	4990	4982	4986	4990
CLKB	DOB11	4982	4986	4990	4982	4986	4990
CLKB	DOB12	4982	4986	4990	4982	4986	4990
CLKB	DOB13	4982	4986	4990	4982	4986	4990
CLKB	DOB14	4982	4986	4990	4982	4986	4990
CLKB	DOB15	4982	4986	4990	4982	4986	4990
CLKB	DOB16	4982	4986	4990	4982	4986	4990
CLKB	DOB17	4982	4986	4990	4982	4986	4990
CLKB	DOB2	4982	4986	4990	4982	4986	4990
CLKB	DOB3	4982	4986	4990	4982	4986	4990
CLKB	DOB4	4982	4986	4990	4982	4986	4990
CLKB	DOB5	4982	4986	4990	4982	4986	4990
CLKB	DOB6	4982	4986	4990	4982	4986	4990
CLKB	DOB7	4982	4986	4990	4982	4986	4990
CLKB	DOB8	4982	4986	4990	4982	4986	4990
CLKB	DOB9	4982	4986	4990	4982	4986	4990

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	226	226	226	3	3	3
ADA1	posedge CLKA	226	226	226	3	3	3
ADA10	posedge CLKA	226	226	226	3	3	3
ADA11	posedge CLKA	226	226	226	3	3	3
ADA12	posedge CLKA	226	226	226	3	3	3
ADA13	posedge CLKA	226	226	226	3	3	3
ADA2	posedge CLKA	226	226	226	3	3	3
ADA3	posedge CLKA	226	226	226	3	3	3
ADA4	posedge CLKA	226	226	226	3	3	3
ADA5	posedge CLKA	226	226	226	3	3	3
ADA6	posedge CLKA	226	226	226	3	3	3
ADA7	posedge CLKA	226	226	226	3	3	3
ADA8	posedge CLKA	226	226	226	3	3	3
ADA9	posedge CLKA	226	226	226	3	3	3
ADB0	posedge CLKB	189	189	189	93	93	93
ADB1	posedge CLKB	189	189	189	93	93	93
ADB10	posedge CLKB	189	189	189	93	93	93
ADB11	posedge CLKB	189	189	189	93	93	93
ADB12	posedge CLKB	189	189	189	93	93	93
ADB13	posedge CLKB	189	189	189	93	93	93
ADB2	posedge CLKB	189	189	189	93	93	93
ADB3	posedge CLKB	189	189	189	93	93	93
ADB4	posedge CLKB	189	189	189	93	93	93
ADB5	posedge CLKB	189	189	189	93	93	93
ADB6	posedge CLKB	189	189	189	93	93	93
ADB7	posedge CLKB	189	189	189	93	93	93
ADB8	posedge CLKB	189	189	189	93	93	93
ADB9	posedge CLKB	189	189	189	93	93	93
CEA	posedge CLKA	184	184	184	61	61	61
CEB	posedge CLKB	298	298	298	65	65	65
CSA0	posedge CLKA	24	24	24	178	178	178
CSA1	posedge CLKA	24	24	24	178	178	178
CSA2	posedge CLKA	24	24	24	178	178	178
CSB0	posedge CLKB	0	0	0	350	350	350
CSB1	posedge CLKB	0	0	0	350	350	350
CSB2	posedge CLKB	0	0	0	350	350	350
DIA0	posedge CLKA	198	198	198	28	28	28
DIA1	posedge CLKA	198	198	198	28	28	28
DIA10	posedge CLKA	198	198	198	28	28	28
DIA11	posedge CLKA	198	198	198	28	28	28
DIA12	posedge CLKA	198	198	198	28	28	28
DIA13	posedge CLKA	198	198	198	28	28	28
DIA14	posedge CLKA	198	198	198	28	28	28
DIA15	posedge CLKA	198	198	198	28	28	28
DIA16	posedge CLKA	198	198	198	28	28	28
DIA17	posedge CLKA	198	198	198	28	28	28
DIA2	posedge CLKA	198	198	198	28	28	28
DIA3	posedge CLKA	198	198	198	28	28	28
DIA4	posedge CLKA	198	198	198	28	28	28
DIA5	posedge CLKA	198	198	198	28	28	28
DIA6	posedge CLKA	198	198	198	28	28	28
DIA7	posedge CLKA	198	198	198	28	28	28
DIA8	posedge CLKA	198	198	198	28	28	28
DIA9	posedge CLKA	198	198	198	28	28	28
DIB0	posedge CLKB	132	132	132	228	228	228
DIB1	posedge CLKB	132	132	132	228	228	228
DIB10	posedge CLKB	132	132	132	228	228	228
DIB11	posedge CLKB	132	132	132	228	228	228
DIB12	posedge CLKB	132	132	132	228	228	228
DIB13	posedge CLKB	132	132	132	228	228	228
DIB14	posedge CLKB	132	132	132	228	228	228
DIB15	posedge CLKB	132	132	132	228	228	228
DIB16	posedge CLKB	132	132	132	228	228	228
DIB17	posedge CLKB	132	132	132	228	228	228
DIB2	posedge CLKB	132	132	132	228	228	228
DIB3	posedge CLKB	132	132	132	228	228	228
DIB4	posedge CLKB	132	132	132	228	228	228
DIB5	posedge CLKB	132	132	132	228	228	228
DIB6	posedge CLKB	132	132	132	228	228	228
DIB7	posedge CLKB	132	132	132	228	228	228
DIB8	posedge CLKB	132	132	132	228	228	228
DIB9	posedge CLKB	132	132	132	228	228	228
OCEA	posedge CLKA	207	207	207	0	0	0
OCEB	posedge CLKB	225	225	225	0	0	0
RSTA	posedge CLKA	511	511	511	0	0	0
RSTB	posedge CLKB	518	518	518	0	0	0
WEA	posedge CLKA	134	134	134	95	95	95
WEB	posedge CLKB	0	0	0	357	357	357

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1967	1967	1967	254	254	254
negedge CLKB	2581	2581	2581	194	194	194
posedge CLKA	1967	1967	1967	254	254	254
posedge CLKB	2581	2581	2581	194	194	194

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	4804	4829	4854	4804	4829	4854
CLKA	DOA1	4804	4829	4854	4804	4829	4854
CLKA	DOA10	4804	4829	4854	4804	4829	4854
CLKA	DOA11	4804	4829	4854	4804	4829	4854
CLKA	DOA12	4804	4829	4854	4804	4829	4854
CLKA	DOA13	4804	4829	4854	4804	4829	4854
CLKA	DOA14	4804	4829	4854	4804	4829	4854
CLKA	DOA15	4804	4829	4854	4804	4829	4854
CLKA	DOA16	4804	4829	4854	4804	4829	4854
CLKA	DOA17	4804	4829	4854	4804	4829	4854
CLKA	DOA2	4804	4829	4854	4804	4829	4854
CLKA	DOA3	4804	4829	4854	4804	4829	4854
CLKA	DOA4	4804	4829	4854	4804	4829	4854
CLKA	DOA5	4804	4829	4854	4804	4829	4854
CLKA	DOA6	4804	4829	4854	4804	4829	4854
CLKA	DOA7	4804	4829	4854	4804	4829	4854
CLKA	DOA8	4804	4829	4854	4804	4829	4854
CLKA	DOA9	4804	4829	4854	4804	4829	4854
CLKB	DOB0	4984	4989	4995	4984	4989	4995
CLKB	DOB1	4984	4989	4995	4984	4989	4995
CLKB	DOB10	4984	4989	4995	4984	4989	4995
CLKB	DOB11	4984	4989	4995	4984	4989	4995
CLKB	DOB12	4984	4989	4995	4984	4989	4995
CLKB	DOB13	4984	4989	4995	4984	4989	4995
CLKB	DOB14	4984	4989	4995	4984	4989	4995
CLKB	DOB15	4984	4989	4995	4984	4989	4995
CLKB	DOB16	4984	4989	4995	4984	4989	4995
CLKB	DOB17	4984	4989	4995	4984	4989	4995
CLKB	DOB2	4984	4989	4995	4984	4989	4995
CLKB	DOB3	4984	4989	4995	4984	4989	4995
CLKB	DOB4	4984	4989	4995	4984	4989	4995
CLKB	DOB5	4984	4989	4995	4984	4989	4995
CLKB	DOB6	4984	4989	4995	4984	4989	4995
CLKB	DOB7	4984	4989	4995	4984	4989	4995
CLKB	DOB8	4984	4989	4995	4984	4989	4995
CLKB	DOB9	4984	4989	4995	4984	4989	4995

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	226	226	226	3	3	3
ADA1	posedge CLKA	226	226	226	3	3	3
ADA10	posedge CLKA	226	226	226	3	3	3
ADA11	posedge CLKA	226	226	226	3	3	3
ADA12	posedge CLKA	226	226	226	3	3	3
ADA13	posedge CLKA	226	226	226	3	3	3
ADA2	posedge CLKA	226	226	226	3	3	3
ADA3	posedge CLKA	226	226	226	3	3	3
ADA4	posedge CLKA	226	226	226	3	3	3
ADA5	posedge CLKA	226	226	226	3	3	3
ADA6	posedge CLKA	226	226	226	3	3	3
ADA7	posedge CLKA	226	226	226	3	3	3
ADA8	posedge CLKA	226	226	226	3	3	3
ADA9	posedge CLKA	226	226	226	3	3	3
ADB0	posedge CLKB	189	189	189	93	93	93
ADB1	posedge CLKB	189	189	189	93	93	93
ADB10	posedge CLKB	189	189	189	93	93	93
ADB11	posedge CLKB	189	189	189	93	93	93
ADB12	posedge CLKB	189	189	189	93	93	93
ADB13	posedge CLKB	189	189	189	93	93	93
ADB2	posedge CLKB	189	189	189	93	93	93
ADB3	posedge CLKB	189	189	189	93	93	93
ADB4	posedge CLKB	189	189	189	93	93	93
ADB5	posedge CLKB	189	189	189	93	93	93
ADB6	posedge CLKB	189	189	189	93	93	93
ADB7	posedge CLKB	189	189	189	93	93	93
ADB8	posedge CLKB	189	189	189	93	93	93
ADB9	posedge CLKB	189	189	189	93	93	93
CEA	posedge CLKA	184	184	184	61	61	61
CEB	posedge CLKB	298	298	298	65	65	65
CSA0	posedge CLKA	24	24	24	178	178	178
CSA1	posedge CLKA	24	24	24	178	178	178
CSA2	posedge CLKA	24	24	24	178	178	178
CSB0	posedge CLKB	0	0	0	350	350	350
CSB1	posedge CLKB	0	0	0	350	350	350
CSB2	posedge CLKB	0	0	0	350	350	350
DIA0	posedge CLKA	198	198	198	28	28	28
DIA1	posedge CLKA	198	198	198	28	28	28
DIA10	posedge CLKA	198	198	198	28	28	28
DIA11	posedge CLKA	198	198	198	28	28	28
DIA12	posedge CLKA	198	198	198	28	28	28
DIA13	posedge CLKA	198	198	198	28	28	28
DIA14	posedge CLKA	198	198	198	28	28	28
DIA15	posedge CLKA	198	198	198	28	28	28
DIA16	posedge CLKA	198	198	198	28	28	28
DIA17	posedge CLKA	198	198	198	28	28	28
DIA2	posedge CLKA	198	198	198	28	28	28
DIA3	posedge CLKA	198	198	198	28	28	28
DIA4	posedge CLKA	198	198	198	28	28	28
DIA5	posedge CLKA	198	198	198	28	28	28
DIA6	posedge CLKA	198	198	198	28	28	28
DIA7	posedge CLKA	198	198	198	28	28	28
DIA8	posedge CLKA	198	198	198	28	28	28
DIA9	posedge CLKA	198	198	198	28	28	28
DIB0	posedge CLKB	132	132	132	228	228	228
DIB1	posedge CLKB	132	132	132	228	228	228
DIB10	posedge CLKB	132	132	132	228	228	228
DIB11	posedge CLKB	132	132	132	228	228	228
DIB12	posedge CLKB	132	132	132	228	228	228
DIB13	posedge CLKB	132	132	132	228	228	228
DIB14	posedge CLKB	132	132	132	228	228	228
DIB15	posedge CLKB	132	132	132	228	228	228
DIB16	posedge CLKB	132	132	132	228	228	228
DIB17	posedge CLKB	132	132	132	228	228	228
DIB2	posedge CLKB	132	132	132	228	228	228
DIB3	posedge CLKB	132	132	132	228	228	228
DIB4	posedge CLKB	132	132	132	228	228	228
DIB5	posedge CLKB	132	132	132	228	228	228
DIB6	posedge CLKB	132	132	132	228	228	228
DIB7	posedge CLKB	132	132	132	228	228	228
DIB8	posedge CLKB	132	132	132	228	228	228
DIB9	posedge CLKB	132	132	132	228	228	228
OCEA	posedge CLKA	207	207	207	0	0	0
OCEB	posedge CLKB	225	225	225	0	0	0
RSTA	posedge CLKA	511	511	511	0	0	0
RSTB	posedge CLKB	518	518	518	0	0	0
WEA	posedge CLKA	134	134	134	95	95	95
WEB	posedge CLKB	0	0	0	357	357	357

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	1967	1967	1967	254	254	254
negedge CLKB	1954	1954	1954	256	256	256
posedge CLKA	1967	1967	1967	254	254	254
posedge CLKB	1954	1954	1954	256	256	256

IOLOGIC:MODE=IDDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	318	318	318	318	318	318
CLK	RXDATA1	318	318	318	318	318	318

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge CLK	353	353	353	215	215	215

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=IDDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	403	403	403	403	403	403
CLK	RXDATA1	403	403	403	403	403	403
CLK	RXDATA2	403	403	403	403	403	403
CLK	RXDATA3	403	403	403	403	403	403

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge ECLK	365	365	365	55	55	55
posedge ECLK	posedge CLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1524	1524	1524	328	328	328
posedge ECLK	1524	1524	1524	328	328	328

IOLOGIC:MODE=IREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	INFF	419	419	419	419	419	419

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	69	69	69
DI	posedge CLK	378	378	378	285	285	285
LSR	posedge CLK	105	105	105	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1648	1648	1648	303	303	303
posedge CLK	1648	1648	1648	303	303	303

IOLOGIC:MODE=ODDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	861	863	865	861	863	865

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=ODDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
ECLK	IOLDO	1131	1136	1141	1131	1136	1141

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
TXDATA0	posedge CLK	103	103	103	0	0	0
TXDATA1	posedge CLK	103	103	103	0	0	0
TXDATA2	posedge CLK	103	103	103	0	0	0
TXDATA3	posedge CLK	103	103	103	0	0	0
posedge CLK	posedge ECLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1425	1425	1425	351	351	351
posedge ECLK	1425	1425	1425	351	351	351

IOLOGIC:MODE=OREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	1109	1109	1109	1109	1109	1109

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	66	66	66
LSR	posedge CLK	117	117	117	0	0	0
TXDATA0	posedge CLK	130	130	130	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1648	1648	1648	303	303	303
posedge CLK	1648	1648	1648	303	303	303

IOLOGIC:MODE=TSREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLTO	898	898	898	898	898	898

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	66	66	66
LSR	posedge CLK	117	117	117	0	0	0
TSDATA0	posedge CLK	180	180	180	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1648	1648	1648	303	303	303
posedge CLK	1648	1648	1648	303	303	303

MULT18X18D:REGS=ALL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	530	593	656	530	593	656

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	37	50	63	0	0	26
B	posedge CLK0	37	50	63	0	0	26
CE0	posedge CLK0	147	189	231	0	0	21
RST0	posedge CLK0	74	89	105	53	63	74
SIGNEDA	posedge CLK0	0	0	0	131	144	158
SIGNEDB	posedge CLK0	0	0	0	131	144	158

MULT18X18D:REGS=INPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	2583	3019	3455	2583	3019	3455

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	37	50	63	0	0	26
B	posedge CLK0	37	50	63	0	0	26
CE0	posedge CLK0	147	189	231	0	0	21
RST0	posedge CLK0	74	89	105	53	63	74
SIGNEDA	posedge CLK0	0	0	0	131	144	158
SIGNEDB	posedge CLK0	0	0	0	131	144	158

MULT18X18D:REGS=NONE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A	P	2620	3058	3497	2620	3058	3497
B	P	2620	3058	3497	2620	3058	3497
SIGNEDA	P	2473	2898	3323	2473	2898	3323
SIGNEDB	P	2473	2898	3323	2473	2898	3323

MULT18X18D:REGS=OUTPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	530	593	656	530	593	656

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	2699	2880	3061	0	0	0
B	posedge CLK0	2699	2880	3061	0	0	0
CE0	posedge CLK0	147	189	231	0	0	21
RST0	posedge CLK0	74	89	105	53	63	74
SIGNEDA	posedge CLK0	2557	2722	2888	0	0	0
SIGNEDB	posedge CLK0	2557	2722	2888	0	0	0

MULT18X18D:REGS=PIPELINE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	1192	1207	1223	1192	1207	1223

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	2121	2213	2305	0	0	0
B	posedge CLK0	2121	2213	2305	0	0	0
CE0	posedge CLK0	147	189	231	0	0	21
RST0	posedge CLK0	74	89	105	53	63	74
SIGNEDA	posedge CLK0	1979	2055	2131	0	0	0
SIGNEDB	posedge CLK0	1979	2055	2131	0	0	0

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	642	669	697	642	669	697
PADDO	PAD	1445	1589	1733	1445	1589	1733
PADDT	PAD	1602	1858	2115	1602	1858	2115

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1586	1604	1622	1586	1604	1622
PADDO	PAD	1469	1619	1769	1469	1619	1769
PADDT	PAD	1598	1790	1982	1598	1790	1982

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1228	1290	1352	1228	1290	1352
PADDO	PAD	1520	1657	1794	1520	1657	1794
PADDT	PAD	1798	1946	2095	1798	1946	2095

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	857	898	940	857	898	940
PADDO	PAD	1841	1842	1844	1841	1842	1844
PADDT	PAD	1792	1921	2050	1792	1921	2050

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	956	1005	1055	956	1005	1055
PADDO	PAD	1903	2168	2433	1903	2168	2433
PADDT	PAD	2158	2470	2783	2158	2470	2783

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	465	466	467	465	466	467
PADDO	PAD	1011	1012	1013	1011	1012	1013

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	428	438	449	428	438	449
PADDO	PAD	1832	1931	2030	1832	1931	2030
PADDT	PAD	1899	2481	3063	1899	2481	3063

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	428	438	449	428	438	449
PADDO	PAD	1746	1817	1888	1746	1817	1888
PADDT	PAD	1727	2492	3257	1727	2492	3257

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	425	436	448	425	436	448
PADDO	PAD	1899	1985	2071	1899	1985	2071
PADDT	PAD	2043	2445	2847	2043	2445	2847

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	425	436	448	425	436	448
PADDO	PAD	1665	1717	1770	1665	1717	1770
PADDT	PAD	1600	2494	3389	1600	2494	3389

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

SCCU2C

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	176	192	208	176	192	208
A0	F1	520	563	607	520	563	607
A0	FCO	160	280	401	160	280	401
A1	F1	176	192	208	176	192	208
A1	FCO	160	280	401	160	280	401
B0	F0	176	192	208	176	192	208
B0	F1	520	563	607	520	563	607
B0	FCO	160	280	401	160	280	401
B1	F1	176	192	208	176	192	208
B1	FCO	160	280	401	160	280	401
C0	F0	176	192	208	176	192	208
C0	F1	520	563	607	520	563	607
C0	FCO	160	280	401	160	280	401
C1	F1	176	192	208	176	192	208
C1	FCO	160	280	401	160	280	401
CLK	Q0	379	419	460	379	419	460
CLK	Q1	378	417	457	378	417	457
D0	F0	176	192	208	176	192	208
D0	F1	520	563	607	520	563	607
D0	FCO	160	280	401	160	280	401
D1	F1	176	192	208	176	192	208
D1	FCO	160	280	401	160	280	401
FCI	F0	211	298	385	211	298	385
FCI	F1	307	359	412	307	359	412
FCI	FCO	56	59	63	56	59	63

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	129	130	132
CE	posedge CLK	0	0	0	129	131	133
DI0	posedge CLK	0	0	0	240	254	268
DI1	posedge CLK	0	0	0	239	253	268
LSR	posedge CLK	229	292	355	0	0	0
LSR	posedge CLK	229	292	356	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1092	1092	1092	458	458	458
negedge LSR	546	546	546	916	916	916
posedge CLK	1092	1092	1092	458	458	458
posedge LSR	546	546	546	916	916	916

SDPRAME

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	Q0	379	419	460	379	419	460
CLK	Q1	378	417	457	378	417	457
RAD0	F0	176	192	208	176	192	208
RAD0	F1	176	192	208	176	192	208
RAD1	F0	176	192	208	176	192	208
RAD1	F1	176	192	208	176	192	208
RAD2	F0	176	192	208	176	192	208
RAD2	F1	176	192	208	176	192	208
RAD3	F0	176	192	208	176	192	208
RAD3	F1	176	192	208	176	192	208
WCK	F0	806	813	820	806	813	820
WCK	F1	809	816	823	809	816	823

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI0	posedge CLK	0	0	0	240	254	268
DI1	posedge CLK	0	0	0	239	253	268
WAD0	posedge WCK	0	0	0	246	280	314
WAD1	posedge WCK	0	0	0	255	287	320
WAD2	posedge WCK	0	0	0	236	272	308
WAD3	posedge WCK	0	0	0	251	284	317
WD0	posedge WCK	0	0	0	185	222	260
WD1	posedge WCK	0	0	0	188	223	259
WRE	posedge WCK	218	273	329	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1092	1092	1092	458	458	458
negedge WCK	546	546	546	916	916	916
posedge CLK	1092	1092	1092	458	458	458
posedge WCK	546	546	546	916	916	916

SLOGICB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	176	192	208	176	192	208
A0	OFX0	234	294	354	234	294	354
A1	F1	176	192	208	176	192	208
A1	OFX0	234	294	354	234	294	354
B0	F0	176	192	208	176	192	208
B0	OFX0	234	294	354	234	294	354
B1	F1	176	192	208	176	192	208
B1	OFX0	234	294	354	234	294	354
C0	F0	176	192	208	176	192	208
C0	OFX0	234	294	354	234	294	354
C1	F1	176	192	208	176	192	208
C1	OFX0	234	294	354	234	294	354
CLK	Q0	379	419	460	379	419	460
CLK	Q1	378	417	457	378	417	457
D0	F0	176	192	208	176	192	208
D0	OFX0	234	294	354	234	294	354
D1	F1	176	192	208	176	192	208
D1	OFX0	234	294	354	234	294	354
FXA	OFX1	166	187	209	166	187	209
FXB	OFX1	166	188	211	166	188	211
M0	OFX0	166	195	225	166	195	225
M1	OFX1	166	193	221	166	193	221

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	129	130	132
CE	posedge CLK	0	0	0	129	131	133
DI0	posedge CLK	0	0	0	240	254	268
DI1	posedge CLK	0	0	0	239	253	268
LSR	posedge CLK	229	292	356	0	0	0
M0	posedge CLK	0	0	0	215	241	268
M1	posedge CLK	0	0	0	215	242	269

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1092	1092	1092	458	458	458
negedge LSR	546	546	546	916	916	916
posedge CLK	1092	1092	1092	458	458	458
posedge LSR	546	546	546	916	916	916

SRAMWB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	WADO3	0	0	0	0	0	0
A1	WDO1	0	0	0	0	0	0
B0	WADO1	0	0	0	0	0	0
B1	WDO3	0	0	0	0	0	0
C0	WADO2	0	0	0	0	0	0
C1	WDO0	0	0	0	0	0	0
D0	WADO0	0	0	0	0	0	0
D1	WDO2	0	0	0	0	0	0

ECP5 Speed Grade -7 Cell Timings

Contents

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX1F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=ODDRX1F

Propagation Delays

Width Checks

IOLOGIC:MODE=ODDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=OREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=TSREG

Propagation Delays

Setup/Hold Checks

Width Checks

MULT18X18D:REGS=ALL

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=INPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=NONE

Propagation Delays

MULT18X18D:REGS=OUTPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=PIPELINE

Propagation Delays

Setup/Hold Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks