ECP5 Speed Grade -6 Cell Timings

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG
DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE
DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH
IOLOGIC:MODE=IDDRX1F
IOLOGIC:MODE=IDDRX2F
IOLOGIC:MODE=IREG
IOLOGIC:MODE=ODDRX1F
IOLOGIC:MODE=ODDRX2F
IOLOGIC:MODE=OREG
IOLOGIC:MODE=TSREG
MULT18X18D:REGS=ALL
MULT18X18D:REGS=INPUT
MULT18X18D:REGS=NONE
MULT18X18D:REGS=OUTPUT
MULT18X18D:REGS=PIPELINE
PIO:IOTYPE=LVCMOS12
PIO:IOTYPE=LVCMOS15
PIO:IOTYPE=LVCMOS18
PIO:IOTYPE=LVCMOS25
PIO:IOTYPE=LVCMOS33
PIO:IOTYPE=LVDS
PIO:IOTYPE=SSTL15_I
PIO:IOTYPE=SSTL15_II
PIO:IOTYPE=SSTL18_I
PIO:IOTYPE=SSTL18_II
SCCU2C
SDPRAME
SLOGICB
SRAMWB

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	5535	5572	5609	5535	5572	5609
CLKA	DOA1	5535	5572	5609	5535	5572	5609
CLKA	DOA10	5535	5572	5609	5535	5572	5609
CLKA	DOA11	5535	5572	5609	5535	5572	5609
CLKA	DOA12	5535	5572	5609	5535	5572	5609
CLKA	DOA13	5535	5572	5609	5535	5572	5609
CLKA	DOA14	5535	5572	5609	5535	5572	5609
CLKA	DOA15	5535	5572	5609	5535	5572	5609
CLKA	DOA16	5535	5572	5609	5535	5572	5609
CLKA	DOA17	5535	5572	5609	5535	5572	5609
CLKA	DOA2	5535	5572	5609	5535	5572	5609
CLKA	DOA3	5535	5572	5609	5535	5572	5609
CLKA	DOA4	5535	5572	5609	5535	5572	5609
CLKA	DOA5	5535	5572	5609	5535	5572	5609
CLKA	DOA6	5535	5572	5609	5535	5572	5609
CLKA	DOA7	5535	5572	5609	5535	5572	5609
CLKA	DOA8	5535	5572	5609	5535	5572	5609
CLKA	DOA9	5535	5572	5609	5535	5572	5609
CLKB	DOB0	5795	5812	5830	5795	5812	5830
CLKB	DOB1	5795	5812	5830	5795	5812	5830
CLKB	DOB10	5795	5812	5830	5795	5812	5830
CLKB	DOB11	5795	5812	5830	5795	5812	5830
CLKB	DOB12	5795	5812	5830	5795	5812	5830
CLKB	DOB13	5795	5812	5830	5795	5812	5830
CLKB	DOB14	5795	5812	5830	5795	5812	5830
CLKB	DOB15	5795	5812	5830	5795	5812	5830
CLKB	DOB16	5795	5812	5830	5795	5812	5830
CLKB	DOB17	5795	5812	5830	5795	5812	5830
CLKB	DOB2	5795	5812	5830	5795	5812	5830
CLKB	DOB3	5795	5812	5830	5795	5812	5830
CLKB	DOB4	5795	5812	5830	5795	5812	5830
CLKB	DOB5	5795	5812	5830	5795	5812	5830
CLKB	DOB6	5795	5812	5830	5795	5812	5830
CLKB	DOB7	5795	5812	5830	5795	5812	5830
CLKB	DOB8	5795	5812	5830	5795	5812	5830
CLKB	DOB9	5795	5812	5830	5795	5812	5830

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	251	251	251	1	1	1
ADA1	posedge CLKA	251	251	251	1	1	1
ADA10	posedge CLKA	251	251	251	1	1	1
ADA11	posedge CLKA	251	251	251	1	1	1
ADA12	posedge CLKA	251	251	251	1	1	1
ADA13	posedge CLKA	251	251	251	1	1	1
ADA2	posedge CLKA	251	251	251	1	1	1
ADA3	posedge CLKA	251	251	251	1	1	1
ADA4	posedge CLKA	251	251	251	1	1	1
ADA5	posedge CLKA	251	251	251	1	1	1
ADA6	posedge CLKA	251	251	251	1	1	1
ADA7	posedge CLKA	251	251	251	1	1	1
ADA8	posedge CLKA	251	251	251	1	1	1
ADA9	posedge CLKA	251	251	251	1	1	1
ADB0	posedge CLKB	205	205	205	101	101	101
ADB1	posedge CLKB	205	205	205	101	101	101
ADB10	posedge CLKB	205	205	205	101	101	101
ADB11	posedge CLKB	205	205	205	101	101	101
ADB12	posedge CLKB	205	205	205	101	101	101
ADB13	posedge CLKB	205	205	205	101	101	101
ADB2	posedge CLKB	205	205	205	101	101	101
ADB3	posedge CLKB	205	205	205	101	101	101
ADB4	posedge CLKB	205	205	205	101	101	101
ADB5	posedge CLKB	205	205	205	101	101	101
ADB6	posedge CLKB	205	205	205	101	101	101
ADB7	posedge CLKB	205	205	205	101	101	101
ADB8	posedge CLKB	205	205	205	101	101	101
ADB9	posedge CLKB	205	205	205	101	101	101
CEA	posedge CLKA	211	211	211	47	47	47
CEB	posedge CLKB	340	340	340	60	60	60
CSA0	posedge CLKA	20	20	20	202	202	202
CSA1	posedge CLKA	20	20	20	202	202	202
CSA2	posedge CLKA	20	20	20	202	202	202
CSB0	posedge CLKB	0	0	0	404	404	404
CSB1	posedge CLKB	0	0	0	404	404	404
CSB2	posedge CLKB	0	0	0	404	404	404
DIA0	posedge CLKA	218	218	218	25	25	25
DIA1	posedge CLKA	218	218	218	25	25	25
DIA10	posedge CLKA	218	218	218	25	25	25
DIA11	posedge CLKA	218	218	218	25	25	25
DIA12	posedge CLKA	218	218	218	25	25	25
DIA13	posedge CLKA	218	218	218	25	25	25
DIA14	posedge CLKA	218	218	218	25	25	25
DIA15	posedge CLKA	218	218	218	25	25	25
DIA16	posedge CLKA	218	218	218	25	25	25
DIA17	posedge CLKA	218	218	218	25	25	25
DIA2	posedge CLKA	218	218	218	25	25	25
DIA3	posedge CLKA	218	218	218	25	25	25
DIA4	posedge CLKA	218	218	218	25	25	25
DIA5	posedge CLKA	218	218	218	25	25	25
DIA6	posedge CLKA	218	218	218	25	25	25
DIA7	posedge CLKA	218	218	218	25	25	25
DIA8	posedge CLKA	218	218	218	25	25	25
DIA9	posedge CLKA	218	218	218	25	25	25
DIB0	posedge CLKB	134	134	134	259	259	259
DIB1	posedge CLKB	134	134	134	259	259	259
DIB10	posedge CLKB	134	134	134	259	259	259
DIB11	posedge CLKB	134	134	134	259	259	259
DIB12	posedge CLKB	134	134	134	259	259	259
DIB13	posedge CLKB	134	134	134	259	259	259
DIB14	posedge CLKB	134	134	134	259	259	259
DIB15	posedge CLKB	134	134	134	259	259	259
DIB16	posedge CLKB	134	134	134	259	259	259
DIB17	posedge CLKB	134	134	134	259	259	259
DIB2	posedge CLKB	134	134	134	259	259	259
DIB3	posedge CLKB	134	134	134	259	259	259
DIB4	posedge CLKB	134	134	134	259	259	259
DIB5	posedge CLKB	134	134	134	259	259	259
DIB6	posedge CLKB	134	134	134	259	259	259
DIB7	posedge CLKB	134	134	134	259	259	259
DIB8	posedge CLKB	134	134	134	259	259	259
DIB9	posedge CLKB	134	134	134	259	259	259
OCEA	posedge CLKA	226	226	226	0	0	0
OCEB	posedge CLKB	253	253	253	0	0	0
RSTA	posedge CLKA	579	579	579	0	0	0
RSTB	posedge CLKB	585	585	585	0	0	0
WEA	posedge CLKA	139	139	139	102	102	102
WEB	posedge CLKB	0	0	0	392	392	392

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2359	2359	2359	212	212	212
negedge CLKB	2359	2359	2359	212	212	212
posedge CLKA	2359	2359	2359	212	212	212
posedge CLKB	2359	2359	2359	212	212	212

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	5535	5572	5609	5535	5572	5609
CLKA	DOA1	5535	5572	5609	5535	5572	5609
CLKA	DOA10	5535	5572	5609	5535	5572	5609
CLKA	DOA11	5535	5572	5609	5535	5572	5609
CLKA	DOA12	5535	5572	5609	5535	5572	5609
CLKA	DOA13	5535	5572	5609	5535	5572	5609
CLKA	DOA14	5535	5572	5609	5535	5572	5609
CLKA	DOA15	5535	5572	5609	5535	5572	5609
CLKA	DOA16	5535	5572	5609	5535	5572	5609
CLKA	DOA17	5535	5572	5609	5535	5572	5609
CLKA	DOA2	5535	5572	5609	5535	5572	5609
CLKA	DOA3	5535	5572	5609	5535	5572	5609
CLKA	DOA4	5535	5572	5609	5535	5572	5609
CLKA	DOA5	5535	5572	5609	5535	5572	5609
CLKA	DOA6	5535	5572	5609	5535	5572	5609
CLKA	DOA7	5535	5572	5609	5535	5572	5609
CLKA	DOA8	5535	5572	5609	5535	5572	5609
CLKA	DOA9	5535	5572	5609	5535	5572	5609
CLKB	DOB0	882	919	956	882	919	956
CLKB	DOB1	882	919	956	882	919	956
CLKB	DOB10	882	919	956	882	919	956
CLKB	DOB11	882	919	956	882	919	956
CLKB	DOB12	882	919	956	882	919	956
CLKB	DOB13	882	919	956	882	919	956
CLKB	DOB14	882	919	956	882	919	956
CLKB	DOB15	882	919	956	882	919	956
CLKB	DOB16	882	919	956	882	919	956
CLKB	DOB17	882	919	956	882	919	956
CLKB	DOB2	882	919	956	882	919	956
CLKB	DOB3	882	919	956	882	919	956
CLKB	DOB4	882	919	956	882	919	956
CLKB	DOB5	882	919	956	882	919	956
CLKB	DOB6	882	919	956	882	919	956
CLKB	DOB7	882	919	956	882	919	956
CLKB	DOB8	882	919	956	882	919	956
CLKB	DOB9	882	919	956	882	919	956

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	251	251	251	1	1	1
ADA1	posedge CLKA	251	251	251	1	1	1
ADA10	posedge CLKA	251	251	251	1	1	1
ADA11	posedge CLKA	251	251	251	1	1	1
ADA12	posedge CLKA	251	251	251	1	1	1
ADA13	posedge CLKA	251	251	251	1	1	1
ADA2	posedge CLKA	251	251	251	1	1	1
ADA3	posedge CLKA	251	251	251	1	1	1
ADA4	posedge CLKA	251	251	251	1	1	1
ADA5	posedge CLKA	251	251	251	1	1	1
ADA6	posedge CLKA	251	251	251	1	1	1
ADA7	posedge CLKA	251	251	251	1	1	1
ADA8	posedge CLKA	251	251	251	1	1	1
ADA9	posedge CLKA	251	251	251	1	1	1
ADB0	posedge CLKB	205	205	205	101	101	101
ADB1	posedge CLKB	205	205	205	101	101	101
ADB10	posedge CLKB	205	205	205	101	101	101
ADB11	posedge CLKB	205	205	205	101	101	101
ADB12	posedge CLKB	205	205	205	101	101	101
ADB13	posedge CLKB	205	205	205	101	101	101
ADB2	posedge CLKB	205	205	205	101	101	101
ADB3	posedge CLKB	205	205	205	101	101	101
ADB4	posedge CLKB	205	205	205	101	101	101
ADB5	posedge CLKB	205	205	205	101	101	101
ADB6	posedge CLKB	205	205	205	101	101	101
ADB7	posedge CLKB	205	205	205	101	101	101
ADB8	posedge CLKB	205	205	205	101	101	101
ADB9	posedge CLKB	205	205	205	101	101	101
CEA	posedge CLKA	211	211	211	47	47	47
CEB	posedge CLKB	340	340	340	60	60	60
CSA0	posedge CLKA	20	20	20	202	202	202
CSA1	posedge CLKA	20	20	20	202	202	202
CSA2	posedge CLKA	20	20	20	202	202	202
CSB0	posedge CLKB	0	0	0	404	404	404
CSB1	posedge CLKB	0	0	0	404	404	404
CSB2	posedge CLKB	0	0	0	404	404	404
DIA0	posedge CLKA	218	218	218	25	25	25
DIA1	posedge CLKA	218	218	218	25	25	25
DIA10	posedge CLKA	218	218	218	25	25	25
DIA11	posedge CLKA	218	218	218	25	25	25
DIA12	posedge CLKA	218	218	218	25	25	25
DIA13	posedge CLKA	218	218	218	25	25	25
DIA14	posedge CLKA	218	218	218	25	25	25
DIA15	posedge CLKA	218	218	218	25	25	25
DIA16	posedge CLKA	218	218	218	25	25	25
DIA17	posedge CLKA	218	218	218	25	25	25
DIA2	posedge CLKA	218	218	218	25	25	25
DIA3	posedge CLKA	218	218	218	25	25	25
DIA4	posedge CLKA	218	218	218	25	25	25
DIA5	posedge CLKA	218	218	218	25	25	25
DIA6	posedge CLKA	218	218	218	25	25	25
DIA7	posedge CLKA	218	218	218	25	25	25
DIA8	posedge CLKA	218	218	218	25	25	25
DIA9	posedge CLKA	218	218	218	25	25	25
DIB0	posedge CLKB	134	134	134	259	259	259
DIB1	posedge CLKB	134	134	134	259	259	259
DIB10	posedge CLKB	134	134	134	259	259	259
DIB11	posedge CLKB	134	134	134	259	259	259
DIB12	posedge CLKB	134	134	134	259	259	259
DIB13	posedge CLKB	134	134	134	259	259	259
DIB14	posedge CLKB	134	134	134	259	259	259
DIB15	posedge CLKB	134	134	134	259	259	259
DIB16	posedge CLKB	134	134	134	259	259	259
DIB17	posedge CLKB	134	134	134	259	259	259
DIB2	posedge CLKB	134	134	134	259	259	259
DIB3	posedge CLKB	134	134	134	259	259	259
DIB4	posedge CLKB	134	134	134	259	259	259
DIB5	posedge CLKB	134	134	134	259	259	259
DIB6	posedge CLKB	134	134	134	259	259	259
DIB7	posedge CLKB	134	134	134	259	259	259
DIB8	posedge CLKB	134	134	134	259	259	259
DIB9	posedge CLKB	134	134	134	259	259	259
OCEA	posedge CLKA	226	226	226	0	0	0
OCEB	posedge CLKB	253	253	253	0	0	0
RSTA	posedge CLKA	579	579	579	0	0	0
RSTB	posedge CLKB	583	583	583	0	0	0
WEA	posedge CLKA	139	139	139	102	102	102
WEB	posedge CLKB	0	0	0	392	392	392

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2359	2359	2359	212	212	212
negedge CLKB	2359	2359	2359	212	212	212
posedge CLKA	2359	2359	2359	212	212	212
posedge CLKB	2359	2359	2359	212	212	212

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	903	938	973	903	938	973
CLKA	DOA1	903	938	973	903	938	973
CLKA	DOA10	903	938	973	903	938	973
CLKA	DOA11	903	938	973	903	938	973
CLKA	DOA12	903	938	973	903	938	973
CLKA	DOA13	903	938	973	903	938	973
CLKA	DOA14	903	938	973	903	938	973
CLKA	DOA15	903	938	973	903	938	973
CLKA	DOA16	903	938	973	903	938	973
CLKA	DOA17	903	938	973	903	938	973
CLKA	DOA2	903	938	973	903	938	973
CLKA	DOA3	903	938	973	903	938	973
CLKA	DOA4	903	938	973	903	938	973
CLKA	DOA5	903	938	973	903	938	973
CLKA	DOA6	903	938	973	903	938	973
CLKA	DOA7	903	938	973	903	938	973
CLKA	DOA8	903	938	973	903	938	973
CLKA	DOA9	903	938	973	903	938	973
CLKB	DOB0	5795	5812	5830	5795	5812	5830
CLKB	DOB1	5795	5812	5830	5795	5812	5830
CLKB	DOB10	5795	5812	5830	5795	5812	5830
CLKB	DOB11	5795	5812	5830	5795	5812	5830
CLKB	DOB12	5795	5812	5830	5795	5812	5830
CLKB	DOB13	5795	5812	5830	5795	5812	5830
CLKB	DOB14	5795	5812	5830	5795	5812	5830
CLKB	DOB15	5795	5812	5830	5795	5812	5830
CLKB	DOB16	5795	5812	5830	5795	5812	5830
CLKB	DOB17	5795	5812	5830	5795	5812	5830
CLKB	DOB2	5795	5812	5830	5795	5812	5830
CLKB	DOB3	5795	5812	5830	5795	5812	5830
CLKB	DOB4	5795	5812	5830	5795	5812	5830
CLKB	DOB5	5795	5812	5830	5795	5812	5830
CLKB	DOB6	5795	5812	5830	5795	5812	5830
CLKB	DOB7	5795	5812	5830	5795	5812	5830
CLKB	DOB8	5795	5812	5830	5795	5812	5830
CLKB	DOB9	5795	5812	5830	5795	5812	5830

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	251	251	251	1	1	1
ADA1	posedge CLKA	251	251	251	1	1	1
ADA10	posedge CLKA	251	251	251	1	1	1
ADA11	posedge CLKA	251	251	251	1	1	1
ADA12	posedge CLKA	251	251	251	1	1	1
ADA13	posedge CLKA	251	251	251	1	1	1
ADA2	posedge CLKA	251	251	251	1	1	1
ADA3	posedge CLKA	251	251	251	1	1	1
ADA4	posedge CLKA	251	251	251	1	1	1
ADA5	posedge CLKA	251	251	251	1	1	1
ADA6	posedge CLKA	251	251	251	1	1	1
ADA7	posedge CLKA	251	251	251	1	1	1
ADA8	posedge CLKA	251	251	251	1	1	1
ADA9	posedge CLKA	251	251	251	1	1	1
ADB0	posedge CLKB	205	205	205	101	101	101
ADB1	posedge CLKB	205	205	205	101	101	101
ADB10	posedge CLKB	205	205	205	101	101	101
ADB11	posedge CLKB	205	205	205	101	101	101
ADB12	posedge CLKB	205	205	205	101	101	101
ADB13	posedge CLKB	205	205	205	101	101	101
ADB2	posedge CLKB	205	205	205	101	101	101
ADB3	posedge CLKB	205	205	205	101	101	101
ADB4	posedge CLKB	205	205	205	101	101	101
ADB5	posedge CLKB	205	205	205	101	101	101
ADB6	posedge CLKB	205	205	205	101	101	101
ADB7	posedge CLKB	205	205	205	101	101	101
ADB8	posedge CLKB	205	205	205	101	101	101
ADB9	posedge CLKB	205	205	205	101	101	101
CEA	posedge CLKA	211	211	211	47	47	47
CEB	posedge CLKB	340	340	340	60	60	60
CSA0	posedge CLKA	20	20	20	202	202	202
CSA1	posedge CLKA	20	20	20	202	202	202
CSA2	posedge CLKA	20	20	20	202	202	202
CSB0	posedge CLKB	0	0	0	404	404	404
CSB1	posedge CLKB	0	0	0	404	404	404
CSB2	posedge CLKB	0	0	0	404	404	404
DIA0	posedge CLKA	218	218	218	25	25	25
DIA1	posedge CLKA	218	218	218	25	25	25
DIA10	posedge CLKA	218	218	218	25	25	25
DIA11	posedge CLKA	218	218	218	25	25	25
DIA12	posedge CLKA	218	218	218	25	25	25
DIA13	posedge CLKA	218	218	218	25	25	25
DIA14	posedge CLKA	218	218	218	25	25	25
DIA15	posedge CLKA	218	218	218	25	25	25
DIA16	posedge CLKA	218	218	218	25	25	25
DIA17	posedge CLKA	218	218	218	25	25	25
DIA2	posedge CLKA	218	218	218	25	25	25
DIA3	posedge CLKA	218	218	218	25	25	25
DIA4	posedge CLKA	218	218	218	25	25	25
DIA5	posedge CLKA	218	218	218	25	25	25
DIA6	posedge CLKA	218	218	218	25	25	25
DIA7	posedge CLKA	218	218	218	25	25	25
DIA8	posedge CLKA	218	218	218	25	25	25
DIA9	posedge CLKA	218	218	218	25	25	25
DIB0	posedge CLKB	134	134	134	259	259	259
DIB1	posedge CLKB	134	134	134	259	259	259
DIB10	posedge CLKB	134	134	134	259	259	259
DIB11	posedge CLKB	134	134	134	259	259	259
DIB12	posedge CLKB	134	134	134	259	259	259
DIB13	posedge CLKB	134	134	134	259	259	259
DIB14	posedge CLKB	134	134	134	259	259	259
DIB15	posedge CLKB	134	134	134	259	259	259
DIB16	posedge CLKB	134	134	134	259	259	259
DIB17	posedge CLKB	134	134	134	259	259	259
DIB2	posedge CLKB	134	134	134	259	259	259
DIB3	posedge CLKB	134	134	134	259	259	259
DIB4	posedge CLKB	134	134	134	259	259	259
DIB5	posedge CLKB	134	134	134	259	259	259
DIB6	posedge CLKB	134	134	134	259	259	259
DIB7	posedge CLKB	134	134	134	259	259	259
DIB8	posedge CLKB	134	134	134	259	259	259
DIB9	posedge CLKB	134	134	134	259	259	259
OCEA	posedge CLKA	226	226	226	0	0	0
OCEB	posedge CLKB	253	253	253	0	0	0
RSTA	posedge CLKA	576	576	576	0	0	0
RSTB	posedge CLKB	585	585	585	0	0	0
WEA	posedge CLKA	139	139	139	102	102	102
WEB	posedge CLKB	0	0	0	392	392	392

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2359	2359	2359	212	212	212
negedge CLKB	2359	2359	2359	212	212	212
posedge CLKA	2359	2359	2359	212	212	212
posedge CLKB	2359	2359	2359	212	212	212

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	903	938	973	903	938	973
CLKA	DOA1	903	938	973	903	938	973
CLKA	DOA10	903	938	973	903	938	973
CLKA	DOA11	903	938	973	903	938	973
CLKA	DOA12	903	938	973	903	938	973
CLKA	DOA13	903	938	973	903	938	973
CLKA	DOA14	903	938	973	903	938	973
CLKA	DOA15	903	938	973	903	938	973
CLKA	DOA16	903	938	973	903	938	973
CLKA	DOA17	903	938	973	903	938	973
CLKA	DOA2	903	938	973	903	938	973
CLKA	DOA3	903	938	973	903	938	973
CLKA	DOA4	903	938	973	903	938	973
CLKA	DOA5	903	938	973	903	938	973
CLKA	DOA6	903	938	973	903	938	973
CLKA	DOA7	903	938	973	903	938	973
CLKA	DOA8	903	938	973	903	938	973
CLKA	DOA9	903	938	973	903	938	973
CLKB	DOB0	882	919	956	882	919	956
CLKB	DOB1	882	919	956	882	919	956
CLKB	DOB10	882	919	956	882	919	956
CLKB	DOB11	882	919	956	882	919	956
CLKB	DOB12	882	919	956	882	919	956
CLKB	DOB13	882	919	956	882	919	956
CLKB	DOB14	882	919	956	882	919	956
CLKB	DOB15	882	919	956	882	919	956
CLKB	DOB16	882	919	956	882	919	956
CLKB	DOB17	882	919	956	882	919	956
CLKB	DOB2	882	919	956	882	919	956
CLKB	DOB3	882	919	956	882	919	956
CLKB	DOB4	882	919	956	882	919	956
CLKB	DOB5	882	919	956	882	919	956
CLKB	DOB6	882	919	956	882	919	956
CLKB	DOB7	882	919	956	882	919	956
CLKB	DOB8	882	919	956	882	919	956
CLKB	DOB9	882	919	956	882	919	956

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	251	251	251	1	1	1
ADA1	posedge CLKA	251	251	251	1	1	1
ADA10	posedge CLKA	251	251	251	1	1	1
ADA11	posedge CLKA	251	251	251	1	1	1
ADA12	posedge CLKA	251	251	251	1	1	1
ADA13	posedge CLKA	251	251	251	1	1	1
ADA2	posedge CLKA	251	251	251	1	1	1
ADA3	posedge CLKA	251	251	251	1	1	1
ADA4	posedge CLKA	251	251	251	1	1	1
ADA5	posedge CLKA	251	251	251	1	1	1
ADA6	posedge CLKA	251	251	251	1	1	1
ADA7	posedge CLKA	251	251	251	1	1	1
ADA8	posedge CLKA	251	251	251	1	1	1
ADA9	posedge CLKA	251	251	251	1	1	1
ADB0	posedge CLKB	205	205	205	101	101	101
ADB1	posedge CLKB	205	205	205	101	101	101
ADB10	posedge CLKB	205	205	205	101	101	101
ADB11	posedge CLKB	205	205	205	101	101	101
ADB12	posedge CLKB	205	205	205	101	101	101
ADB13	posedge CLKB	205	205	205	101	101	101
ADB2	posedge CLKB	205	205	205	101	101	101
ADB3	posedge CLKB	205	205	205	101	101	101
ADB4	posedge CLKB	205	205	205	101	101	101
ADB5	posedge CLKB	205	205	205	101	101	101
ADB6	posedge CLKB	205	205	205	101	101	101
ADB7	posedge CLKB	205	205	205	101	101	101
ADB8	posedge CLKB	205	205	205	101	101	101
ADB9	posedge CLKB	205	205	205	101	101	101
CEA	posedge CLKA	211	211	211	47	47	47
CEB	posedge CLKB	340	340	340	60	60	60
CSA0	posedge CLKA	20	20	20	202	202	202
CSA1	posedge CLKA	20	20	20	202	202	202
CSA2	posedge CLKA	20	20	20	202	202	202
CSB0	posedge CLKB	0	0	0	404	404	404
CSB1	posedge CLKB	0	0	0	404	404	404
CSB2	posedge CLKB	0	0	0	404	404	404
DIA0	posedge CLKA	218	218	218	25	25	25
DIA1	posedge CLKA	218	218	218	25	25	25
DIA10	posedge CLKA	218	218	218	25	25	25
DIA11	posedge CLKA	218	218	218	25	25	25
DIA12	posedge CLKA	218	218	218	25	25	25
DIA13	posedge CLKA	218	218	218	25	25	25
DIA14	posedge CLKA	218	218	218	25	25	25
DIA15	posedge CLKA	218	218	218	25	25	25
DIA16	posedge CLKA	218	218	218	25	25	25
DIA17	posedge CLKA	218	218	218	25	25	25
DIA2	posedge CLKA	218	218	218	25	25	25
DIA3	posedge CLKA	218	218	218	25	25	25
DIA4	posedge CLKA	218	218	218	25	25	25
DIA5	posedge CLKA	218	218	218	25	25	25
DIA6	posedge CLKA	218	218	218	25	25	25
DIA7	posedge CLKA	218	218	218	25	25	25
DIA8	posedge CLKA	218	218	218	25	25	25
DIA9	posedge CLKA	218	218	218	25	25	25
DIB0	posedge CLKB	134	134	134	259	259	259
DIB1	posedge CLKB	134	134	134	259	259	259
DIB10	posedge CLKB	134	134	134	259	259	259
DIB11	posedge CLKB	134	134	134	259	259	259
DIB12	posedge CLKB	134	134	134	259	259	259
DIB13	posedge CLKB	134	134	134	259	259	259
DIB14	posedge CLKB	134	134	134	259	259	259
DIB15	posedge CLKB	134	134	134	259	259	259
DIB16	posedge CLKB	134	134	134	259	259	259
DIB17	posedge CLKB	134	134	134	259	259	259
DIB2	posedge CLKB	134	134	134	259	259	259
DIB3	posedge CLKB	134	134	134	259	259	259
DIB4	posedge CLKB	134	134	134	259	259	259
DIB5	posedge CLKB	134	134	134	259	259	259
DIB6	posedge CLKB	134	134	134	259	259	259
DIB7	posedge CLKB	134	134	134	259	259	259
DIB8	posedge CLKB	134	134	134	259	259	259
DIB9	posedge CLKB	134	134	134	259	259	259
OCEA	posedge CLKA	226	226	226	0	0	0
OCEB	posedge CLKB	253	253	253	0	0	0
RSTA	posedge CLKA	576	576	576	0	0	0
RSTB	posedge CLKB	583	583	583	0	0	0
WEA	posedge CLKA	139	139	139	102	102	102
WEB	posedge CLKB	0	0	0	392	392	392

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2359	2359	2359	212	212	212
negedge CLKB	2359	2359	2359	212	212	212
posedge CLKA	2359	2359	2359	212	212	212
posedge CLKB	2359	2359	2359	212	212	212

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	5535	5572	5609	5535	5572	5609
CLKA	DOA1	5535	5572	5609	5535	5572	5609
CLKA	DOA10	5535	5572	5609	5535	5572	5609
CLKA	DOA11	5535	5572	5609	5535	5572	5609
CLKA	DOA12	5535	5572	5609	5535	5572	5609
CLKA	DOA13	5535	5572	5609	5535	5572	5609
CLKA	DOA14	5535	5572	5609	5535	5572	5609
CLKA	DOA15	5535	5572	5609	5535	5572	5609
CLKA	DOA16	5535	5572	5609	5535	5572	5609
CLKA	DOA17	5535	5572	5609	5535	5572	5609
CLKA	DOA2	5535	5572	5609	5535	5572	5609
CLKA	DOA3	5535	5572	5609	5535	5572	5609
CLKA	DOA4	5535	5572	5609	5535	5572	5609
CLKA	DOA5	5535	5572	5609	5535	5572	5609
CLKA	DOA6	5535	5572	5609	5535	5572	5609
CLKA	DOA7	5535	5572	5609	5535	5572	5609
CLKA	DOA8	5535	5572	5609	5535	5572	5609
CLKA	DOA9	5535	5572	5609	5535	5572	5609
CLKB	DOB0	5795	5812	5830	5795	5812	5830
CLKB	DOB1	5795	5812	5830	5795	5812	5830
CLKB	DOB10	5795	5812	5830	5795	5812	5830
CLKB	DOB11	5795	5812	5830	5795	5812	5830
CLKB	DOB12	5795	5812	5830	5795	5812	5830
CLKB	DOB13	5795	5812	5830	5795	5812	5830
CLKB	DOB14	5795	5812	5830	5795	5812	5830
CLKB	DOB15	5795	5812	5830	5795	5812	5830
CLKB	DOB16	5795	5812	5830	5795	5812	5830
CLKB	DOB17	5795	5812	5830	5795	5812	5830
CLKB	DOB2	5795	5812	5830	5795	5812	5830
CLKB	DOB3	5795	5812	5830	5795	5812	5830
CLKB	DOB4	5795	5812	5830	5795	5812	5830
CLKB	DOB5	5795	5812	5830	5795	5812	5830
CLKB	DOB6	5795	5812	5830	5795	5812	5830
CLKB	DOB7	5795	5812	5830	5795	5812	5830
CLKB	DOB8	5795	5812	5830	5795	5812	5830
CLKB	DOB9	5795	5812	5830	5795	5812	5830

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	251	251	251	1	1	1
ADA1	posedge CLKA	251	251	251	1	1	1
ADA10	posedge CLKA	251	251	251	1	1	1
ADA11	posedge CLKA	251	251	251	1	1	1
ADA12	posedge CLKA	251	251	251	1	1	1
ADA13	posedge CLKA	251	251	251	1	1	1
ADA2	posedge CLKA	251	251	251	1	1	1
ADA3	posedge CLKA	251	251	251	1	1	1
ADA4	posedge CLKA	251	251	251	1	1	1
ADA5	posedge CLKA	251	251	251	1	1	1
ADA6	posedge CLKA	251	251	251	1	1	1
ADA7	posedge CLKA	251	251	251	1	1	1
ADA8	posedge CLKA	251	251	251	1	1	1
ADA9	posedge CLKA	251	251	251	1	1	1
ADB0	posedge CLKB	205	205	205	101	101	101
ADB1	posedge CLKB	205	205	205	101	101	101
ADB10	posedge CLKB	205	205	205	101	101	101
ADB11	posedge CLKB	205	205	205	101	101	101
ADB12	posedge CLKB	205	205	205	101	101	101
ADB13	posedge CLKB	205	205	205	101	101	101
ADB2	posedge CLKB	205	205	205	101	101	101
ADB3	posedge CLKB	205	205	205	101	101	101
ADB4	posedge CLKB	205	205	205	101	101	101
ADB5	posedge CLKB	205	205	205	101	101	101
ADB6	posedge CLKB	205	205	205	101	101	101
ADB7	posedge CLKB	205	205	205	101	101	101
ADB8	posedge CLKB	205	205	205	101	101	101
ADB9	posedge CLKB	205	205	205	101	101	101
CEA	posedge CLKA	211	211	211	47	47	47
CEB	posedge CLKB	340	340	340	60	60	60
CSA0	posedge CLKA	20	20	20	202	202	202
CSA1	posedge CLKA	20	20	20	202	202	202
CSA2	posedge CLKA	20	20	20	202	202	202
CSB0	posedge CLKB	0	0	0	404	404	404
CSB1	posedge CLKB	0	0	0	404	404	404
CSB2	posedge CLKB	0	0	0	404	404	404
DIA0	posedge CLKA	218	218	218	25	25	25
DIA1	posedge CLKA	218	218	218	25	25	25
DIA10	posedge CLKA	218	218	218	25	25	25
DIA11	posedge CLKA	218	218	218	25	25	25
DIA12	posedge CLKA	218	218	218	25	25	25
DIA13	posedge CLKA	218	218	218	25	25	25
DIA14	posedge CLKA	218	218	218	25	25	25
DIA15	posedge CLKA	218	218	218	25	25	25
DIA16	posedge CLKA	218	218	218	25	25	25
DIA17	posedge CLKA	218	218	218	25	25	25
DIA2	posedge CLKA	218	218	218	25	25	25
DIA3	posedge CLKA	218	218	218	25	25	25
DIA4	posedge CLKA	218	218	218	25	25	25
DIA5	posedge CLKA	218	218	218	25	25	25
DIA6	posedge CLKA	218	218	218	25	25	25
DIA7	posedge CLKA	218	218	218	25	25	25
DIA8	posedge CLKA	218	218	218	25	25	25
DIA9	posedge CLKA	218	218	218	25	25	25
DIB0	posedge CLKB	134	134	134	259	259	259
DIB1	posedge CLKB	134	134	134	259	259	259
DIB10	posedge CLKB	134	134	134	259	259	259
DIB11	posedge CLKB	134	134	134	259	259	259
DIB12	posedge CLKB	134	134	134	259	259	259
DIB13	posedge CLKB	134	134	134	259	259	259
DIB14	posedge CLKB	134	134	134	259	259	259
DIB15	posedge CLKB	134	134	134	259	259	259
DIB16	posedge CLKB	134	134	134	259	259	259
DIB17	posedge CLKB	134	134	134	259	259	259
DIB2	posedge CLKB	134	134	134	259	259	259
DIB3	posedge CLKB	134	134	134	259	259	259
DIB4	posedge CLKB	134	134	134	259	259	259
DIB5	posedge CLKB	134	134	134	259	259	259
DIB6	posedge CLKB	134	134	134	259	259	259
DIB7	posedge CLKB	134	134	134	259	259	259
DIB8	posedge CLKB	134	134	134	259	259	259
DIB9	posedge CLKB	134	134	134	259	259	259
OCEA	posedge CLKA	226	226	226	0	0	0
OCEB	posedge CLKB	253	253	253	0	0	0
RSTA	posedge CLKA	579	579	579	0	0	0
RSTB	posedge CLKB	585	585	585	0	0	0
WEA	posedge CLKA	139	139	139	102	102	102
WEB	posedge CLKB	0	0	0	392	392	392

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2359	2359	2359	212	212	212
negedge CLKB	2359	2359	2359	212	212	212
posedge CLKA	2359	2359	2359	212	212	212
posedge CLKB	2359	2359	2359	212	212	212

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	5535	5572	5609	5535	5572	5609
CLKA	DOA1	5535	5572	5609	5535	5572	5609
CLKA	DOA10	5535	5572	5609	5535	5572	5609
CLKA	DOA11	5535	5572	5609	5535	5572	5609
CLKA	DOA12	5535	5572	5609	5535	5572	5609
CLKA	DOA13	5535	5572	5609	5535	5572	5609
CLKA	DOA14	5535	5572	5609	5535	5572	5609
CLKA	DOA15	5535	5572	5609	5535	5572	5609
CLKA	DOA16	5535	5572	5609	5535	5572	5609
CLKA	DOA17	5535	5572	5609	5535	5572	5609
CLKA	DOA2	5535	5572	5609	5535	5572	5609
CLKA	DOA3	5535	5572	5609	5535	5572	5609
CLKA	DOA4	5535	5572	5609	5535	5572	5609
CLKA	DOA5	5535	5572	5609	5535	5572	5609
CLKA	DOA6	5535	5572	5609	5535	5572	5609
CLKA	DOA7	5535	5572	5609	5535	5572	5609
CLKA	DOA8	5535	5572	5609	5535	5572	5609
CLKA	DOA9	5535	5572	5609	5535	5572	5609
CLKB	DOB0	5714	5715	5716	5714	5715	5716
CLKB	DOB1	5714	5715	5716	5714	5715	5716
CLKB	DOB10	5714	5715	5716	5714	5715	5716
CLKB	DOB11	5714	5715	5716	5714	5715	5716
CLKB	DOB12	5714	5715	5716	5714	5715	5716
CLKB	DOB13	5714	5715	5716	5714	5715	5716
CLKB	DOB14	5714	5715	5716	5714	5715	5716
CLKB	DOB15	5714	5715	5716	5714	5715	5716
CLKB	DOB16	5714	5715	5716	5714	5715	5716
CLKB	DOB17	5714	5715	5716	5714	5715	5716
CLKB	DOB2	5714	5715	5716	5714	5715	5716
CLKB	DOB3	5714	5715	5716	5714	5715	5716
CLKB	DOB4	5714	5715	5716	5714	5715	5716
CLKB	DOB5	5714	5715	5716	5714	5715	5716
CLKB	DOB6	5714	5715	5716	5714	5715	5716
CLKB	DOB7	5714	5715	5716	5714	5715	5716
CLKB	DOB8	5714	5715	5716	5714	5715	5716
CLKB	DOB9	5714	5715	5716	5714	5715	5716

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	251	251	251	1	1	1
ADA1	posedge CLKA	251	251	251	1	1	1
ADA10	posedge CLKA	251	251	251	1	1	1
ADA11	posedge CLKA	251	251	251	1	1	1
ADA12	posedge CLKA	251	251	251	1	1	1
ADA13	posedge CLKA	251	251	251	1	1	1
ADA2	posedge CLKA	251	251	251	1	1	1
ADA3	posedge CLKA	251	251	251	1	1	1
ADA4	posedge CLKA	251	251	251	1	1	1
ADA5	posedge CLKA	251	251	251	1	1	1
ADA6	posedge CLKA	251	251	251	1	1	1
ADA7	posedge CLKA	251	251	251	1	1	1
ADA8	posedge CLKA	251	251	251	1	1	1
ADA9	posedge CLKA	251	251	251	1	1	1
ADB0	posedge CLKB	205	205	205	101	101	101
ADB1	posedge CLKB	205	205	205	101	101	101
ADB10	posedge CLKB	205	205	205	101	101	101
ADB11	posedge CLKB	205	205	205	101	101	101
ADB12	posedge CLKB	205	205	205	101	101	101
ADB13	posedge CLKB	205	205	205	101	101	101
ADB2	posedge CLKB	205	205	205	101	101	101
ADB3	posedge CLKB	205	205	205	101	101	101
ADB4	posedge CLKB	205	205	205	101	101	101
ADB5	posedge CLKB	205	205	205	101	101	101
ADB6	posedge CLKB	205	205	205	101	101	101
ADB7	posedge CLKB	205	205	205	101	101	101
ADB8	posedge CLKB	205	205	205	101	101	101
ADB9	posedge CLKB	205	205	205	101	101	101
CEA	posedge CLKA	211	211	211	47	47	47
CEB	posedge CLKB	340	340	340	60	60	60
CSA0	posedge CLKA	20	20	20	202	202	202
CSA1	posedge CLKA	20	20	20	202	202	202
CSA2	posedge CLKA	20	20	20	202	202	202
CSB0	posedge CLKB	0	0	0	404	404	404
CSB1	posedge CLKB	0	0	0	404	404	404
CSB2	posedge CLKB	0	0	0	404	404	404
DIA0	posedge CLKA	218	218	218	25	25	25
DIA1	posedge CLKA	218	218	218	25	25	25
DIA10	posedge CLKA	218	218	218	25	25	25
DIA11	posedge CLKA	218	218	218	25	25	25
DIA12	posedge CLKA	218	218	218	25	25	25
DIA13	posedge CLKA	218	218	218	25	25	25
DIA14	posedge CLKA	218	218	218	25	25	25
DIA15	posedge CLKA	218	218	218	25	25	25
DIA16	posedge CLKA	218	218	218	25	25	25
DIA17	posedge CLKA	218	218	218	25	25	25
DIA2	posedge CLKA	218	218	218	25	25	25
DIA3	posedge CLKA	218	218	218	25	25	25
DIA4	posedge CLKA	218	218	218	25	25	25
DIA5	posedge CLKA	218	218	218	25	25	25
DIA6	posedge CLKA	218	218	218	25	25	25
DIA7	posedge CLKA	218	218	218	25	25	25
DIA8	posedge CLKA	218	218	218	25	25	25
DIA9	posedge CLKA	218	218	218	25	25	25
DIB0	posedge CLKB	134	134	134	259	259	259
DIB1	posedge CLKB	134	134	134	259	259	259
DIB10	posedge CLKB	134	134	134	259	259	259
DIB11	posedge CLKB	134	134	134	259	259	259
DIB12	posedge CLKB	134	134	134	259	259	259
DIB13	posedge CLKB	134	134	134	259	259	259
DIB14	posedge CLKB	134	134	134	259	259	259
DIB15	posedge CLKB	134	134	134	259	259	259
DIB16	posedge CLKB	134	134	134	259	259	259
DIB17	posedge CLKB	134	134	134	259	259	259
DIB2	posedge CLKB	134	134	134	259	259	259
DIB3	posedge CLKB	134	134	134	259	259	259
DIB4	posedge CLKB	134	134	134	259	259	259
DIB5	posedge CLKB	134	134	134	259	259	259
DIB6	posedge CLKB	134	134	134	259	259	259
DIB7	posedge CLKB	134	134	134	259	259	259
DIB8	posedge CLKB	134	134	134	259	259	259
DIB9	posedge CLKB	134	134	134	259	259	259
OCEA	posedge CLKA	226	226	226	0	0	0
OCEB	posedge CLKB	253	253	253	0	0	0
RSTA	posedge CLKA	579	579	579	0	0	0
RSTB	posedge CLKB	585	585	585	0	0	0
WEA	posedge CLKA	139	139	139	102	102	102
WEB	posedge CLKB	0	0	0	392	392	392

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2359	2359	2359	212	212	212
negedge CLKB	3235	3235	3235	155	155	155
posedge CLKA	2359	2359	2359	212	212	212
posedge CLKB	3235	3235	3235	155	155	155

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLKA	DOA0	5535	5572	5609	5535	5572	5609
CLKA	DOA1	5535	5572	5609	5535	5572	5609
CLKA	DOA10	5535	5572	5609	5535	5572	5609
CLKA	DOA11	5535	5572	5609	5535	5572	5609
CLKA	DOA12	5535	5572	5609	5535	5572	5609
CLKA	DOA13	5535	5572	5609	5535	5572	5609
CLKA	DOA14	5535	5572	5609	5535	5572	5609
CLKA	DOA15	5535	5572	5609	5535	5572	5609
CLKA	DOA16	5535	5572	5609	5535	5572	5609
CLKA	DOA17	5535	5572	5609	5535	5572	5609
CLKA	DOA2	5535	5572	5609	5535	5572	5609
CLKA	DOA3	5535	5572	5609	5535	5572	5609
CLKA	DOA4	5535	5572	5609	5535	5572	5609
CLKA	DOA5	5535	5572	5609	5535	5572	5609
CLKA	DOA6	5535	5572	5609	5535	5572	5609
CLKA	DOA7	5535	5572	5609	5535	5572	5609
CLKA	DOA8	5535	5572	5609	5535	5572	5609
CLKA	DOA9	5535	5572	5609	5535	5572	5609
CLKB	DOB0	5720	5722	5724	5720	5722	5724
CLKB	DOB1	5720	5722	5724	5720	5722	5724
CLKB	DOB10	5720	5722	5724	5720	5722	5724
CLKB	DOB11	5720	5722	5724	5720	5722	5724
CLKB	DOB12	5720	5722	5724	5720	5722	5724
CLKB	DOB13	5720	5722	5724	5720	5722	5724
CLKB	DOB14	5720	5722	5724	5720	5722	5724
CLKB	DOB15	5720	5722	5724	5720	5722	5724
CLKB	DOB16	5720	5722	5724	5720	5722	5724
CLKB	DOB17	5720	5722	5724	5720	5722	5724
CLKB	DOB2	5720	5722	5724	5720	5722	5724
CLKB	DOB3	5720	5722	5724	5720	5722	5724
CLKB	DOB4	5720	5722	5724	5720	5722	5724
CLKB	DOB5	5720	5722	5724	5720	5722	5724
CLKB	DOB6	5720	5722	5724	5720	5722	5724
CLKB	DOB7	5720	5722	5724	5720	5722	5724
CLKB	DOB8	5720	5722	5724	5720	5722	5724
CLKB	DOB9	5720	5722	5724	5720	5722	5724

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
ADA0	posedge CLKA	251	251	251	1	1	1
ADA1	posedge CLKA	251	251	251	1	1	1
ADA10	posedge CLKA	251	251	251	1	1	1
ADA11	posedge CLKA	251	251	251	1	1	1
ADA12	posedge CLKA	251	251	251	1	1	1
ADA13	posedge CLKA	251	251	251	1	1	1
ADA2	posedge CLKA	251	251	251	1	1	1
ADA3	posedge CLKA	251	251	251	1	1	1
ADA4	posedge CLKA	251	251	251	1	1	1
ADA5	posedge CLKA	251	251	251	1	1	1
ADA6	posedge CLKA	251	251	251	1	1	1
ADA7	posedge CLKA	251	251	251	1	1	1
ADA8	posedge CLKA	251	251	251	1	1	1
ADA9	posedge CLKA	251	251	251	1	1	1
ADB0	posedge CLKB	205	205	205	101	101	101
ADB1	posedge CLKB	205	205	205	101	101	101
ADB10	posedge CLKB	205	205	205	101	101	101
ADB11	posedge CLKB	205	205	205	101	101	101
ADB12	posedge CLKB	205	205	205	101	101	101
ADB13	posedge CLKB	205	205	205	101	101	101
ADB2	posedge CLKB	205	205	205	101	101	101
ADB3	posedge CLKB	205	205	205	101	101	101
ADB4	posedge CLKB	205	205	205	101	101	101
ADB5	posedge CLKB	205	205	205	101	101	101
ADB6	posedge CLKB	205	205	205	101	101	101
ADB7	posedge CLKB	205	205	205	101	101	101
ADB8	posedge CLKB	205	205	205	101	101	101
ADB9	posedge CLKB	205	205	205	101	101	101
CEA	posedge CLKA	211	211	211	47	47	47
CEB	posedge CLKB	340	340	340	60	60	60
CSA0	posedge CLKA	20	20	20	202	202	202
CSA1	posedge CLKA	20	20	20	202	202	202
CSA2	posedge CLKA	20	20	20	202	202	202
CSB0	posedge CLKB	0	0	0	404	404	404
CSB1	posedge CLKB	0	0	0	404	404	404
CSB2	posedge CLKB	0	0	0	404	404	404
DIA0	posedge CLKA	218	218	218	25	25	25
DIA1	posedge CLKA	218	218	218	25	25	25
DIA10	posedge CLKA	218	218	218	25	25	25
DIA11	posedge CLKA	218	218	218	25	25	25
DIA12	posedge CLKA	218	218	218	25	25	25
DIA13	posedge CLKA	218	218	218	25	25	25
DIA14	posedge CLKA	218	218	218	25	25	25
DIA15	posedge CLKA	218	218	218	25	25	25
DIA16	posedge CLKA	218	218	218	25	25	25
DIA17	posedge CLKA	218	218	218	25	25	25
DIA2	posedge CLKA	218	218	218	25	25	25
DIA3	posedge CLKA	218	218	218	25	25	25
DIA4	posedge CLKA	218	218	218	25	25	25
DIA5	posedge CLKA	218	218	218	25	25	25
DIA6	posedge CLKA	218	218	218	25	25	25
DIA7	posedge CLKA	218	218	218	25	25	25
DIA8	posedge CLKA	218	218	218	25	25	25
DIA9	posedge CLKA	218	218	218	25	25	25
DIB0	posedge CLKB	134	134	134	259	259	259
DIB1	posedge CLKB	134	134	134	259	259	259
DIB10	posedge CLKB	134	134	134	259	259	259
DIB11	posedge CLKB	134	134	134	259	259	259
DIB12	posedge CLKB	134	134	134	259	259	259
DIB13	posedge CLKB	134	134	134	259	259	259
DIB14	posedge CLKB	134	134	134	259	259	259
DIB15	posedge CLKB	134	134	134	259	259	259
DIB16	posedge CLKB	134	134	134	259	259	259
DIB17	posedge CLKB	134	134	134	259	259	259
DIB2	posedge CLKB	134	134	134	259	259	259
DIB3	posedge CLKB	134	134	134	259	259	259
DIB4	posedge CLKB	134	134	134	259	259	259
DIB5	posedge CLKB	134	134	134	259	259	259
DIB6	posedge CLKB	134	134	134	259	259	259
DIB7	posedge CLKB	134	134	134	259	259	259
DIB8	posedge CLKB	134	134	134	259	259	259
DIB9	posedge CLKB	134	134	134	259	259	259
OCEA	posedge CLKA	226	226	226	0	0	0
OCEB	posedge CLKB	253	253	253	0	0	0
RSTA	posedge CLKA	579	579	579	0	0	0
RSTB	posedge CLKB	585	585	585	0	0	0
WEA	posedge CLKA	139	139	139	102	102	102
WEB	posedge CLKB	0	0	0	392	392	392

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLKA	2359	2359	2359	212	212	212
negedge CLKB	2341	2341	2341	214	214	214
posedge CLKA	2359	2359	2359	212	212	212
posedge CLKB	2341	2341	2341	214	214	214

IOLOGIC:MODE=IDDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	356	356	356	356	356	356
CLK	RXDATA1	356	356	356	356	356	356

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge CLK	401	401	401	235	235	235

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=IDDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	RXDATA0	453	453	453	453	453	453
CLK	RXDATA1	453	453	453	453	453	453
CLK	RXDATA2	453	453	453	453	453	453
CLK	RXDATA3	453	453	453	453	453	453

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI	posedge ECLK	445	445	445	12	12	12
posedge ECLK	posedge CLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1799	1799	1799	278	278	278
posedge ECLK	1799	1799	1799	278	278	278

IOLOGIC:MODE=IREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	INFF	474	474	474	474	474	474

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	77	77	77
DI	posedge CLK	439	439	439	311	311	311
LSR	posedge CLK	128	128	128	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1945	1945	1945	257	257	257
posedge CLK	1945	1945	1945	257	257	257

IOLOGIC:MODE=ODDRX1F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	983	985	987	983	985	987

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	2000	2000	2000	250	250	250
posedge CLK	2000	2000	2000	250	250	250

IOLOGIC:MODE=ODDRX2F

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
ECLK	IOLDO	1287	1295	1303	1287	1295	1303

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
TXDATA0	posedge CLK	113	113	113	0	0	0
TXDATA1	posedge CLK	113	113	113	0	0	0
TXDATA2	posedge CLK	113	113	113	0	0	0
TXDATA3	posedge CLK	113	113	113	0	0	0
posedge CLK	posedge ECLK	0	0	0	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge ECLK	1600	1600	1600	312	312	312
posedge ECLK	1600	1600	1600	312	312	312

IOLOGIC:MODE=OREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLDO	1200	1200	1200	1200	1200	1200

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	74	74	74
LSR	posedge CLK	141	141	141	0	0	0
TXDATA0	posedge CLK	148	148	148	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1945	1945	1945	257	257	257
posedge CLK	1945	1945	1945	257	257	257

IOLOGIC:MODE=TSREG

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	IOLTO	1031	1031	1031	1031	1031	1031

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	74	74	74
LSR	posedge CLK	141	141	141	0	0	0
TSDATA0	posedge CLK	205	205	205	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1945	1945	1945	257	257	257
posedge CLK	1945	1945	1945	257	257	257

MULT18X18D:REGS=ALL

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	578	656	735	578	656	735

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	53	68	84	0	0	21
B	posedge CLK0	53	68	84	0	0	21
CE0	posedge CLK0	147	199	252	0	0	21
RST0	posedge CLK0	63	79	95	63	73	84
SIGNEDA	posedge CLK0	0	0	0	137	152	168
SIGNEDB	posedge CLK0	0	0	0	137	152	168

MULT18X18D:REGS=INPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	2856	3360	3864	2856	3360	3864

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	53	68	84	0	0	21
B	posedge CLK0	53	68	84	0	0	21
CE0	posedge CLK0	147	199	252	0	0	21
RST0	posedge CLK0	63	79	95	63	73	84
SIGNEDA	posedge CLK0	0	0	0	137	152	168
SIGNEDB	posedge CLK0	0	0	0	137	152	168

MULT18X18D:REGS=NONE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A	P	2909	3418	3927	2909	3418	3927
B	P	2909	3418	3927	2909	3418	3927
SIGNEDA	P	2740	3234	3728	2740	3234	3728
SIGNEDB	P	2740	3234	3728	2740	3234	3728

MULT18X18D:REGS=OUTPUT

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	578	656	735	578	656	735

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	3035	3260	3486	0	0	0
B	posedge CLK0	3035	3260	3486	0	0	0
CE0	posedge CLK0	147	199	252	0	0	21
RST0	posedge CLK0	63	79	95	63	73	84
SIGNEDA	posedge CLK0	2877	3082	3287	0	0	0
SIGNEDB	posedge CLK0	2877	3082	3287	0	0	0

MULT18X18D:REGS=PIPELINE

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK0	P	1302	1318	1334	1302	1318	1334

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
A	posedge CLK0	2405	2515	2625	0	0	0
B	posedge CLK0	2405	2515	2625	0	0	0
CE0	posedge CLK0	147	199	252	0	0	21
RST0	posedge CLK0	63	79	95	63	73	84
SIGNEDA	posedge CLK0	2247	2336	2425	0	0	0
SIGNEDB	posedge CLK0	2247	2336	2425	0	0	0

PIO:IOTYPE=LVCMOS12

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	689	729	770	689	729	770
PADDO	PAD	1543	1665	1787	1543	1665	1787
PADDT	PAD	1650	1916	2183	1650	1916	2183

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS15

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1707	1734	1761	1707	1734	1761
PADDO	PAD	1542	1684	1827	1542	1684	1827
PADDT	PAD	1644	1847	2051	1644	1847	2051

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS18

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	1311	1390	1469	1311	1390	1469
PADDO	PAD	1599	1726	1854	1599	1726	1854
PADDT	PAD	1844	2003	2162	1844	2003	2162

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS25

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	887	946	1005	887	946	1005
PADDO	PAD	1915	1933	1951	1915	1933	1951
PADDT	PAD	1838	2001	2165	1838	2001	2165

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVCMOS33

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	990	1065	1140	990	1065	1140
PADDO	PAD	1988	2331	2674	1988	2331	2674
PADDT	PAD	2203	2613	3023	2203	2613	3023

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	2500	2500	2500	200	200	200
posedge PAD	2500	2500	2500	200	200	200

PIO:IOTYPE=LVDS

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	492	494	497	492	494	497
PADDO	PAD	1065	1066	1067	1065	1066	1067

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	454	465	476	454	465	476
PADDO	PAD	1908	2001	2094	1908	2001	2094
PADDT	PAD	1978	2543	3108	1978	2543	3108

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL15_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	454	465	476	454	465	476
PADDO	PAD	1814	1882	1950	1814	1882	1950
PADDT	PAD	1793	2552	3312	1793	2552	3312

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_I

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	452	463	475	452	463	475
PADDO	PAD	1981	2057	2134	1981	2057	2134
PADDT	PAD	2131	2509	2888	2131	2509	2888

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

PIO:IOTYPE=SSTL18_II

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
PAD	PADDI	452	463	475	452	463	475
PADDO	PAD	1746	1788	1830	1746	1788	1830
PADDT	PAD	1681	2558	3435	1681	2558	3435

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge PAD	1250	1250	1250	400	400	400
posedge PAD	1250	1250	1250	400	400	400

SCCU2C

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	200	218	236	200	218	236
A0	F1	591	652	714	591	652	714
A0	FCO	175	311	447	175	311	447
A1	F1	200	218	236	200	218	236
A1	FCO	175	311	447	175	311	447
B0	F0	200	218	236	200	218	236
B0	F1	591	652	714	591	652	714
B0	FCO	175	311	447	175	311	447
B1	F1	200	218	236	200	218	236
B1	FCO	175	311	447	175	311	447
C0	F0	200	218	236	200	218	236
C0	F1	591	652	714	591	652	714
C0	FCO	175	311	447	175	311	447
C1	F1	200	218	236	200	218	236
C1	FCO	175	311	447	175	311	447
CLK	Q0	430	477	525	430	477	525
CLK	Q1	429	475	522	429	475	522
D0	F0	200	218	236	200	218	236
D0	F1	591	652	714	591	652	714
D0	FCO	175	311	447	175	311	447
D1	F1	200	218	236	200	218	236
D1	FCO	175	311	447	175	311	447
FCI	F0	244	343	443	244	343	443
FCI	F1	357	415	474	357	415	474
FCI	FCO	62	66	71	62	66	71

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	144	147	151
CE	posedge CLK	0	0	0	144	148	152
DI0	posedge CLK	0	0	0	267	285	303
DI1	posedge CLK	0	0	0	266	284	303
LSR	posedge CLK	271	347	424	0	0	0
LSR	posedge CLK	272	348	424	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1050	1050	1050	476	476	476
negedge LSR	525	525	525	952	952	952
posedge CLK	1050	1050	1050	476	476	476
posedge LSR	525	525	525	952	952	952

SDPRAME

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
CLK	Q0	430	477	525	430	477	525
CLK	Q1	429	475	522	429	475	522
RAD0	F0	200	218	236	200	218	236
RAD0	F1	200	218	236	200	218	236
RAD1	F0	200	218	236	200	218	236
RAD1	F1	200	218	236	200	218	236
RAD2	F0	200	218	236	200	218	236
RAD2	F1	200	218	236	200	218	236
RAD3	F0	200	218	236	200	218	236
RAD3	F1	200	218	236	200	218	236
WCK	F0	908	917	926	908	917	926
WCK	F1	910	919	929	910	919	929

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
DI0	posedge CLK	0	0	0	267	285	303
DI1	posedge CLK	0	0	0	266	284	303
WAD0	posedge WCK	0	0	0	268	312	356
WAD1	posedge WCK	0	0	0	278	320	362
WAD2	posedge WCK	0	0	0	256	303	350
WAD3	posedge WCK	0	0	0	273	316	360
WD0	posedge WCK	0	0	0	202	249	297
WD1	posedge WCK	0	0	0	205	250	296
WRE	posedge WCK	254	323	392	0	0	0

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1050	1050	1050	476	476	476
negedge WCK	525	525	525	952	952	952
posedge CLK	1050	1050	1050	476	476	476
posedge WCK	525	525	525	952	952	952

SLOGICB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	F0	200	218	236	200	218	236
A0	OFX0	268	334	401	268	334	401
A1	F1	200	218	236	200	218	236
A1	OFX0	268	334	401	268	334	401
B0	F0	200	218	236	200	218	236
B0	OFX0	268	334	401	268	334	401
B1	F1	200	218	236	200	218	236
B1	OFX0	268	334	401	268	334	401
C0	F0	200	218	236	200	218	236
C0	OFX0	268	334	401	268	334	401
C1	F1	200	218	236	200	218	236
C1	OFX0	268	334	401	268	334	401
CLK	Q0	430	477	525	430	477	525
CLK	Q1	429	475	522	429	475	522
D0	F0	200	218	236	200	218	236
D0	OFX0	268	334	401	268	334	401
D1	F1	200	218	236	200	218	236
D1	OFX0	268	334	401	268	334	401
FXA	OFX1	189	214	239	189	214	239
FXB	OFX1	189	215	242	189	215	242
M0	OFX0	187	221	256	187	221	256
M1	OFX1	186	219	252	186	219	252

Setup/Hold Checks

From Port	To Clock	Setup (ps)			Hold (ps)
From Port	To Clock	Min	Typ	Max	Min	Typ	Max
CE	posedge CLK	0	0	0	144	147	151
CE	posedge CLK	0	0	0	144	148	152
DI0	posedge CLK	0	0	0	267	285	303
DI1	posedge CLK	0	0	0	266	284	303
LSR	posedge CLK	271	347	424	0	0	0
LSR	posedge CLK	272	348	424	0	0	0
M0	posedge CLK	0	0	0	233	268	303
M1	posedge CLK	0	0	0	234	270	306

Width Checks

Clock	Width (ps)			Equiv. Freq (MHz)
Clock	Min	Typ	Max	Min	Typ	Max
negedge CLK	1050	1050	1050	476	476	476
negedge LSR	525	525	525	952	952	952
posedge CLK	1050	1050	1050	476	476	476
posedge LSR	525	525	525	952	952	952

SRAMWB

Propagation Delays

From Port	To Port	Low-High Transition (ps)			High-Low Transition (ps)
From Port	To Port	Min	Typ	Max	Min	Typ	Max
A0	WADO3	0	0	0	0	0	0
A1	WDO1	0	0	0	0	0	0
B0	WADO1	0	0	0	0	0	0
B1	WDO3	0	0	0	0	0	0
C0	WADO2	0	0	0	0	0	0
C1	WDO0	0	0	0	0	0	0
D0	WADO0	0	0	0	0	0	0
D1	WDO2	0	0	0	0	0	0

ECP5 Speed Grade -6 Cell Timings

Contents

DP16KD:REGMODE_A=NOREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=NOREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=NOREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:REGMODE_A=OUTREG,REGMODE_B=OUTREG

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=NORMAL

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=READBEFOREWRITE

Propagation Delays

Setup/Hold Checks

Width Checks

DP16KD:WRITEMODE_A=NORMAL,WRITEMODE_B=WRITETHROUGH

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX1F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IDDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=IREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=ODDRX1F

Propagation Delays

Width Checks

IOLOGIC:MODE=ODDRX2F

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=OREG

Propagation Delays

Setup/Hold Checks

Width Checks

IOLOGIC:MODE=TSREG

Propagation Delays

Setup/Hold Checks

Width Checks

MULT18X18D:REGS=ALL

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=INPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=NONE

Propagation Delays

MULT18X18D:REGS=OUTPUT

Propagation Delays

Setup/Hold Checks

MULT18X18D:REGS=PIPELINE

Propagation Delays

Setup/Hold Checks

PIO:IOTYPE=LVCMOS12

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS15

Propagation Delays

Width Checks

PIO:IOTYPE=LVCMOS18

Propagation Delays

Width Checks