PLL1_UR Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
C
C
C
D
D
D
D
D
D
 
 
D
D
D
D
D
D
D
D
D
D
D
D
E
E
E
M
M
M
M
D
D
D
 
T
T
T
T
T
T
S
E
E
P
D
D
D
P
D
D
D
D
D
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Configuration word CLKOP_DIV

Default value: 7'b0000000

CLKOP_DIV[0]F6B4
CLKOP_DIV[1]F5B4
CLKOP_DIV[2]F4B4
CLKOP_DIV[3]F3B4
CLKOP_DIV[4]F2B4
CLKOP_DIV[5]F1B4
CLKOP_DIV[6]F0B4

Configuration word CLKOS2_CPHASE

Default value: 7'b000000X

CLKOS2_CPHASE[0]
CLKOS2_CPHASE[1]F9B3
CLKOS2_CPHASE[2]F8B3
CLKOS2_CPHASE[3]F7B3
CLKOS2_CPHASE[4]F6B3
CLKOS2_CPHASE[5]F5B3
CLKOS2_CPHASE[6]F4B3

Configuration word CLKOS2_DIV

Default value: 7'b0000000

CLKOS2_DIV[0]F0B5
CLKOS2_DIV[1]F9B6
CLKOS2_DIV[2]F8B6
CLKOS2_DIV[3]F7B6
CLKOS2_DIV[4]F6B6
CLKOS2_DIV[5]F5B6
CLKOS2_DIV[6]F4B6

Configuration word CLKOS3_CPHASE

Default value: 7'b0000000

CLKOS3_CPHASE[0]F3B3
CLKOS3_CPHASE[1]F2B3
CLKOS3_CPHASE[2]F1B3
CLKOS3_CPHASE[3]F0B3
CLKOS3_CPHASE[4]F9B4
CLKOS3_CPHASE[5]F8B4
CLKOS3_CPHASE[6]F7B4

Configuration word CLKOS3_DIV

Default value: 7'b0000000

CLKOS3_DIV[0]F3B6
CLKOS3_DIV[1]F2B6
CLKOS3_DIV[2]F1B6
CLKOS3_DIV[3]F0B6
CLKOS3_DIV[4]F9B7
CLKOS3_DIV[5]F8B7
CLKOS3_DIV[6]F7B7

Configuration word CLKOS_DIV

Default value: 7'b0000000

CLKOS_DIV[0]F9B5
CLKOS_DIV[1]F8B5
CLKOS_DIV[2]F5B5
CLKOS_DIV[3]F4B5
CLKOS_DIV[4]F3B5
CLKOS_DIV[5]F2B5
CLKOS_DIV[6]F1B5

Configuration word MFG1_TEST

Default value: 3'b000

MFG1_TEST[0]F3B8
MFG1_TEST[1]F2B8
MFG1_TEST[2]F1B8

Configuration word MFG2_TEST

Default value: 3'b000

MFG2_TEST[0]F6B8
MFG2_TEST[1]F5B8
MFG2_TEST[2]F4B8

Configuration Setting CLKOP_ENABLE

Default value: DISABLED

Value F2B7
DISABLED -
ENABLED 1

Configuration Setting CLKOP_TRIM_DELAY

Default value: 0

Value F5B9 F6B9 F7B9 F8B9 F9B9
0 0 0 0 0 0
1 0 0 1 1 1
2 0 1 0 1 1
4 1 0 0 1 1

Configuration Setting CLKOP_TRIM_POL

Default value: FALLING

Value F4B9
FALLING 0
RISING 1

Configuration Setting CLKOS2_ENABLE

Default value: DISABLED

Value F0B7
DISABLED -
ENABLED 1

Configuration Setting CLKOS3_ENABLE

Default value: DISABLED

Value F9B8
DISABLED -
ENABLED 1

Configuration Setting CLKOS_ENABLE

Default value: DISABLED

Value F1B7
DISABLED -
ENABLED 1

Configuration Setting CLKOS_TRIM_DELAY

Default value: 0

Value F1B9 F2B9 F3B9 F8B9
0 0 0 0 0
1 0 0 1 1
2 0 1 0 1
4 1 0 0 1

Configuration Setting CLKOS_TRIM_POL

Default value: FALLING

Value F0B9
FALLING 0
RISING 1

Configuration Setting DPHASE_SOURCE

Default value: DISABLED

Value F7B8
DISABLED 0
ENABLED 1

Configuration Setting OUTDIVIDER_MUXA

Default value: DIVA

Value F6B7
DIVA -
REFCLK 1

Configuration Setting OUTDIVIDER_MUXB

Default value: DIVB

Value F5B7
DIVB -
REFCLK 1

Configuration Setting OUTDIVIDER_MUXC

Default value: DIVC

Value F4B7
DIVC -
REFCLK 1

Configuration Setting OUTDIVIDER_MUXD

Default value: DIVD

Value F3B7
DIVD -
REFCLK 1

Configuration Setting SYNC_ENABLE

Default value: DISABLED

Value F8B8
DISABLED 0
ENABLED 1