PLL0_UL Bit Data

M
R
E
E
W
R
R
R
R
R
R
C
C
P
P
P
P
D
D
D
D
D
D
D
D
D
D
D
D
D
D
S
M
M
M
A
A
R
R
R
R
R
R
R
C
C
C
C
C
C
C
K
 
 
K
K
G
G
G
T
T
T
T
P
R
P
R
R
I
V
U
T
S
S
F
F
F
F
F
F
F
F
F
F
F
F
F
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Mux driving E1_CLKFB

Source F1B1 F2B1
E1_CLKINTFB - -
E1_JCLKFB1 1 -
E1_JCLKFB2 - 1
E1_JCLKFB3 1 1

Mux driving E1_REFCLK0

Source F5B0 F6B0 F7B0
E1_JREFCLK0_0 - - -
E1_JREFCLK0_1 1 - -
E1_JREFCLK0_2 - 1 -
E1_JREFCLK0_3 1 1 -
E1_JREFCLK0_4 - - 1
E1_JREFCLK0_5 1 - 1
E1_JREFCLK0_6 - 1 1

Mux driving E1_REFCLK1

Source F0B1 F8B0 F9B0
E1_JREFCLK1_0 - - -
E1_JREFCLK1_4 1 - -
E1_JREFCLK1_1 - 1 -
E1_JREFCLK1_5 1 1 -
E1_JREFCLK1_2 - - 1
E1_JREFCLK1_6 1 - 1
E1_JREFCLK1_3 - 1 1

Configuration word CLKFB_DIV

Default value: 7'b0000000

CLKFB_DIV[0]F4B2
CLKFB_DIV[1]F5B2
CLKFB_DIV[2]F6B2
CLKFB_DIV[3]F7B2
CLKFB_DIV[4]F8B2
CLKFB_DIV[5]F9B2
CLKFB_DIV[6]F0B3

Configuration word CLKI_DIV

Default value: 7'b0000000

CLKI_DIV[0]F7B1
CLKI_DIV[1]F8B1
CLKI_DIV[2]F9B1
CLKI_DIV[3]F0B2
CLKI_DIV[4]F1B2
CLKI_DIV[5]F2B2
CLKI_DIV[6]F3B2

Configuration word CLKOP_CPHASE

Default value: 7'b0000000

CLKOP_CPHASE[0]F7B8
CLKOP_CPHASE[1]F8B8
CLKOP_CPHASE[2]F9B8
CLKOP_CPHASE[3]F0B9
CLKOP_CPHASE[4]F1B9
CLKOP_CPHASE[5]F2B9
CLKOP_CPHASE[6]F3B9

Configuration word CLKOP_FPHASE

Default value: 3'b000

CLKOP_FPHASE[0]F5B7
CLKOP_FPHASE[1]F6B7
CLKOP_FPHASE[2]F7B7

Configuration word CLKOS2_CPHASE

Default value: 7'bXXXXXX0

CLKOS2_CPHASE[0]F1B10
CLKOS2_CPHASE[1]
CLKOS2_CPHASE[2]
CLKOS2_CPHASE[3]
CLKOS2_CPHASE[4]
CLKOS2_CPHASE[5]
CLKOS2_CPHASE[6]

Configuration word CLKOS2_FPHASE

Default value: 3'b000

CLKOS2_FPHASE[0]F1B8
CLKOS2_FPHASE[1]F2B8
CLKOS2_FPHASE[2]F3B8

Configuration word CLKOS3_FPHASE

Default value: 3'b000

CLKOS3_FPHASE[0]F4B8
CLKOS3_FPHASE[1]F5B8
CLKOS3_FPHASE[2]F6B8

Configuration word CLKOS_CPHASE

Default value: 7'b0000000

CLKOS_CPHASE[0]F4B9
CLKOS_CPHASE[1]F5B9
CLKOS_CPHASE[2]F6B9
CLKOS_CPHASE[3]F7B9
CLKOS_CPHASE[4]F8B9
CLKOS_CPHASE[5]F9B9
CLKOS_CPHASE[6]F0B10

Configuration word CLKOS_FPHASE

Default value: 3'b000

CLKOS_FPHASE[0]F8B7
CLKOS_FPHASE[1]F9B7
CLKOS_FPHASE[2]F0B8

Configuration word FREQ_LOCK_ACCURACY

Default value: 2'b00

FREQ_LOCK_ACCURACY[0]F5B3
FREQ_LOCK_ACCURACY[1]F6B3

Configuration word ICP_CURRENT

Default value: 5'b00000

ICP_CURRENT[0]F6B4
ICP_CURRENT[1]F7B4
ICP_CURRENT[2]F8B4
ICP_CURRENT[3]F9B4
ICP_CURRENT[4]F0B5

Configuration word KVCO

Default value: 3'b000

KVCO[0]F1B5
KVCO[1]F4B5
KVCO[2]F5B5

Configuration word LPF_CAPACITOR

Default value: 2'b00

LPF_CAPACITOR[0]F4B4
LPF_CAPACITOR[1]F5B4

Configuration word LPF_RESISTOR

Default value: 7'b0000000

LPF_RESISTOR[0]F7B3
LPF_RESISTOR[1]F8B3
LPF_RESISTOR[2]F9B3
LPF_RESISTOR[3]F0B4
LPF_RESISTOR[4]F1B4
LPF_RESISTOR[5]F2B4
LPF_RESISTOR[6]F3B4

Configuration bit MFG_ENABLE_FILTEROPAMP

Default value: 1'b0

MFG_ENABLE_FILTEROPAMP[0]F4B7

Configuration bit MFG_EN_UP

Default value: 1'b0

MFG_EN_UP[0]F0B7

Configuration bit MFG_FLOAT_ICP

Default value: 1'b0

MFG_FLOAT_ICP[0]F8B6

Configuration bit MFG_FORCE_VFILTER

Default value: 1'b0

MFG_FORCE_VFILTER[0]F9B6

Configuration word MFG_GMCREF_SEL

Default value: 2'b00

MFG_GMCREF_SEL[0]F2B7
MFG_GMCREF_SEL[1]F3B7

Configuration word MFG_GMC_GAIN

Default value: 3'b000

MFG_GMC_GAIN[0]F6B5
MFG_GMC_GAIN[1]F7B5
MFG_GMC_GAIN[2]F8B5

Configuration bit MFG_GMC_PRESET

Default value: 1'b0

MFG_GMC_PRESET[0]F3B6

Configuration bit MFG_GMC_RESET

Default value: 1'b0

MFG_GMC_RESET[0]F4B6

Configuration word MFG_GMC_TEST

Default value: 4'b0000

MFG_GMC_TEST[0]F9B5
MFG_GMC_TEST[1]F0B6
MFG_GMC_TEST[2]F1B6
MFG_GMC_TEST[3]F2B6

Configuration bit MFG_ICP_TEST

Default value: 1'b0

MFG_ICP_TEST[0]F1B7

Configuration bit MFG_LF_PRESET

Default value: 1'b0

MFG_LF_PRESET[0]F5B6

Configuration bit MFG_LF_RESET

Default value: 1'b0

MFG_LF_RESET[0]F6B6

Configuration bit MFG_LF_RESGRND

Default value: 1'b0

MFG_LF_RESGRND[0]F7B6

Configuration word PLL_LOCK_MODE

Default value: 3'b000

PLL_LOCK_MODE[0]F2B3
PLL_LOCK_MODE[1]F3B3
PLL_LOCK_MODE[2]F4B3

Configuration Setting FEEDBK_PATH

Default value: USERCLOCK

Value F1B1 F2B1 F3B1 F4B1 F5B1 F6B1
CLKOP - - - - - -
CLKOS - - - - - -
INT_OP - 1 1 1 - -
INT_OS 1 - 1 1 1 -
USERCLOCK - - - - - -
CLKOS2 - - - - - -
INT_OS2 - - 1 1 - 1
CLKOS3 - - - - - -
INT_OS3 1 1 - 1 1 1

Configuration Setting INTFB_WAKE

Default value: DISABLED

Value F4B0
DISABLED 0
ENABLED 1

Configuration Setting INT_LOCK_STICKY

Default value: DISABLED

Value F1B3
DISABLED 0
ENABLED 1

Configuration Setting MODE

Default value: NONE

Value F0B0
NONE -
EHXPLLL 1

Configuration Setting PLLRST_ENA

Default value: DISABLED

Value F2B0
DISABLED 0
ENABLED 1

Configuration Setting REFIN_RESET

Default value: DISABLED

Value F1B0
DISABLED 0
ENABLED 1

Configuration Setting STDBY_ENABLE

Default value: DISABLED

Value F3B0
DISABLED 0
ENABLED 1

Fixed Connections

SourceSink
E1_REFCLK0→ E1_CLK0_PLLREFCS
E1_REFCLK1→ E1_CLK1_PLLREFCS
E1_CLKFB→ E1_CLKFB_PLL
E1_CLKINTFB_PLL→ E1_CLKINTFB
E1_PLLCSOUT_PLLREFCS→ E1_CLKI_PLL
E1_JCLKOP_PLL→ G_JULCPLL0CLKOP
E1_JCLKOS_PLL→ G_JULCPLL0CLKOS
E1_JCLKOS2_PLL→ G_JULCPLL0CLKOS2
E1_JCLKOS3_PLL→ G_JULCPLL0CLKOS3
45K_S30_JECLK0→ E1_JCLKFB1
85K_S42_JECLK0→ E1_JCLKFB1
45K_S30_JECLK1→ E1_JCLKFB2
85K_S42_JECLK1→ E1_JCLKFB2
S1E1_JCLK0→ E1_JCLKFB3
E1_JD2→ E1_JENCLKOP_PLL
E1_JB3→ E1_JENCLKOS2_PLL
E1_JC3→ E1_JENCLKOS3_PLL
E1_JA3→ E1_JENCLKOS_PLL
E1_JCLKOP_PLL→ E1_JF0
E1_JCLKOS_PLL→ E1_JF2
E1_JCLKOS2_PLL→ E1_JF4
E1_JCLKOS3_PLL→ E1_JF6
E1_JD4→ E1_JPHASEDIR_PLL
E1_JD3→ E1_JPHASELOADREG_PLL
E1_JB4→ E1_JPHASESEL0_PLL
E1_JA4→ E1_JPHASESEL1_PLL
E1_JC4→ E1_JPHASESTEP_PLL
E1_JC2→ E1_JPLLWAKESYNC_PLL
E1_JLOCK_PLL→ E1_JQ2
E1_JINTLOCK_PLL→ E1_JQ4
E1_JCLK0→ E1_JREFCLK0_0
45K_S28_JPADDIC_PIO→ E1_JREFCLK0_1
85K_S40_JPADDIC_PIO→ E1_JREFCLK0_1
45K_S28_JPADDIA_PIO→ E1_JREFCLK0_2
85K_S40_JPADDIA_PIO→ E1_JREFCLK0_2
45K_S7_JPADDIA_PIO→ E1_JREFCLK0_3
85K_S7_JPADDIA_PIO→ E1_JREFCLK0_3
45K_N4E4_JPADDIA_PIO→ E1_JREFCLK0_4
85K_N4E4_JPADDIA_PIO→ E1_JREFCLK0_4
45K_N4E36_JPADDIA_PIO→ E1_JREFCLK0_5
85K_N4E63_JPADDIA_PIO→ E1_JREFCLK0_5
45K_N4E38_JPADDIA_PIO→ E1_JREFCLK0_6
85K_N4E65_JPADDIA_PIO→ E1_JREFCLK0_6
E1_JCLK1→ E1_JREFCLK1_0
45K_S28_JPADDIC_PIO→ E1_JREFCLK1_1
85K_S40_JPADDIC_PIO→ E1_JREFCLK1_1
45K_S28_JPADDIA_PIO→ E1_JREFCLK1_2
85K_S40_JPADDIA_PIO→ E1_JREFCLK1_2
45K_S7_JPADDIA_PIO→ E1_JREFCLK1_3
85K_S7_JPADDIA_PIO→ E1_JREFCLK1_3
45K_N4E4_JPADDIA_PIO→ E1_JREFCLK1_4
85K_N4E4_JPADDIA_PIO→ E1_JREFCLK1_4
45K_N4E36_JPADDIA_PIO→ E1_JREFCLK1_5
85K_N4E63_JPADDIA_PIO→ E1_JREFCLK1_5
45K_N4E38_JPADDIA_PIO→ E1_JREFCLK1_6
85K_N4E65_JPADDIA_PIO→ E1_JREFCLK1_6
E1_CLKI_PLL→ E1_JREFCLK_PLL
E1_JB1→ E1_JRST_PLL
E1_JB2→ E1_JSEL_PLLREFCS
E1_JLSR0→ E1_JSTDBY_PLL