PLL0_LR Bit Data

M
R
E
E
W
R
R
 
R
R
 
C
C
P
P
P
P
D
D
D
D
D
D
D
D
D
D
D
D
D
D
S
M
M
M
A
A
R
R
R
R
R
R
R
C
C
C
C
C
C
C
K
 
 
K
K
G
G
G
T
T
T
T
P
R
P
R
R
I
V
U
T
S
S
F
F
F
F
F
F
F
F
F
F
F
F
F
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Mux driving N1_CLKFB

Source F11B0 F12B0
N1_CLKINTFB - -
N1_JCLKFB1 1 -
N1_JCLKFB2 - 1
N1_JCLKFB3 1 1

Mux driving N1_REFCLK0

Source F5B0 F6B0
N1_JREFCLK0_0 - -
N1_JREFCLK0_1 1 -
N1_JREFCLK0_2 - 1
N1_JREFCLK0_3 1 1

Mux driving N1_REFCLK1

Source F8B0 F9B0
N1_JREFCLK1_0 - -
N1_JREFCLK1_1 1 -
N1_JREFCLK1_2 - 1
N1_JREFCLK1_3 1 1

Configuration word CLKFB_DIV

Default value: 7'b0000000

CLKFB_DIV[0]F24B0
CLKFB_DIV[1]F25B0
CLKFB_DIV[2]F26B0
CLKFB_DIV[3]F27B0
CLKFB_DIV[4]F28B0
CLKFB_DIV[5]F29B0
CLKFB_DIV[6]F30B0

Configuration word CLKI_DIV

Default value: 7'b0000000

CLKI_DIV[0]F17B0
CLKI_DIV[1]F18B0
CLKI_DIV[2]F19B0
CLKI_DIV[3]F20B0
CLKI_DIV[4]F21B0
CLKI_DIV[5]F22B0
CLKI_DIV[6]F23B0

Configuration word CLKOP_CPHASE

Default value: 7'b0000000

CLKOP_CPHASE[0]F87B0
CLKOP_CPHASE[1]F88B0
CLKOP_CPHASE[2]F89B0
CLKOP_CPHASE[3]F90B0
CLKOP_CPHASE[4]F91B0
CLKOP_CPHASE[5]F92B0
CLKOP_CPHASE[6]F93B0

Configuration word CLKOP_FPHASE

Default value: 3'b000

CLKOP_FPHASE[0]F75B0
CLKOP_FPHASE[1]F76B0
CLKOP_FPHASE[2]F77B0

Configuration word CLKOS2_CPHASE

Default value: 7'bXXXXXX0

CLKOS2_CPHASE[0]F101B0
CLKOS2_CPHASE[1]
CLKOS2_CPHASE[2]
CLKOS2_CPHASE[3]
CLKOS2_CPHASE[4]
CLKOS2_CPHASE[5]
CLKOS2_CPHASE[6]

Configuration word CLKOS2_FPHASE

Default value: 3'b000

CLKOS2_FPHASE[0]F81B0
CLKOS2_FPHASE[1]F82B0
CLKOS2_FPHASE[2]F83B0

Configuration word CLKOS3_FPHASE

Default value: 3'b000

CLKOS3_FPHASE[0]F84B0
CLKOS3_FPHASE[1]F85B0
CLKOS3_FPHASE[2]F86B0

Configuration word CLKOS_CPHASE

Default value: 7'b0000000

CLKOS_CPHASE[0]F94B0
CLKOS_CPHASE[1]F95B0
CLKOS_CPHASE[2]F96B0
CLKOS_CPHASE[3]F97B0
CLKOS_CPHASE[4]F98B0
CLKOS_CPHASE[5]F99B0
CLKOS_CPHASE[6]F100B0

Configuration word CLKOS_FPHASE

Default value: 3'b000

CLKOS_FPHASE[0]F78B0
CLKOS_FPHASE[1]F79B0
CLKOS_FPHASE[2]F80B0

Configuration word FREQ_LOCK_ACCURACY

Default value: 2'b00

FREQ_LOCK_ACCURACY[0]F35B0
FREQ_LOCK_ACCURACY[1]F36B0

Configuration word ICP_CURRENT

Default value: 5'b00000

ICP_CURRENT[0]F46B0
ICP_CURRENT[1]F47B0
ICP_CURRENT[2]F48B0
ICP_CURRENT[3]F49B0
ICP_CURRENT[4]F50B0

Configuration word KVCO

Default value: 3'b000

KVCO[0]F51B0
KVCO[1]F54B0
KVCO[2]F55B0

Configuration word LPF_CAPACITOR

Default value: 2'b00

LPF_CAPACITOR[0]F44B0
LPF_CAPACITOR[1]F45B0

Configuration word LPF_RESISTOR

Default value: 7'b0000000

LPF_RESISTOR[0]F37B0
LPF_RESISTOR[1]F38B0
LPF_RESISTOR[2]F39B0
LPF_RESISTOR[3]F40B0
LPF_RESISTOR[4]F41B0
LPF_RESISTOR[5]F42B0
LPF_RESISTOR[6]F43B0

Configuration bit MFG_ENABLE_FILTEROPAMP

Default value: 1'b0

MFG_ENABLE_FILTEROPAMP[0]F74B0

Configuration bit MFG_EN_UP

Default value: 1'b0

MFG_EN_UP[0]F70B0

Configuration bit MFG_FLOAT_ICP

Default value: 1'b0

MFG_FLOAT_ICP[0]F68B0

Configuration bit MFG_FORCE_VFILTER

Default value: 1'b0

MFG_FORCE_VFILTER[0]F69B0

Configuration word MFG_GMCREF_SEL

Default value: 2'b00

MFG_GMCREF_SEL[0]F72B0
MFG_GMCREF_SEL[1]F73B0

Configuration word MFG_GMC_GAIN

Default value: 3'b000

MFG_GMC_GAIN[0]F56B0
MFG_GMC_GAIN[1]F57B0
MFG_GMC_GAIN[2]F58B0

Configuration bit MFG_GMC_PRESET

Default value: 1'b0

MFG_GMC_PRESET[0]F63B0

Configuration bit MFG_GMC_RESET

Default value: 1'b0

MFG_GMC_RESET[0]F64B0

Configuration word MFG_GMC_TEST

Default value: 4'b0000

MFG_GMC_TEST[0]F59B0
MFG_GMC_TEST[1]F60B0
MFG_GMC_TEST[2]F61B0
MFG_GMC_TEST[3]F62B0

Configuration bit MFG_ICP_TEST

Default value: 1'b0

MFG_ICP_TEST[0]F71B0

Configuration bit MFG_LF_PRESET

Default value: 1'b0

MFG_LF_PRESET[0]F65B0

Configuration bit MFG_LF_RESET

Default value: 1'b0

MFG_LF_RESET[0]F66B0

Configuration bit MFG_LF_RESGRND

Default value: 1'b0

MFG_LF_RESGRND[0]F67B0

Configuration word PLL_LOCK_MODE

Default value: 3'b000

PLL_LOCK_MODE[0]F32B0
PLL_LOCK_MODE[1]F33B0
PLL_LOCK_MODE[2]F34B0

Configuration Setting FEEDBK_PATH

Default value: USERCLOCK

Value F11B0 F12B0 F13B0 F14B0 F15B0 F16B0
CLKOP - - - - - -
CLKOS - - - - - -
INT_OP - 1 1 1 - -
INT_OS 1 - 1 1 1 -
USERCLOCK - - - - - -
CLKOS2 - - - - - -
INT_OS2 - - 1 1 - 1
CLKOS3 - - - - - -
INT_OS3 1 1 - 1 1 1

Configuration Setting INTFB_WAKE

Default value: DISABLED

Value F4B0
DISABLED 0
ENABLED 1

Configuration Setting INT_LOCK_STICKY

Default value: DISABLED

Value F31B0
DISABLED 0
ENABLED 1

Configuration Setting MODE

Default value: NONE

Value F0B0
NONE -
EHXPLLL 1

Configuration Setting PLLRST_ENA

Default value: DISABLED

Value F2B0
DISABLED 0
ENABLED 1

Configuration Setting REFIN_RESET

Default value: DISABLED

Value F1B0
DISABLED 0
ENABLED 1

Configuration Setting STDBY_ENABLE

Default value: DISABLED

Value F3B0
DISABLED 0
ENABLED 1

Fixed Connections

SourceSink
N1_REFCLK0→ N1_CLK0_PLLREFCS
N1_REFCLK1→ N1_CLK1_PLLREFCS
N1_CLKFB→ N1_CLKFB_PLL
N1_CLKINTFB_PLL→ N1_CLKINTFB
N1_PLLCSOUT_PLLREFCS→ N1_CLKI_PLL
N1_JCLKOP_PLL→ G_JLRCPLL0CLKOP
N1_JCLKOS_PLL→ G_JLRCPLL0CLKOS
N1_JCLKOS2_PLL→ G_JLRCPLL0CLKOS2
N1_JCLKOS3_PLL→ G_JLRCPLL0CLKOS3
25K_N24E2_JECLK0→ N1_JCLKFB1
45K_N36E2_JECLK0→ N1_JCLKFB1
85K_N48E2_JECLK0→ N1_JCLKFB1
25K_N24E2_JECLK1→ N1_JCLKFB2
45K_N36E2_JECLK1→ N1_JCLKFB2
85K_N48E2_JECLK1→ N1_JCLKFB2
N1W1_JCLK0→ N1_JCLKFB3
N1_JD2→ N1_JENCLKOP_PLL
N1_JB3→ N1_JENCLKOS2_PLL
N1_JC3→ N1_JENCLKOS3_PLL
N1_JA3→ N1_JENCLKOS_PLL
N1_JCLKOP_PLL→ N1_JF0
N1_JCLKOS_PLL→ N1_JF2
N1_JCLKOS2_PLL→ N1_JF4
N1_JCLKOS3_PLL→ N1_JF6
N1_JD4→ N1_JPHASEDIR_PLL
N1_JD3→ N1_JPHASELOADREG_PLL
N1_JB4→ N1_JPHASESEL0_PLL
N1_JA4→ N1_JPHASESEL1_PLL
N1_JC4→ N1_JPHASESTEP_PLL
N1_JC2→ N1_JPLLWAKESYNC_PLL
N1_JLOCK_PLL→ N1_JQ2
N1_JINTLOCK_PLL→ N1_JQ4
N1_JCLK0→ N1_JREFCLK0_0
25K_N24E2_JPADDIC_PIO→ N1_JREFCLK0_1
45K_N36E2_JPADDIC_PIO→ N1_JREFCLK0_1
85K_N48E2_JPADDIC_PIO→ N1_JREFCLK0_1
25K_N24E2_JPADDIA_PIO→ N1_JREFCLK0_2
45K_N36E2_JPADDIA_PIO→ N1_JREFCLK0_2
85K_N48E2_JPADDIA_PIO→ N1_JREFCLK0_2
25K_N3E2_JPADDIC_PIO→ N1_JREFCLK0_3
45K_N3E2_JPADDIC_PIO→ N1_JREFCLK0_3
85K_N3E2_JPADDIC_PIO→ N1_JREFCLK0_3
N1_JCLK1→ N1_JREFCLK1_0
25K_N24E2_JPADDIC_PIO→ N1_JREFCLK1_1
45K_N36E2_JPADDIC_PIO→ N1_JREFCLK1_1
85K_N48E2_JPADDIC_PIO→ N1_JREFCLK1_1
25K_N24E2_JPADDIA_PIO→ N1_JREFCLK1_2
45K_N36E2_JPADDIA_PIO→ N1_JREFCLK1_2
85K_N48E2_JPADDIA_PIO→ N1_JREFCLK1_2
25K_N3E2_JPADDIC_PIO→ N1_JREFCLK1_3
45K_N3E2_JPADDIC_PIO→ N1_JREFCLK1_3
85K_N3E2_JPADDIC_PIO→ N1_JREFCLK1_3
N1_CLKI_PLL→ N1_JREFCLK_PLL
N1_JB1→ N1_JRST_PLL
N1_JB2→ N1_JSEL_PLLREFCS
N1_JLSR0→ N1_JSTDBY_PLL