PICT0 Bit Data

 
 
S
C
V
V
V
V
V
V
V
T
G
 
 
 
 
R
 
C
C
D
L
 
 
 
M
 
 
 
 
I
L
 
 
 
 
L
 
E
R
M
C
C
O
L
 
 
 
 
O
O
 
 
T
T
R
 
 
T
 
 
 
 
M
 
 
O
O
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Mux driving N1_JDIA

Source F21B0
N1_INDDA_SIOLOGIC 1

Configuration word IOLOGICA.DELAY.DEL_VALUE

Default value: 7'b0000000

IOLOGICA.DELAY.DEL_VALUE[0]F10B0
IOLOGICA.DELAY.DEL_VALUE[1]F9B0
IOLOGICA.DELAY.DEL_VALUE[2]F8B0
IOLOGICA.DELAY.DEL_VALUE[3]F7B0
IOLOGICA.DELAY.DEL_VALUE[4]F6B0
IOLOGICA.DELAY.DEL_VALUE[5]F5B0
IOLOGICA.DELAY.DEL_VALUE[6]F4B0

Configuration Setting IOLOGICA.CEIMUX

Default value: CEMUX

Value F64B0
CEMUX -
1 1

Configuration Setting IOLOGICA.CEMUX

Default value: INV

Value F3B0
CE 1
INV -

Configuration Setting IOLOGICA.CEOMUX

Default value: CEMUX

Value F41B0
CEMUX -
1 1

Configuration Setting IOLOGICA.CLKIMUX

Default value: 0

Value F19B0 F20B0
0 - -
CLK 1 -
INV 1 1

Configuration Setting IOLOGICA.CLKOMUX

Default value: 0

Value F42B0 F43B0
0 - -
CLK 1 -
INV 1 1

Configuration Setting IOLOGICA.DELAY.OUTDEL

Default value: DISABLED

Value F44B0
DISABLED -
ENABLED 1

Configuration Setting IOLOGICA.DELAY.WAIT_FOR_EDGE

Default value: DISABLED

Value F39B0
DISABLED -
ENABLED 1

Configuration Setting IOLOGICA.FF.INREGMODE

Default value: FF

Value F31B0
FF -
LATCH 1

Configuration Setting IOLOGICA.FF.REGSET

Default value: RESET

Value F17B0
RESET -
SET 1

Configuration Setting IOLOGICA.GSR

Default value: ENABLED

Value F12B0
DISABLED 1
ENABLED -

Configuration Setting IOLOGICA.LOADNMUX

Default value: 1

Value F37B0
LOADN 1
1 -

Configuration Setting IOLOGICA.LSRIMUX

Default value: 0

Value F22B0
0 -
LSRMUX 1

Configuration Setting IOLOGICA.LSRMUX

Default value: INV

Value F32B0
INV -
LSR 1

Configuration Setting IOLOGICA.LSROMUX

Default value: 0

Value F45B0
0 -
LSRMUX 1

Configuration Setting IOLOGICA.MODE

Default value: IREG_OREG

Value F26B0 F41B0 F64B0
NONE - - -
IREG_OREG - - -
IDDRX1_ODDRX1 1 1 1

Configuration Setting IOLOGICA.OUTREG.OUTREGMODE

Default value: FF

Value F68B0
FF -
LATCH 1

Configuration Setting IOLOGICA.OUTREG.REGSET

Default value: RESET

Value F40B0
RESET -
SET 1

Configuration Setting IOLOGICA.SRMODE

Default value: ASYNC

Value F2B0
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICA.TSREG.OUTREGMODE

Default value: FF

Value F67B0
FF -
LATCH 1

Configuration Setting IOLOGICA.TSREG.REGSET

Default value: RESET

Value F56B0
RESET -
SET 1

Configuration Setting PIOA.BASE_TYPE

Default value: INPUT_LVCMOS12

Value F11B0 F54B0 F55B0
NONE - - -
BIDIR_LVCMOS12 - 1 1
INPUT_LVCMOS12 - - -
OUTPUT_HSUL12 - 1 1
OUTPUT_HSUL12D 1 1 1
OUTPUT_LVCMOS12 - 1 1
OUTPUT_LVCMOS12D 1 1 1
BIDIR_LVCMOS15 - 1 1
INPUT_LVCMOS15 - - -
OUTPUT_LVCMOS15 - 1 1
OUTPUT_LVCMOS15D 1 1 1
OUTPUT_SSTL15D_I 1 1 1
OUTPUT_SSTL15D_II 1 1 1
OUTPUT_SSTL15_I - 1 1
OUTPUT_SSTL15_II - 1 1
BIDIR_LVCMOS18 - 1 1
INPUT_LVCMOS18 - - -
OUTPUT_LVCMOS18 - 1 1
OUTPUT_LVCMOS18D 1 1 1
OUTPUT_SSTL18D_I 1 1 1
OUTPUT_SSTL18D_II 1 1 1
OUTPUT_SSTL18_I - 1 1
OUTPUT_SSTL18_II - 1 1
BIDIR_LVCMOS25 - 1 1
INPUT_LVCMOS25 - - -
OUTPUT_LVCMOS25 - 1 1
OUTPUT_LVCMOS25D 1 1 1
OUTPUT_LVDS25E 1 1 1
BIDIR_LVCMOS33 - 1 1
BIDIR_LVTTL33 - 1 1
INPUT_LVCMOS33 - - -
INPUT_LVTTL33 - - -
OUTPUT_LVCMOS33 - 1 1
OUTPUT_LVCMOS33D 1 1 1
OUTPUT_LVPECL33E 1 1 1
OUTPUT_LVTTL33 - 1 1
OUTPUT_SSTL135D_I 1 1 1
OUTPUT_SSTL135D_II 1 1 1
OUTPUT_SSTL135_I - 1 1
OUTPUT_SSTL135_II - 1 1

Configuration Setting PIOA.DATAMUX_ODDR

Default value: PADDO

Value F50B0
IOLDO 1
PADDO -

Configuration Setting PIOA.DATAMUX_OREG

Default value: PADDO

Value F51B0
IOLDO 1
PADDO -

Configuration Setting PIOA.TRIMUX_TSREG

Default value: PADDT

Value F59B0
IOLTO 1
PADDT -