PICR2_DQS1 Bit Data

V
V
V
V
V
V
C
S
 
 
L
D
C
C
R
E
 
G
T
V
C
M
R
E
L
L
I
M
M
 
M
M
O
O
 
 
M
L
O
C
M
M
W
T
I
 
R
T
T
I
V
V
V
V
C
S
O
O
 
M
C
C
R
E
M
G
T
V
V
V
R
E
L
L
I
M
M
 
L
D
O
 
 
 
 
L
O
C
C
M
T
I
 
R
T
T
I
M
M
O
V
V
M
M
O
O
M
M
M
W
U
M
A
M
V
V
V
V
V
V

Mux driving N2_ECLKC

Source F5B1
BNK_ECLK1 1

Mux driving N2_ECLKD

Source F3B6
BNK_ECLK1 1

Mux driving N2_JDIC

Source F1B1
N2_INDDC_IOLOGIC 1

Mux driving N2_JDID

Source F9B7
N2_INDDD_IOLOGIC 1

Configuration word DQS.DQS_LO_DEL_VAL

Default value: 8'b00000000

DQS.DQS_LO_DEL_VAL[0]F1B10
DQS.DQS_LO_DEL_VAL[1]F0B10
DQS.DQS_LO_DEL_VAL[2]F9B11
DQS.DQS_LO_DEL_VAL[3]F8B11
DQS.DQS_LO_DEL_VAL[4]F7B11
DQS.DQS_LO_DEL_VAL[5]F6B11
DQS.DQS_LO_DEL_VAL[6]F5B11
DQS.DQS_LO_DEL_VAL[7]F4B11

Configuration word IOLOGICC.DELAY.DEL_VALUE

Default value: 7'b0000000

IOLOGICC.DELAY.DEL_VALUE[0]F9B1
IOLOGICC.DELAY.DEL_VALUE[1]F0B0
IOLOGICC.DELAY.DEL_VALUE[2]F1B0
IOLOGICC.DELAY.DEL_VALUE[3]F2B0
IOLOGICC.DELAY.DEL_VALUE[4]F3B0
IOLOGICC.DELAY.DEL_VALUE[5]F4B0
IOLOGICC.DELAY.DEL_VALUE[6]F5B0

Configuration word IOLOGICD.DELAY.DEL_VALUE

Default value: 7'b0000000

IOLOGICD.DELAY.DEL_VALUE[0]F7B6
IOLOGICD.DELAY.DEL_VALUE[1]F8B6
IOLOGICD.DELAY.DEL_VALUE[2]F9B6
IOLOGICD.DELAY.DEL_VALUE[3]F0B5
IOLOGICD.DELAY.DEL_VALUE[4]F1B5
IOLOGICD.DELAY.DEL_VALUE[5]F2B5
IOLOGICD.DELAY.DEL_VALUE[6]F3B5

Configuration Setting DQS.DQS_LO_DEL_ADJ

Default value: PLUS

Value F2B11
MINUS 1
PLUS 0

Configuration Setting DQS.MODE

Default value: NONE

Value F1B11 F3B11
NONE - -
DQSBUFM 1 1

Configuration Setting DQS.PAUSE_USED

Default value: NO

Value F0B11
NO -
YES 1

Configuration Setting IOLOGICC.CEIMUX

Default value: CEMUX

Value F9B5
CEMUX -
1 1

Configuration Setting IOLOGICC.CEMUX

Default value: INV

Value F6B0
CE 1
INV -

Configuration Setting IOLOGICC.CEOMUX

Default value: CEMUX

Value F1B2
CEMUX -
1 1

Configuration Setting IOLOGICC.CLKIMUX

Default value: 0

Value F2B1 F3B1
0 - -
CLK - 1
INV 1 1

Configuration Setting IOLOGICC.CLKOMUX

Default value: 0

Value F0B2 F9B3
0 - -
CLK 1 -
INV 1 1

Configuration Setting IOLOGICC.DELAY.OUTDEL

Default value: DISABLED

Value F8B3
DISABLED -
ENABLED 1

Configuration Setting IOLOGICC.DELAY.WAIT_FOR_EDGE

Default value: DISABLED

Value F3B2
DISABLED -
ENABLED 1

Configuration Setting IOLOGICC.FF.INREGMODE

Default value: FF

Value F6B2
FF -
LATCH 1

Configuration Setting IOLOGICC.FF.REGSET

Default value: RESET

Value F4B1
RESET -
SET 1

Configuration Setting IOLOGICC.GSR

Default value: ENABLED

Value F7B1
DISABLED 1
ENABLED -

Configuration Setting IOLOGICC.IDDRXN.MODE

Default value: NONE

Value F5B7 F6B7 F7B2 F8B2
NONE - - - -
IDDRX2 - - - 1
IDDR71 1 1 1 1

Configuration Setting IOLOGICC.IOLTOMUX

Default value: TS

Value F4B4
NONE -
TDDR 1
TS -

Configuration Setting IOLOGICC.LOADNMUX

Default value: 1

Value F4B2
LOADN 1
1 -

Configuration Setting IOLOGICC.LSRIMUX

Default value: 0

Value F0B1
0 -
LSRMUX 1

Configuration Setting IOLOGICC.LSRMUX

Default value: INV

Value F5B2
INV -
LSR 1

Configuration Setting IOLOGICC.LSROMUX

Default value: 0

Value F7B3
0 -
LSRMUX 1

Configuration Setting IOLOGICC.MIDDRX.MODE

Default value: NONE

Value F3B10 F8B2
NONE - -
MIDDRX2 1 1

Configuration Setting IOLOGICC.MIDDRX_MODDRX.WRCLKMUX

Default value: NONE

Value F1B4 F2B4
NONE - -
DQSW - 1
DQSW270 1 1

Configuration Setting IOLOGICC.MODDRX.MODE

Default value: NONE

Value F0B3 F1B3 F1B4
NONE - - -
MODDRX2 - 1 -
MOSHX2 1 - 1

Configuration Setting IOLOGICC.MODE

Default value: NONE

Value F0B4 F1B2 F2B3 F3B3 F6B3 F7B2 F9B5
NONE - - - - 0 - -
IDDRXN 1 1 - - 0 - 1
IREG_OREG 1 - - - 0 - -
MIDDRX_MODDRX 1 1 - - 1 - 1
ODDRXN 1 1 1 1 0 - 1
IDDRX1_ODDRX1 1 1 - - 0 1 1

Configuration Setting IOLOGICC.MTDDRX.DQSW_INVERT

Default value: DISABLED

Value F9B4
DISABLED -
ENABLED 1

Configuration Setting IOLOGICC.MTDDRX.MODE

Default value: NONE

Value F1B3
NONE -
MTSHX2 1

Configuration Setting IOLOGICC.MTDDRX.REGSET

Default value: RESET

Value F6B4
RESET -
SET 1

Configuration Setting IOLOGICC.ODDRXN.MODE

Default value: NONE

Value F0B3 F0B8 F1B3 F1B4 F7B9 F8B9 F9B9
NONE - - - - - - -
ODDRX2 - - 1 1 - - -
ODDR71 1 1 1 1 1 1 1

Configuration Setting IOLOGICC.OUTREG.OUTREGMODE

Default value: FF

Value F6B5
FF -
LATCH 1

Configuration Setting IOLOGICC.OUTREG.REGSET

Default value: RESET

Value F2B2
RESET -
SET 1

Configuration Setting IOLOGICC.SRMODE

Default value: ASYNC

Value F7B0
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICC.TSREG.OUTREGMODE

Default value: FF

Value F7B5
FF -
LATCH 1

Configuration Setting IOLOGICC.TSREG.REGSET

Default value: RESET

Value F6B4
RESET -
SET 1

Configuration Setting IOLOGICD.CEIMUX

Default value: CEMUX

Value F6B10
CEMUX -
1 1

Configuration Setting IOLOGICD.CEMUX

Default value: INV

Value F4B5
CE 1
INV -

Configuration Setting IOLOGICD.CEOMUX

Default value: CEMUX

Value F9B8
CEMUX -
1 1

Configuration Setting IOLOGICD.CLKIMUX

Default value: 0

Value F0B6 F1B6
0 - -
CLK - 1
INV 1 1

Configuration Setting IOLOGICD.CLKOMUX

Default value: 0

Value F7B8 F8B8
0 - -
CLK - 1
INV 1 1

Configuration Setting IOLOGICD.DELAY.OUTDEL

Default value: DISABLED

Value F6B8
DISABLED -
ENABLED 1

Configuration Setting IOLOGICD.DELAY.WAIT_FOR_EDGE

Default value: DISABLED

Value F1B7
DISABLED -
ENABLED 1

Configuration Setting IOLOGICD.FF.INREGMODE

Default value: FF

Value F4B7
FF -
LATCH 1

Configuration Setting IOLOGICD.FF.REGSET

Default value: RESET

Value F2B6
RESET -
SET 1

Configuration Setting IOLOGICD.GSR

Default value: ENABLED

Value F5B6
DISABLED 1
ENABLED -

Configuration Setting IOLOGICD.IDDRXN.MODE

Default value: NONE

Value F5B7 F6B7
NONE - -
IDDRX2 - 1
IDDR71 1 1

Configuration Setting IOLOGICD.IOLTOMUX

Default value: TS

Value F1B9
NONE -
TDDR 1
TS -

Configuration Setting IOLOGICD.LOADNMUX

Default value: 1

Value F2B7
LOADN 1
1 -

Configuration Setting IOLOGICD.LSRIMUX

Default value: 0

Value F8B7
0 -
LSRMUX 1

Configuration Setting IOLOGICD.LSRMUX

Default value: INV

Value F3B7
INV -
LSR 1

Configuration Setting IOLOGICD.LSROMUX

Default value: 0

Value F5B8
0 -
LSRMUX 1

Configuration Setting IOLOGICD.MIDDRX.MODE

Default value: NONE

Value F2B10 F6B7
NONE - -
MIDDRX2 1 1

Configuration Setting IOLOGICD.MIDDRX_MODDRX.WRCLKMUX

Default value: NONE

Value F8B10 F9B10
NONE - -
DQSW - 1
DQSW270 1 1

Configuration Setting IOLOGICD.MODDRX.MODE

Default value: NONE

Value F7B9 F8B9 F8B10
NONE - - -
MODDRX2 - 1 -
MOSHX2 1 - 1

Configuration Setting IOLOGICD.MODE

Default value: NONE

Value F0B8 F4B6 F5B7 F6B10 F7B10 F9B8 F9B9
NONE - 0 - - - - -
IDDRXN - 0 - 1 1 1 -
IREG_OREG - 0 - - 1 - -
MIDDRX_MODDRX - 1 - 1 1 1 -
ODDRXN 1 0 - 1 1 1 1
IDDRX1_ODDRX1 - 0 1 1 1 1 -

Configuration Setting IOLOGICD.MTDDRX.DQSW_INVERT

Default value: DISABLED

Value F6B9
DISABLED -
ENABLED 1

Configuration Setting IOLOGICD.MTDDRX.MODE

Default value: NONE

Value F8B9
NONE -
MTSHX2 1

Configuration Setting IOLOGICD.MTDDRX.REGSET

Default value: RESET

Value F3B9
RESET -
SET 1

Configuration Setting IOLOGICD.ODDRXN.MODE

Default value: NONE

Value F7B9 F8B9 F8B10
NONE - - -
ODDRX2 - 1 1
ODDR71 1 1 1

Configuration Setting IOLOGICD.OUTREG.OUTREGMODE

Default value: FF

Value F4B10
FF -
LATCH 1

Configuration Setting IOLOGICD.OUTREG.REGSET

Default value: RESET

Value F0B7
RESET -
SET 1

Configuration Setting IOLOGICD.SRMODE

Default value: ASYNC

Value F5B5
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICD.TSREG.OUTREGMODE

Default value: FF

Value F5B10
FF -
LATCH 1

Configuration Setting IOLOGICD.TSREG.REGSET

Default value: RESET

Value F3B9
RESET -
SET 1

Configuration Setting PIOC.BASE_TYPE

Default value: INPUT_LVCMOS18D

Value F4B9 F5B9 F6B6 F7B4 F8B1 F8B4
NONE - - - - - -
INPUT_LVDS - - - - - -
INPUT_SLVS - - - - - -
INPUT_SUBLVDS - - - - - -
BIDIR_HSUL12 - - - 1 - 1
BIDIR_HSUL12D 1 1 1 1 1 1
BIDIR_LVCMOS12 - - - 1 - 1
INPUT_HSUL12 - - - - - -
INPUT_HSUL12D - - - - - -
INPUT_LVCMOS12 - - - - - -
OUTPUT_HSUL12 - - - 1 - 1
OUTPUT_HSUL12D 1 1 1 1 1 1
OUTPUT_LVCMOS12 - - - 1 - 1
BIDIR_LVCMOS15 - - - 1 - 1
BIDIR_SSTL15D_I 1 1 1 1 1 1
BIDIR_SSTL15D_II 1 1 1 1 1 1
BIDIR_SSTL15_I - - - 1 - 1
BIDIR_SSTL15_II - - - 1 - 1
INPUT_LVCMOS15 - - - - - -
INPUT_SSTL15D_I - - - - - -
INPUT_SSTL15D_II - - - - - -
INPUT_SSTL15_I - - - - - -
INPUT_SSTL15_II - - - - - -
OUTPUT_LVCMOS15 - - - 1 - 1
OUTPUT_SSTL15D_I 1 1 1 1 1 1
OUTPUT_SSTL15D_II 1 1 1 1 1 1
OUTPUT_SSTL15_I - - - 1 - 1
OUTPUT_SSTL15_II - - - 1 - 1
BIDIR_LVCMOS18 - - - 1 - 1
BIDIR_SSTL18D_I 1 1 1 1 1 1
BIDIR_SSTL18D_II 1 1 1 1 1 1
BIDIR_SSTL18_I - - - 1 - 1
BIDIR_SSTL18_II - - - 1 - 1
INPUT_LVCMOS18 - - - - - -
INPUT_LVCMOS18D - - - - - -
INPUT_SSTL18D_I - - - - - -
INPUT_SSTL18D_II - - - - - -
INPUT_SSTL18_I - - - - - -
INPUT_SSTL18_II - - - - - -
OUTPUT_LVCMOS18 - - - 1 - 1
OUTPUT_SSTL18D_I 1 1 1 1 1 1
OUTPUT_SSTL18D_II 1 1 1 1 1 1
OUTPUT_SSTL18_I - - - 1 - 1
OUTPUT_SSTL18_II - - - 1 - 1
BIDIR_BLVDS25E 1 1 1 1 1 1
BIDIR_LVCMOS25 - - - 1 - 1
BIDIR_LVCMOS25D 1 1 1 1 1 1
BIDIR_MLVDS25E 1 1 1 1 1 1
INPUT_BLVDS25 - - - - - -
INPUT_LVCMOS25 - - - - - -
INPUT_LVCMOS25D - - - - - -
INPUT_MLVDS25 - - - - - -
OUTPUT_BLVDS25E 1 1 1 1 1 1
OUTPUT_LVCMOS25 - - - 1 - 1
OUTPUT_LVCMOS25D 1 1 1 1 1 1
OUTPUT_LVDS25E 1 1 1 1 1 1
OUTPUT_MLVDS25E 1 1 1 1 1 1
BIDIR_LVCMOS33 - - - 1 - 1
BIDIR_LVCMOS33D 1 1 1 1 1 1
BIDIR_LVTTL33 - - - 1 - 1
INPUT_LVCMOS33 - - - - - -
INPUT_LVCMOS33D - - - - - -
INPUT_LVPECL33 - - - - - -
INPUT_LVTTL33 - - - - - -
OUTPUT_LVCMOS33 - - - 1 - 1
OUTPUT_LVCMOS33D 1 1 1 1 1 1
OUTPUT_LVPECL33E 1 1 1 1 1 1
OUTPUT_LVTTL33 - - - 1 - 1
BIDIR_SSTL135D_I 1 1 1 1 1 1
BIDIR_SSTL135D_II 1 1 1 1 1 1
BIDIR_SSTL135_I - - - 1 - 1
BIDIR_SSTL135_II - - - 1 - 1
INPUT_SSTL135D_I - - - - - -
INPUT_SSTL135D_II - - - - - -
INPUT_SSTL135_I - - - - - -
INPUT_SSTL135_II - - - - - -
OUTPUT_SSTL135D_I 1 1 1 1 1 1
OUTPUT_SSTL135D_II 1 1 1 1 1 1
OUTPUT_SSTL135_I - - - 1 - 1
OUTPUT_SSTL135_II - - - 1 - 1

Configuration Setting PIOC.DATAMUX_MDDR

Default value: PADDO

Value F2B3 F3B3
IOLDO 1 1
PADDO - -

Configuration Setting PIOC.DATAMUX_ODDR

Default value: PADDO

Value F3B3
IOLDO 1
PADDO -

Configuration Setting PIOC.DATAMUX_OREG

Default value: PADDO

Value F2B3
IOLDO 1
PADDO -

Configuration Setting PIOC.TRIMUX_TSREG

Default value: PADDT

Value F3B4
IOLTO 1
PADDT -

Configuration Setting PIOD.BASE_TYPE

Default value: INPUT_HSUL12

Value F4B9 F5B9
NONE - -
BIDIR_HSUL12 1 1
BIDIR_LVCMOS12 1 1
INPUT_HSUL12 - -
INPUT_LVCMOS12 - -
OUTPUT_HSUL12 1 1
OUTPUT_LVCMOS12 1 1
BIDIR_LVCMOS15 1 1
BIDIR_SSTL15_I 1 1
BIDIR_SSTL15_II 1 1
INPUT_LVCMOS15 - -
INPUT_SSTL15_I - -
INPUT_SSTL15_II - -
OUTPUT_LVCMOS15 1 1
OUTPUT_SSTL15_I 1 1
OUTPUT_SSTL15_II 1 1
BIDIR_LVCMOS18 1 1
BIDIR_SSTL18_I 1 1
BIDIR_SSTL18_II 1 1
INPUT_LVCMOS18 - -
INPUT_SSTL18_I - -
INPUT_SSTL18_II - -
OUTPUT_LVCMOS18 1 1
OUTPUT_SSTL18_I 1 1
OUTPUT_SSTL18_II 1 1
BIDIR_LVCMOS25 1 1
INPUT_LVCMOS25 - -
OUTPUT_LVCMOS25 1 1
BIDIR_LVCMOS33 1 1
BIDIR_LVTTL33 1 1
INPUT_LVCMOS33 - -
INPUT_LVTTL33 - -
OUTPUT_LVCMOS33 1 1
OUTPUT_LVTTL33 1 1
BIDIR_SSTL135_I 1 1
BIDIR_SSTL135_II 1 1
INPUT_SSTL135_I - -
INPUT_SSTL135_II - -
OUTPUT_SSTL135_I 1 1
OUTPUT_SSTL135_II 1 1

Configuration Setting PIOD.DATAMUX_MDDR

Default value: PADDO

Value F0B8 F9B9
IOLDO 1 1
PADDO - -

Configuration Setting PIOD.DATAMUX_ODDR

Default value: PADDO

Value F0B8
IOLDO 1
PADDO -

Configuration Setting PIOD.DATAMUX_OREG

Default value: PADDO

Value F9B9
IOLDO 1
PADDO -

Configuration Setting PIOD.TRIMUX_TSREG

Default value: PADDT

Value F0B9
IOLTO 1
PADDT -