PICR0 Bit Data

V
V
V
V
V
V
C
S
 
 
L
D
C
C
R
E
M
G
T
V
C
M
R
E
L
L
I
M
M
 
M
M
O
O
 
 
 
L
O
C
M
M
W
T
I
 
R
T
T
I
V
V
V
V
C
S
O
O
 
M
C
C
R
E
M
G
T
V
V
V
R
E
L
L
I
M
M
 
L
D
O
O
 
 
 
L
O
C
C
M
W
T
I
 
R
T
T
I
M
M
 
 
M
M
O
O
 
M
M
M
 
 
 
 
 
 
 
 
 
 

Mux driving ECLKA

Source F5B1
BNK_ECLK0 -
BNK_ECLK1 1

Mux driving ECLKB

Source F3B6
BNK_ECLK0 -
BNK_ECLK1 1

Mux driving JDIA

Source F1B1
JPADDIA_PIO -
INDDA_IOLOGIC 1

Mux driving JDIB

Source F9B7
JPADDIB_PIO -
INDDB_IOLOGIC 1

Configuration word IOLOGICA.DELAY.DEL_VALUE

Default value: 7'b0000000

IOLOGICA.DELAY.DEL_VALUE[0]F9B1
IOLOGICA.DELAY.DEL_VALUE[1]F0B0
IOLOGICA.DELAY.DEL_VALUE[2]F1B0
IOLOGICA.DELAY.DEL_VALUE[3]F2B0
IOLOGICA.DELAY.DEL_VALUE[4]F3B0
IOLOGICA.DELAY.DEL_VALUE[5]F4B0
IOLOGICA.DELAY.DEL_VALUE[6]F5B0

Configuration word IOLOGICB.DELAY.DEL_VALUE

Default value: 7'b0000000

IOLOGICB.DELAY.DEL_VALUE[0]F7B6
IOLOGICB.DELAY.DEL_VALUE[1]F8B6
IOLOGICB.DELAY.DEL_VALUE[2]F9B6
IOLOGICB.DELAY.DEL_VALUE[3]F0B5
IOLOGICB.DELAY.DEL_VALUE[4]F1B5
IOLOGICB.DELAY.DEL_VALUE[5]F2B5
IOLOGICB.DELAY.DEL_VALUE[6]F3B5

Configuration Setting IOLOGICA.CEIMUX

Default value: CEMUX

Value F9B5
CEMUX -
1 1

Configuration Setting IOLOGICA.CEMUX

Default value: INV

Value F6B0
CE 1
INV -

Configuration Setting IOLOGICA.CEOMUX

Default value: CEMUX

Value F1B2
CEMUX -
1 1

Configuration Setting IOLOGICA.CLKIMUX

Default value: 0

Value F2B1 F3B1
0 - -
CLK - 1
INV 1 1

Configuration Setting IOLOGICA.CLKOMUX

Default value: 0

Value F0B2 F9B3
0 - -
CLK 1 -
INV 1 1

Configuration Setting IOLOGICA.DELAY.OUTDEL

Default value: DISABLED

Value F8B3
DISABLED -
ENABLED 1

Configuration Setting IOLOGICA.DELAY.WAIT_FOR_EDGE

Default value: DISABLED

Value F3B2
DISABLED -
ENABLED 1

Configuration Setting IOLOGICA.FF.INREGMODE

Default value: FF

Value F6B2
FF -
LATCH 1

Configuration Setting IOLOGICA.FF.REGSET

Default value: RESET

Value F4B1
RESET -
SET 1

Configuration Setting IOLOGICA.GSR

Default value: ENABLED

Value F7B1
DISABLED 1
ENABLED -

Configuration Setting IOLOGICA.IDDRXN.MODE

Default value: NONE

Value F5B7 F6B7 F7B2 F8B2
NONE - - - -
IDDRX2 - - - 1
IDDR71 1 1 1 1

Configuration Setting IOLOGICA.IOLTOMUX

Default value: TS

Value F4B4
NONE -
TDDR 1
TS -

Configuration Setting IOLOGICA.LOADNMUX

Default value: 1

Value F4B2
LOADN 1
1 -

Configuration Setting IOLOGICA.LSRIMUX

Default value: 0

Value F0B1
0 -
LSRMUX 1

Configuration Setting IOLOGICA.LSRMUX

Default value: INV

Value F5B2
INV -
LSR 1

Configuration Setting IOLOGICA.LSROMUX

Default value: 0

Value F7B3
0 -
LSRMUX 1

Configuration Setting IOLOGICA.MIDDRX.MODE

Default value: NONE

Value F3B10 F8B2
NONE - -
MIDDRX2 1 1

Configuration Setting IOLOGICA.MIDDRX_MODDRX.WRCLKMUX

Default value: NONE

Value F1B4 F2B4
NONE - -
DQSW - 1
DQSW270 1 1

Configuration Setting IOLOGICA.MODDRX.MODE

Default value: NONE

Value F0B3 F1B3 F1B4
NONE - - -
MODDRX2 - 1 -
MOSHX2 1 - 1

Configuration Setting IOLOGICA.MODE

Default value: NONE

Value F0B4 F1B2 F2B3 F3B3 F6B1 F7B2 F9B5
NONE - - - - 0 - -
IDDRXN 1 1 - - 0 - 1
IREG_OREG 1 - - - 0 - -
MIDDRX_MODDRX 1 1 - - 1 - 1
ODDRXN 1 1 1 1 0 - 1
IDDRX1_ODDRX1 1 1 - - 0 1 1

Configuration Setting IOLOGICA.MTDDRX.DQSW_INVERT

Default value: DISABLED

Value F9B4
DISABLED -
ENABLED 1

Configuration Setting IOLOGICA.MTDDRX.MODE

Default value: NONE

Value F1B3
NONE -
MTSHX2 1

Configuration Setting IOLOGICA.MTDDRX.REGSET

Default value: RESET

Value F6B4
RESET -
SET 1

Configuration Setting IOLOGICA.ODDRXN.MODE

Default value: NONE

Value F0B3 F0B8 F1B3 F1B4 F1B8 F8B9 F9B9
NONE - - - - - - -
ODDRX2 - - 1 1 - - -
ODDR71 1 1 1 1 1 1 1

Configuration Setting IOLOGICA.OUTREG.OUTREGMODE

Default value: FF

Value F6B5
FF -
LATCH 1

Configuration Setting IOLOGICA.OUTREG.REGSET

Default value: RESET

Value F2B2
RESET -
SET 1

Configuration Setting IOLOGICA.SRMODE

Default value: ASYNC

Value F7B0
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICA.TSREG.OUTREGMODE

Default value: FF

Value F7B5
FF -
LATCH 1

Configuration Setting IOLOGICA.TSREG.REGSET

Default value: RESET

Value F6B4
RESET -
SET 1

Configuration Setting IOLOGICB.CEIMUX

Default value: CEMUX

Value F7B10
CEMUX -
1 1

Configuration Setting IOLOGICB.CEMUX

Default value: INV

Value F4B5
CE 1
INV -

Configuration Setting IOLOGICB.CEOMUX

Default value: CEMUX

Value F9B8
CEMUX -
1 1

Configuration Setting IOLOGICB.CLKIMUX

Default value: 0

Value F0B6 F1B6
0 - -
CLK - 1
INV 1 1

Configuration Setting IOLOGICB.CLKOMUX

Default value: 0

Value F7B8 F8B8
0 - -
CLK - 1
INV 1 1

Configuration Setting IOLOGICB.DELAY.OUTDEL

Default value: DISABLED

Value F6B8
DISABLED -
ENABLED 1

Configuration Setting IOLOGICB.DELAY.WAIT_FOR_EDGE

Default value: DISABLED

Value F1B7
DISABLED -
ENABLED 1

Configuration Setting IOLOGICB.FF.INREGMODE

Default value: FF

Value F4B7
FF -
LATCH 1

Configuration Setting IOLOGICB.FF.REGSET

Default value: RESET

Value F2B6
RESET -
SET 1

Configuration Setting IOLOGICB.GSR

Default value: ENABLED

Value F5B6
DISABLED 1
ENABLED -

Configuration Setting IOLOGICB.IDDRXN.MODE

Default value: NONE

Value F5B7 F6B7
NONE - -
IDDRX2 - 1
IDDR71 1 1

Configuration Setting IOLOGICB.IOLTOMUX

Default value: TS

Value F2B9
NONE -
TDDR 1
TS -

Configuration Setting IOLOGICB.LOADNMUX

Default value: 1

Value F2B7
LOADN 1
1 -

Configuration Setting IOLOGICB.LSRIMUX

Default value: 0

Value F8B7
0 -
LSRMUX 1

Configuration Setting IOLOGICB.LSRMUX

Default value: INV

Value F3B7
INV -
LSR 1

Configuration Setting IOLOGICB.LSROMUX

Default value: 0

Value F5B8
0 -
LSRMUX 1

Configuration Setting IOLOGICB.MIDDRX.MODE

Default value: NONE

Value F2B10 F6B7
NONE - -
MIDDRX2 1 1

Configuration Setting IOLOGICB.MIDDRX_MODDRX.WRCLKMUX

Default value: NONE

Value F0B9 F9B10
NONE - -
DQSW 1 -
DQSW270 1 1

Configuration Setting IOLOGICB.MODDRX.MODE

Default value: NONE

Value F8B9 F9B9 F9B10
NONE - - -
MODDRX2 - 1 -
MOSHX2 1 - 1

Configuration Setting IOLOGICB.MODE

Default value: NONE

Value F0B8 F1B8 F4B6 F5B7 F7B10 F8B10 F9B8
NONE - - 0 - - - -
IDDRXN - - 0 - 1 1 1
IREG_OREG - - 0 - - 1 -
MIDDRX_MODDRX - - 1 - 1 1 1
ODDRXN 1 1 0 - 1 1 1
IDDRX1_ODDRX1 - - 0 1 1 1 1

Configuration Setting IOLOGICB.MTDDRX.DQSW_INVERT

Default value: DISABLED

Value F7B9
DISABLED -
ENABLED 1

Configuration Setting IOLOGICB.MTDDRX.MODE

Default value: NONE

Value F9B9
NONE -
MTSHX2 1

Configuration Setting IOLOGICB.MTDDRX.REGSET

Default value: RESET

Value F4B9
RESET -
SET 1

Configuration Setting IOLOGICB.ODDRXN.MODE

Default value: NONE

Value F8B9 F9B9 F9B10
NONE - - -
ODDRX2 - 1 1
ODDR71 1 1 1

Configuration Setting IOLOGICB.OUTREG.OUTREGMODE

Default value: FF

Value F4B10
FF -
LATCH 1

Configuration Setting IOLOGICB.OUTREG.REGSET

Default value: RESET

Value F0B7
RESET -
SET 1

Configuration Setting IOLOGICB.SRMODE

Default value: ASYNC

Value F5B5
ASYNC -
LSR_OVER_CE 1

Configuration Setting IOLOGICB.TSREG.OUTREGMODE

Default value: FF

Value F5B10
FF -
LATCH 1

Configuration Setting IOLOGICB.TSREG.REGSET

Default value: RESET

Value F4B9
RESET -
SET 1

Configuration Setting PIOA.BASE_TYPE

Default value: INPUT_LVCMOS18D

Value F5B9 F6B6 F6B9 F7B4 F8B1 F8B4
NONE - - - - - -
BIDIR_LVDS 1 1 1 1 1 1
INPUT_LVDS - - - - - -
INPUT_SLVS - - - - - -
INPUT_SUBLVDS - - - - - -
OUTPUT_LVDS 1 1 1 1 1 1
BIDIR_HSUL12 - - - 1 - 1
BIDIR_HSUL12D 1 1 1 1 1 1
BIDIR_LVCMOS12 - - - 1 - 1
INPUT_HSUL12 - - - - - -
INPUT_HSUL12D - - - - - -
INPUT_LVCMOS12 - - - - - -
OUTPUT_HSUL12 - - - 1 - 1
OUTPUT_HSUL12D 1 1 1 1 1 1
OUTPUT_LVCMOS12 - - - 1 - 1
BIDIR_LVCMOS15 - - - 1 - 1
BIDIR_SSTL15D_I 1 1 1 1 1 1
BIDIR_SSTL15D_II 1 1 1 1 1 1
BIDIR_SSTL15_I - - - 1 - 1
BIDIR_SSTL15_II - - - 1 - 1
INPUT_LVCMOS15 - - - - - -
INPUT_SSTL15D_I - - - - - -
INPUT_SSTL15D_II - - - - - -
INPUT_SSTL15_I - - - - - -
INPUT_SSTL15_II - - - - - -
OUTPUT_LVCMOS15 - - - 1 - 1
OUTPUT_SSTL15D_I 1 1 1 1 1 1
OUTPUT_SSTL15D_II 1 1 1 1 1 1
OUTPUT_SSTL15_I - - - 1 - 1
OUTPUT_SSTL15_II - - - 1 - 1
BIDIR_LVCMOS18 - - - 1 - 1
BIDIR_LVCMOS18D 1 1 1 1 1 1
BIDIR_SSTL18D_I 1 1 1 1 1 1
BIDIR_SSTL18D_II 1 1 1 1 1 1
BIDIR_SSTL18_I - - - 1 - 1
BIDIR_SSTL18_II - - - 1 - 1
INPUT_LVCMOS18 - - - - - -
INPUT_LVCMOS18D - - - - - -
INPUT_SSTL18D_I - - - - - -
INPUT_SSTL18D_II - - - - - -
INPUT_SSTL18_I - - - - - -
INPUT_SSTL18_II - - - - - -
OUTPUT_LVCMOS18 - - - 1 - 1
OUTPUT_LVCMOS18D 1 1 1 1 1 1
OUTPUT_SSTL18D_I 1 1 1 1 1 1
OUTPUT_SSTL18D_II 1 1 1 1 1 1
OUTPUT_SSTL18_I - - - 1 - 1
OUTPUT_SSTL18_II - - - 1 - 1
BIDIR_BLVDS25E 1 1 1 1 1 1
BIDIR_LVCMOS25 - - - 1 - 1
BIDIR_LVCMOS25D 1 1 1 1 1 1
BIDIR_MLVDS25E 1 1 1 1 1 1
INPUT_BLVDS25 - - - - - -
INPUT_LVCMOS25 - - - - - -
INPUT_LVCMOS25D - - - - - -
INPUT_MLVDS25 - - - - - -
OUTPUT_BLVDS25E 1 1 1 1 1 1
OUTPUT_LVCMOS25 - - - 1 - 1
OUTPUT_LVCMOS25D 1 1 1 1 1 1
OUTPUT_LVDS25E 1 1 1 1 1 1
OUTPUT_MLVDS25E 1 1 1 1 1 1
BIDIR_LVCMOS33 - - - 1 - 1
BIDIR_LVCMOS33D 1 1 1 1 1 1
BIDIR_LVTTL33 - - - 1 - 1
INPUT_LVCMOS33 - - - - - -
INPUT_LVCMOS33D - - - - - -
INPUT_LVPECL33 - - - - - -
INPUT_LVTTL33 - - - - - -
OUTPUT_LVCMOS33 - - - 1 - 1
OUTPUT_LVCMOS33D 1 1 1 1 1 1
OUTPUT_LVPECL33E 1 1 1 1 1 1
OUTPUT_LVTTL33 - - - 1 - 1
BIDIR_SSTL135D_I 1 1 1 1 1 1
BIDIR_SSTL135D_II 1 1 1 1 1 1
BIDIR_SSTL135_I - - - 1 - 1
BIDIR_SSTL135_II - - - 1 - 1
INPUT_SSTL135D_I - - - - - -
INPUT_SSTL135D_II - - - - - -
INPUT_SSTL135_I - - - - - -
INPUT_SSTL135_II - - - - - -
OUTPUT_SSTL135D_I 1 1 1 1 1 1
OUTPUT_SSTL135D_II 1 1 1 1 1 1
OUTPUT_SSTL135_I - - - 1 - 1
OUTPUT_SSTL135_II - - - 1 - 1

Configuration Setting PIOA.DATAMUX_MDDR

Default value: PADDO

Value F2B3 F3B3
IOLDO 1 1
PADDO - -

Configuration Setting PIOA.DATAMUX_ODDR

Default value: PADDO

Value F3B3
IOLDO 1
PADDO -

Configuration Setting PIOA.DATAMUX_OREG

Default value: PADDO

Value F2B3
IOLDO 1
PADDO -

Configuration Setting PIOA.TRIMUX_TSREG

Default value: PADDT

Value F3B4
IOLTO 1
PADDT -

Configuration Setting PIOB.BASE_TYPE

Default value: INPUT_HSUL12

Value F5B9 F6B9
NONE - -
BIDIR_HSUL12 1 1
BIDIR_LVCMOS12 1 1
INPUT_HSUL12 - -
INPUT_LVCMOS12 - -
OUTPUT_HSUL12 1 1
OUTPUT_LVCMOS12 1 1
BIDIR_LVCMOS15 1 1
BIDIR_SSTL15_I 1 1
BIDIR_SSTL15_II 1 1
INPUT_LVCMOS15 - -
INPUT_SSTL15_I - -
INPUT_SSTL15_II - -
OUTPUT_LVCMOS15 1 1
OUTPUT_SSTL15_I 1 1
OUTPUT_SSTL15_II 1 1
BIDIR_LVCMOS18 1 1
BIDIR_SSTL18_I 1 1
BIDIR_SSTL18_II 1 1
INPUT_LVCMOS18 - -
INPUT_SSTL18_I - -
INPUT_SSTL18_II - -
OUTPUT_LVCMOS18 1 1
OUTPUT_SSTL18_I 1 1
OUTPUT_SSTL18_II 1 1
BIDIR_LVCMOS25 1 1
INPUT_LVCMOS25 - -
OUTPUT_LVCMOS25 1 1
BIDIR_LVCMOS33 1 1
BIDIR_LVTTL33 1 1
INPUT_LVCMOS33 - -
INPUT_LVTTL33 - -
OUTPUT_LVCMOS33 1 1
OUTPUT_LVTTL33 1 1
BIDIR_SSTL135_I 1 1
BIDIR_SSTL135_II 1 1
INPUT_SSTL135_I - -
INPUT_SSTL135_II - -
OUTPUT_SSTL135_I 1 1
OUTPUT_SSTL135_II 1 1

Configuration Setting PIOB.DATAMUX_MDDR

Default value: PADDO

Value F0B8 F1B8
IOLDO 1 1
PADDO - -

Configuration Setting PIOB.DATAMUX_ODDR

Default value: PADDO

Value F1B8
IOLDO 1
PADDO -

Configuration Setting PIOB.DATAMUX_OREG

Default value: PADDO

Value F0B8
IOLDO 1
PADDO -

Configuration Setting PIOB.TRIMUX_TSREG

Default value: PADDT

Value F1B9
IOLTO 1
PADDT -

Fixed Connections

SourceSink
JDIA→ DIA_IOLOGIC
JDIB→ DIB_IOLOGIC
JDIC→ DIC_IOLOGIC
JDID→ DID_IOLOGIC
DQSG_DQSR90→ DQSR90A_IOLOGIC
DQSG_DQSR90→ DQSR90B_IOLOGIC
DQSG_DQSR90→ DQSR90C_IOLOGIC
DQSG_DQSR90→ DQSR90D_IOLOGIC
DQSG_DQSW270→ DQSW270A_IOLOGIC
DQSG_DQSW270→ DQSW270B_IOLOGIC
DQSG_DQSW270→ DQSW270C_IOLOGIC
DQSG_DQSW270→ DQSW270D_IOLOGIC
DQSG_DQSW→ DQSWA_IOLOGIC
DQSG_DQSW→ DQSWB_IOLOGIC
DQSG_DQSW→ DQSWC_IOLOGIC
DQSG_DQSW→ DQSWD_IOLOGIC
ECLKA→ ECLKA_IOLOGIC
ECLKB→ ECLKB_IOLOGIC
BNK_ECLK0→ ECLKC
ECLKC→ ECLKC_IOLOGIC
BNK_ECLK0→ ECLKD
ECLKD→ ECLKD_IOLOGIC
BNK_INRD→ INRDA_PIO
BNK_INRD→ INRDB_PIO
BNK_INRD→ INRDC_PIO
BNK_INRD→ INRDD_PIO
IOLDOA_IOLOGIC→ IOLDOA
IOLDODA_IOLOGIC→ IOLDOA
IOLDOA→ IOLDOA_PIO
IOLDOB_IOLOGIC→ IOLDOB
IOLDODB_IOLOGIC→ IOLDOB
IOLDOB→ IOLDOB_PIO
IOLDOC_IOLOGIC→ IOLDOC
IOLDODC_IOLOGIC→ IOLDOC
IOLDOC→ IOLDOC_PIO
IOLDODD_IOLOGIC→ IOLDOD
IOLDOD_IOLOGIC→ IOLDOD
IOLDOD→ IOLDOD_PIO
IOLDOA_IOLOGIC→ IOLDOIA_IOLOGIC
IOLDOB_IOLOGIC→ IOLDOIB_IOLOGIC
IOLDOC_IOLOGIC→ IOLDOIC_IOLOGIC
IOLDOD_IOLOGIC→ IOLDOID_IOLOGIC
IOLTOA_IOLOGIC→ IOLTOA_PIO
IOLTOB_IOLOGIC→ IOLTOB_PIO
IOLTOC_IOLOGIC→ IOLTOC_PIO
IOLTOD_IOLOGIC→ IOLTOD_PIO
W1_JCE0→ JCEA_IOLOGIC
W1_JCE1→ JCEB_IOLOGIC
S2W1_JCE0→ JCEC_IOLOGIC
S2W1_JCE1→ JCED_IOLOGIC
W1_JCLK0→ JCLKA_IOLOGIC
W1_JCLK1→ JCLKB_IOLOGIC
S2W1_JCLK0→ JCLKC_IOLOGIC
S2W1_JCLK1→ JCLKD_IOLOGIC
JPADDIC_PIO→ JDIC
JPADDID_PIO→ JDID
W1_JA2→ JDIRECTIONA_IOLOGIC
W1_JA5→ JDIRECTIONB_IOLOGIC
S2W1_JA2→ JDIRECTIONC_IOLOGIC
S2W1_JA5→ JDIRECTIOND_IOLOGIC
JRXDATA0C_IOLOGIC→ S2W1_JF0
JRXDATA0A_IOLOGIC→ W1_JF0
JRXDATA1C_IOLOGIC→ S2W1_JF1
JRXDATA1A_IOLOGIC→ W1_JF1
JRXDATA2C_IOLOGIC→ S2W1_JF2
JRXDATA2A_IOLOGIC→ W1_JF2
JRXDATA3C_IOLOGIC→ S2W1_JF3
JRXDATA3A_IOLOGIC→ W1_JF3
JINFFC_IOLOGIC→ S2W1_JF4
JINFFA_IOLOGIC→ W1_JF4
JDIC→ S2W1_JF5
JDIA→ W1_JF5
JCFLAGC_IOLOGIC→ S2W1_JF6
JCFLAGA_IOLOGIC→ W1_JF6
JCFLAGD_IOLOGIC→ S2W1_JF7
JCFLAGB_IOLOGIC→ W1_JF7
W1_JC2→ JLOADNA_IOLOGIC
W1_JC5→ JLOADNB_IOLOGIC
S2W1_JC2→ JLOADNC_IOLOGIC
S2W1_JC5→ JLOADND_IOLOGIC
W1_JLSR0→ JLSRA_IOLOGIC
W1_JLSR1→ JLSRB_IOLOGIC
S2W1_JLSR0→ JLSRC_IOLOGIC
S2W1_JLSR1→ JLSRD_IOLOGIC
W1_JB2→ JMOVEA_IOLOGIC
W1_JB5→ JMOVEB_IOLOGIC
S2W1_JB2→ JMOVEC_IOLOGIC
S2W1_JB5→ JMOVED_IOLOGIC
W1_JA0→ JPADDOA
W1_JA3→ JPADDOB
S2W1_JA0→ JPADDOC
S2W1_JA3→ JPADDOD
W1_JB0→ JPADDTA
W1_JB3→ JPADDTB
S2W1_JB0→ JPADDTC
S2W1_JB3→ JPADDTD
JRXDATA0D_IOLOGIC→ S2W1_JQ0
JRXDATA0B_IOLOGIC→ W1_JQ0
JRXDATA1D_IOLOGIC→ S2W1_JQ1
JRXDATA4C_IOLOGIC→ S2W1_JQ1
JRXDATA1B_IOLOGIC→ W1_JQ1
JRXDATA4A_IOLOGIC→ W1_JQ1
JRXDATA2D_IOLOGIC→ S2W1_JQ2
JRXDATA5C_IOLOGIC→ S2W1_JQ2
JRXDATA2B_IOLOGIC→ W1_JQ2
JRXDATA5A_IOLOGIC→ W1_JQ2
JRXDATA3D_IOLOGIC→ S2W1_JQ3
JRXDATA6C_IOLOGIC→ S2W1_JQ3
JRXDATA3B_IOLOGIC→ W1_JQ3
JRXDATA6A_IOLOGIC→ W1_JQ3
JINFFD_IOLOGIC→ S2W1_JQ4
JINFFB_IOLOGIC→ W1_JQ4
JDID→ S2W1_JQ5
JDIB→ W1_JQ5
W1_JB1→ JSLIPA_IOLOGIC
W1_JB4→ JSLIPB_IOLOGIC
S2W1_JB1→ JSLIPC_IOLOGIC
S2W1_JB4→ JSLIPD_IOLOGIC
W1_JB0→ JTSDATA0A_IOLOGIC
W1_JB3→ JTSDATA0B_IOLOGIC
S2W1_JB0→ JTSDATA0C_IOLOGIC
S2W1_JB3→ JTSDATA0D_IOLOGIC
W1_JC1→ JTSDATA1A_IOLOGIC
W1_JC4→ JTSDATA1B_IOLOGIC
S2W1_JC1→ JTSDATA1C_IOLOGIC
S2W1_JC4→ JTSDATA1D_IOLOGIC
W1_JA0→ JTXDATA0A_IOLOGIC
W1_JA3→ JTXDATA0B_IOLOGIC
S2W1_JA0→ JTXDATA0C_IOLOGIC
S2W1_JA3→ JTXDATA0D_IOLOGIC
W1_JC0→ JTXDATA1A_IOLOGIC
W1_JC3→ JTXDATA1B_IOLOGIC
S2W1_JC0→ JTXDATA1C_IOLOGIC
S2W1_JC3→ JTXDATA1D_IOLOGIC
W1_JD0→ JTXDATA2A_IOLOGIC
W1_JD3→ JTXDATA2B_IOLOGIC
S2W1_JD0→ JTXDATA2C_IOLOGIC
S2W1_JD3→ JTXDATA2D_IOLOGIC
W1_JA1→ JTXDATA3A_IOLOGIC
W1_JA4→ JTXDATA3B_IOLOGIC
S2W1_JA1→ JTXDATA3C_IOLOGIC
S2W1_JA4→ JTXDATA3D_IOLOGIC
W1_JA3→ JTXDATA4A_IOLOGIC
S2W1_JA3→ JTXDATA4C_IOLOGIC
W1_JC3→ JTXDATA5A_IOLOGIC
S2W1_JC3→ JTXDATA5C_IOLOGIC
W1_JD3→ JTXDATA6A_IOLOGIC
S2W1_JD3→ JTXDATA6C_IOLOGIC
BNK_LVDS→ LVDSA_PIO
BNK_LVDS→ LVDSB_PIO
BNK_LVDS→ LVDSC_PIO
BNK_LVDS→ LVDSD_PIO
JPADDIA_PIO→ PADDIA_IOLOGIC
JPADDIB_PIO→ PADDIB_IOLOGIC
JPADDIC_PIO→ PADDIC_IOLOGIC
JPADDID_PIO→ PADDID_IOLOGIC
JPADDOA→ PADDOA_PIO
JPADDOB→ PADDOB_PIO
JPADDOC→ PADDOC_PIO
JPADDOD→ PADDOD_PIO
JPADDTA→ PADDTA_PIO
JPADDTB→ PADDTB_PIO
JPADDTC→ PADDTC_PIO
JPADDTD→ PADDTD_PIO
DQSG_RDPNTR0→ RDPNTR0A_IOLOGIC
DQSG_RDPNTR0→ RDPNTR0B_IOLOGIC
DQSG_RDPNTR0→ RDPNTR0C_IOLOGIC
DQSG_RDPNTR0→ RDPNTR0D_IOLOGIC
DQSG_RDPNTR1→ RDPNTR1A_IOLOGIC
DQSG_RDPNTR1→ RDPNTR1B_IOLOGIC
DQSG_RDPNTR1→ RDPNTR1C_IOLOGIC
DQSG_RDPNTR1→ RDPNTR1D_IOLOGIC
DQSG_RDPNTR2→ RDPNTR2A_IOLOGIC
DQSG_RDPNTR2→ RDPNTR2B_IOLOGIC
DQSG_RDPNTR2→ RDPNTR2C_IOLOGIC
DQSG_RDPNTR2→ RDPNTR2D_IOLOGIC
DQSG_WRPNTR0→ WRPNTR0A_IOLOGIC
DQSG_WRPNTR0→ WRPNTR0B_IOLOGIC
DQSG_WRPNTR0→ WRPNTR0C_IOLOGIC
DQSG_WRPNTR0→ WRPNTR0D_IOLOGIC
DQSG_WRPNTR1→ WRPNTR1A_IOLOGIC
DQSG_WRPNTR1→ WRPNTR1B_IOLOGIC
DQSG_WRPNTR1→ WRPNTR1C_IOLOGIC
DQSG_WRPNTR1→ WRPNTR1D_IOLOGIC
DQSG_WRPNTR2→ WRPNTR2A_IOLOGIC
DQSG_WRPNTR2→ WRPNTR2B_IOLOGIC
DQSG_WRPNTR2→ WRPNTR2C_IOLOGIC
DQSG_WRPNTR2→ WRPNTR2D_IOLOGIC