MIB2_DSP3 Bit Data

Mux driving W1_JCFB0

Source	F35B1
W1_JR0	1

Mux driving W1_JCFB1

Source	F35B1
W1_JR1	1

Mux driving W1_JCFB10

Source	F35B1
W1_JR10	1

Mux driving W1_JCFB11

Source	F35B1
W1_JR11	1

Mux driving W1_JCFB12

Source	F35B1
W1_JR12	1

Mux driving W1_JCFB13

Source	F35B1
W1_JR13	1

Mux driving W1_JCFB14

Source	F35B1
W1_JR14	1

Mux driving W1_JCFB15

Source	F35B1
W1_JR15	1

Mux driving W1_JCFB16

Source	F35B1
W1_JR16	1

Mux driving W1_JCFB17

Source	F35B1
W1_JR17	1

Mux driving W1_JCFB18

Source	F35B1
W1_JR18	1

Mux driving W1_JCFB19

Source	F35B1
W1_JR19	1

Mux driving W1_JCFB2

Source	F35B1
W1_JR2	1

Mux driving W1_JCFB20

Source	F35B1
W1_JR20	1

Mux driving W1_JCFB21

Source	F35B1
W1_JR21	1

Mux driving W1_JCFB22

Source	F35B1
W1_JR22	1

Mux driving W1_JCFB23

Source	F35B1
W1_JR23	1

Mux driving W1_JCFB24

Source	F35B1
W1_JR24	1

Mux driving W1_JCFB25

Source	F35B1
W1_JR25	1

Mux driving W1_JCFB26

Source	F35B1
W1_JR26	1

Mux driving W1_JCFB27

Source	F29B1
W1_JR27	1

Mux driving W1_JCFB28

Source	F29B1
W1_JR28	1

Mux driving W1_JCFB29

Source	F29B1
W1_JR29	1

Mux driving W1_JCFB3

Source	F35B1
W1_JR3	1

Mux driving W1_JCFB30

Source	F29B1
W1_JR30	1

Mux driving W1_JCFB31

Source	F29B1
W1_JR31	1

Mux driving W1_JCFB32

Source	F29B1
W1_JR32	1

Mux driving W1_JCFB33

Source	F29B1
W1_JR33	1

Mux driving W1_JCFB34

Source	F29B1
W1_JR34	1

Mux driving W1_JCFB35

Source	F29B1
W1_JR35	1

Mux driving W1_JCFB36

Source	F29B1
W1_JR36	1

Mux driving W1_JCFB37

Source	F29B1
W1_JR37	1

Mux driving W1_JCFB38

Source	F29B1
W1_JR38	1

Mux driving W1_JCFB39

Source	F29B1
W1_JR39	1

Mux driving W1_JCFB4

Source	F35B1
W1_JR4	1

Mux driving W1_JCFB40

Source	F29B1
W1_JR40	1

Mux driving W1_JCFB41

Source	F29B1
W1_JR41	1

Mux driving W1_JCFB42

Source	F29B1
W1_JR42	1

Mux driving W1_JCFB43

Source	F29B1
W1_JR43	1

Mux driving W1_JCFB44

Source	F29B1
W1_JR44	1

Mux driving W1_JCFB45

Source	F29B1
W1_JR45	1

Mux driving W1_JCFB46

Source	F29B1
W1_JR46	1

Mux driving W1_JCFB47

Source	F29B1
W1_JR47	1

Mux driving W1_JCFB48

Source	F29B1
W1_JR48	1

Mux driving W1_JCFB49

Source	F29B1
W1_JR49	1

Mux driving W1_JCFB5

Source	F35B1
W1_JR5	1

Mux driving W1_JCFB50

Source	F29B1
W1_JR50	1

Mux driving W1_JCFB51

Source	F29B1
W1_JR51	1

Mux driving W1_JCFB52

Source	F29B1
W1_JR52	1

Mux driving W1_JCFB53

Source	F29B1
W1_JR53	1

Mux driving W1_JCFB6

Source	F35B1
W1_JR6	1

Mux driving W1_JCFB7

Source	F35B1
W1_JR7	1

Mux driving W1_JCFB8

Source	F35B1
W1_JR8	1

Mux driving W1_JCFB9

Source	F35B1
W1_JR9	1

Mux driving W1_JDSPC0

Source	F35B1
W1_JROC27	1

Mux driving W1_JDSPC1

Source	F35B1
W1_JROC28	1

Mux driving W1_JDSPC10

Source	F35B1
W1_JROC37	1

Mux driving W1_JDSPC11

Source	F35B1
W1_JROC38	1

Mux driving W1_JDSPC12

Source	F35B1
W1_JROC39	1

Mux driving W1_JDSPC13

Source	F35B1
W1_JROC40	1

Mux driving W1_JDSPC14

Source	F35B1
W1_JROC41	1

Mux driving W1_JDSPC15

Source	F35B1
W1_JROC42	1

Mux driving W1_JDSPC16

Source	F35B1
W1_JROC43	1

Mux driving W1_JDSPC17

Source	F35B1
W1_JROC44	1

Mux driving W1_JDSPC18

Source	F35B1
W1_JROC45	1

Mux driving W1_JDSPC19

Source	F35B1
W1_JROC46	1

Mux driving W1_JDSPC2

Source	F35B1
W1_JROC29	1

Mux driving W1_JDSPC20

Source	F35B1
W1_JROC47	1

Mux driving W1_JDSPC21

Source	F35B1
W1_JROC48	1

Mux driving W1_JDSPC22

Source	F35B1
W1_JROC49	1

Mux driving W1_JDSPC23

Source	F35B1
W1_JROC50	1

Mux driving W1_JDSPC24

Source	F35B1
W1_JROC51	1

Mux driving W1_JDSPC25

Source	F35B1
W1_JROC52	1

Mux driving W1_JDSPC26

Source	F35B1
W1_JROC53	1

Mux driving W1_JDSPC3

Source	F35B1
W1_JROC30	1

Mux driving W1_JDSPC4

Source	F35B1
W1_JROC31	1

Mux driving W1_JDSPC5

Source	F35B1
W1_JROC32	1

Mux driving W1_JDSPC6

Source	F35B1
W1_JROC33	1

Mux driving W1_JDSPC7

Source	F35B1
W1_JROC34	1

Mux driving W1_JDSPC8

Source	F35B1
W1_JROC35	1

Mux driving W1_JDSPC9

Source	F35B1
W1_JROC36	1

Mux driving W1_JP0

Source	F75B1
W1_JCO0	1

Mux driving W1_JP1

Source	F75B1
W1_JCO1	1

Mux driving W1_JP10

Source	F75B1
W1_JCO10	1

Mux driving W1_JP11

Source	F75B1
W1_JCO11	1

Mux driving W1_JP12

Source	F75B1
W1_JCO12	1

Mux driving W1_JP13

Source	F75B1
W1_JCO13	1

Mux driving W1_JP14

Source	F75B1
W1_JCO14	1

Mux driving W1_JP15

Source	F75B1
W1_JCO15	1

Mux driving W1_JP16

Source	F75B1
W1_JCO16	1

Mux driving W1_JP17

Source	F75B1
W1_JCO17	1

Mux driving W1_JP18

Source	F75B1
W1_JCO18	1

Mux driving W1_JP19

Source	F75B1
W1_JCO19	1

Mux driving W1_JP2

Source	F75B1
W1_JCO2	1

Mux driving W1_JP20

Source	F75B1
W1_JCO20	1

Mux driving W1_JP21

Source	F75B1
W1_JCO21	1

Mux driving W1_JP22

Source	F75B1
W1_JCO22	1

Mux driving W1_JP23

Source	F75B1
W1_JCO23	1

Mux driving W1_JP24

Source	F75B1
W1_JCO24	1

Mux driving W1_JP25

Source	F75B1
W1_JCO25	1

Mux driving W1_JP26

Source	F75B1
W1_JCO26	1

Mux driving W1_JP27

Source	F75B1
W1_JCO27	1

Mux driving W1_JP28

Source	F75B1
W1_JCO28	1

Mux driving W1_JP29

Source	F75B1
W1_JCO29	1

Mux driving W1_JP3

Source	F75B1
W1_JCO3	1

Mux driving W1_JP30

Source	F75B1
W1_JCO30	1

Mux driving W1_JP31

Source	F75B1
W1_JCO31	1

Mux driving W1_JP32

Source	F75B1
W1_JCO32	1

Mux driving W1_JP33

Source	F75B1
W1_JCO33	1

Mux driving W1_JP34

Source	F75B1
W1_JCO34	1

Mux driving W1_JP35

Source	F75B1
W1_JCO35	1

Mux driving W1_JP36

Source	F75B1
W1_JCO36	1

Mux driving W1_JP37

Source	F75B1
W1_JCO37	1

Mux driving W1_JP38

Source	F75B1
W1_JCO38	1

Mux driving W1_JP39

Source	F75B1
W1_JCO39	1

Mux driving W1_JP4

Source	F75B1
W1_JCO4	1

Mux driving W1_JP40

Source	F75B1
W1_JCO40	1

Mux driving W1_JP41

Source	F75B1
W1_JCO41	1

Mux driving W1_JP42

Source	F75B1
W1_JCO42	1

Mux driving W1_JP43

Source	F75B1
W1_JCO43	1

Mux driving W1_JP44

Source	F75B1
W1_JCO44	1

Mux driving W1_JP45

Source	F75B1
W1_JCO45	1

Mux driving W1_JP46

Source	F75B1
W1_JCO46	1

Mux driving W1_JP47

Source	F75B1
W1_JCO47	1

Mux driving W1_JP48

Source	F75B1
W1_JCO48	1

Mux driving W1_JP49

Source	F75B1
W1_JCO49	1

Mux driving W1_JP5

Source	F75B1
W1_JCO5	1

Mux driving W1_JP50

Source	F75B1
W1_JCO50	1

Mux driving W1_JP51

Source	F75B1
W1_JCO51	1

Mux driving W1_JP52

Source	F75B1
W1_JCO52	1

Mux driving W1_JP53

Source	F75B1
W1_JCO53	1

Mux driving W1_JP6

Source	F75B1
W1_JCO6	1

Mux driving W1_JP7

Source	F75B1
W1_JCO7	1

Mux driving W1_JP8

Source	F75B1
W1_JCO8	1

Mux driving W1_JP9

Source	F75B1
W1_JCO9	1

Configuration Setting ALU54_3.MODE

Default value: NONE

Value	F28B1	F30B0	F34B1	F76B1
NONE	-	-	-	-
ALU54B	1	1	1	1

Configuration Setting ALU54_3.REG_FLAG_CLK

Default value: CLK3

Value	F3B1	F4B1
NONE	-	-
CLK0	1	1
CLK1	1	-
CLK2	-	1
CLK3	-	-

Configuration Setting ALU54_3.REG_INPUTC1_CLK

Default value: CLK3

Value	F30B1	F31B1
NONE	-	-
CLK0	1	1
CLK1	1	-
CLK2	-	1
CLK3	-	-

Configuration Setting ALU54_3.REG_OPCODEOP0_0_RST

Default value: RST3

Value	F10B1	F11B1
RST0	1	1
RST1	-	1
RST2	1	-
RST3	-	-

Configuration Setting ALU54_3.REG_OPCODEOP0_1_RST

Default value: RST3

Value	F22B1	F23B1
RST0	1	1
RST1	-	1
RST2	1	-
RST3	-	-

Configuration Setting ALU54_3.REG_OUTPUT0_CLK

Default value: CLK3

Value	F5B1	F6B1
NONE	-	-
CLK0	1	1
CLK1	1	-
CLK2	-	1
CLK3	-	-

Configuration Setting ALU54_3.REG_OUTPUT1_CLK

Default value: CLK3

Value	F3B1	F4B1
NONE	-	-
CLK0	1	1
CLK1	1	-
CLK2	-	1
CLK3	-	-

Configuration Setting ALU54_3.RESETMODE

Default value: SYNC

Value	F2B1	F12B1
ASYNC	1	1
SYNC	-	-

Configuration Setting DSP_LEFT.CIBOUT

Default value: OFF

Value	F90B1	F91B1	F92B1	F93B1
OFF	-	-	-	-
ON	1	1	1	1

Configuration Setting MULT18_0.MODE

Default value: NONE

Value	F30B0	F34B1
NONE	-	-
MULT18X18D	1	1

Configuration Setting MULT18_1.CIBOUT_BYP

Value	F3B1	F4B1	F5B1	F6B1	F77B1	F78B1
OFF	1	1	1	1	-	-
ON	-	-	-	-	1	1

Configuration Setting MULT18_1.MODE

Default value: NONE

Value	F28B1	F30B0
NONE	-	-
MULT18X18D	1	1

Configuration Setting MULT18_1.REG_INPUTA_CLK

Default value: CLK3

Value	F20B1	F21B1	F24B1	F25B1	F36B1	F37B1	F48B1	F49B1
NONE	-	-	-	-	-	-	-	-
CLK0	1	1	1	1	1	1	1	1
CLK1	1	-	1	-	1	-	1	-
CLK2	-	1	-	1	-	1	-	1
CLK3	-	-	-	-	-	-	-	-

Configuration Setting MULT18_1.REG_INPUTB_CLK

Default value: CLK3

Value	F32B1	F33B1	F42B1	F43B1
NONE	-	-	-	-
CLK0	1	1	1	1
CLK1	1	-	1	-
CLK2	-	1	-	1
CLK3	-	-	-	-

Configuration Setting MULT18_1.REG_INPUTC_CLK

Default value: CLK3

Value	F30B1	F31B1
NONE	-	-
CLK0	1	1
CLK1	1	-
CLK2	-	1
CLK3	-	-

Configuration Setting MULT18_1.REG_OUTPUT_CLK

Default value: CLK3

Value	F3B1	F4B1	F5B1	F6B1
NONE	-	-	-	-
CLK0	1	1	1	1
CLK1	1	-	1	-
CLK2	-	1	-	1
CLK3	-	-	-	-

Configuration Setting MULT18_1.REG_PIPELINE_CLK

Default value: CLK3

Value	F13B1	F14B1	F16B1	F17B1
NONE	-	-	-	-
CLK0	1	1	1	1
CLK1	1	-	1	-
CLK2	-	1	-	1
CLK3	-	-	-	-

Configuration Setting MULT18_1.RESETMODE

Default value: SYNC

Value	F2B1	F12B1
ASYNC	1	1
SYNC	-	-