DSP_CMUX_UL Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
D
D
D
D
 
D
D
D
D
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Configuration Setting DCS0.DCSMODE

Default value: NEG

Value F70B0 F71B0 F72B0 F73B0 F75B0 F76B0 F77B0 F78B0
NONE - - - - - - - -
CLK0 1 - 1 - 1 - 1 -
CLK0_HIGH - - 1 1 - - 1 1
CLK0_LOW - - 1 - - - 1 -
HIGH 1 1 1 1 1 1 1 1
LOW 1 1 1 - 1 1 1 -
NEG - - - - - - - -
POS - - - 1 - - - 1
CLK1 1 - 1 1 1 - 1 1
CLK1_HIGH - 1 - 1 - 1 - 1
CLK1_LOW - 1 - - - 1 - -

Fixed Connections

SourceSink
G_DCS0CLK0 G_CLK0_DCS0
G_DCS1CLK0 G_CLK0_DCS1
G_DCS0CLK1 G_CLK1_DCS0
G_DCS1CLK1 G_CLK1_DCS1
G_DCSOUT_DCS0 G_DCS0
G_DCSOUT_DCS1 G_DCS1
25K_S24_JA0 G_JCE_DCCBL
25K_S24E1_JA0 G_JCE_DCCBR
25K_JA0 G_JCE_DCCTL
25K_E1_JA0 G_JCE_DCCTR
25K_S24_JD7 G_JCLKI_DCCBL
25K_S24E1_JD7 G_JCLKI_DCCBR
25K_JD7 G_JCLKI_DCCTL
25K_E1_JD7 G_JCLKI_DCCTR
25K_JC0 G_JMODESEL_DCS0
25K_S24_JC0 G_JMODESEL_DCS1
25K_JA3 G_JSEL0_DCS0
25K_S24_JA3 G_JSEL0_DCS1
25K_JA4 G_JSEL1_DCS0
25K_S24_JA4 G_JSEL1_DCS1
G_CLKO_DCCBL G_LLCPCLKCIB0
G_CLKO_DCCBR G_LRCPCLKCIB0
G_CLKO_DCCTL G_ULCPCLKCIB0
G_CLKO_DCCTR G_URCPCLKCIB0