DDRDLL_UR Bit Data

 
 
 
 
 
 
 
 
D
D
 
 
G
D
M
D
M
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Mux driving N10E2_JDDRDLLCLK

Source F8B0 F9B0
N10E2_JCIBCLK0 1 -
BNK_ECLK0 - 1
BNK_ECLK1 1 1

Configuration Setting DDRDLL.FORCE_MAX_DELAY

Value F13B0 F15B0
NO 1 -
YES - 1

Configuration Setting DDRDLL.GSR

Default value: ENABLED

Value F12B0
DISABLED 1
ENABLED -

Configuration Setting DDRDLL.MODE

Default value: NONE

Value F14B0 F16B0
NONE - -
DDRDLLA 1 1

Fixed Connections

SourceSink
N10E2_DDRDEL_DDRDLL G_URDDRDEL
JCLK0 N10E2_JCIBCLK0
N10E2_JDDRDLLCLK N10E2_JCLK_DDRDLL
N10E2_JDCNTL0_DDRDLL JF0
N10E2_JDCNTL1_DDRDLL JF1
N10E2_JDCNTL2_DDRDLL JF2
N10E2_JDCNTL3_DDRDLL JF3
N10E2_JDCNTL4_DDRDLL JF4
N10E2_JDCNTL5_DDRDLL JF5
N10E2_JDCNTL6_DDRDLL JF6
N10E2_JDCNTL7_DDRDLL JF7
JA0 N10E2_JFREEZE_DDRDLL
N10E2_JLOCK_DDRDLL JQ0
N10E2_JDIVOSC_DDRDLL JQ1
JLSR0 N10E2_JRST_DDRDLL
JB0 N10E2_JUDDCNTLN_DDRDLL