DDRDLL_LL Bit Data

 
 
 
 
 
 
 
 
D
D
 
 
G
D
M
D
M
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Mux driving S13W2_JDDRDLLCLK

Source F8B0 F9B0
S13W2_JCIBCLK0 1 -
BNK_ECLK0 - 1
BNK_ECLK1 1 1

Configuration Setting DDRDLL.FORCE_MAX_DELAY

Value F13B0 F15B0
NO 1 -
YES - 1

Configuration Setting DDRDLL.GSR

Default value: ENABLED

Value F12B0
DISABLED 1
ENABLED -

Configuration Setting DDRDLL.MODE

Default value: NONE

Value F14B0 F16B0
NONE - -
DDRDLLA 1 1

Fixed Connections

SourceSink
S13W2_DDRDEL_DDRDLL G_LLDDRDEL
JCLK0 S13W2_JCIBCLK0
S13W2_JDDRDLLCLK S13W2_JCLK_DDRDLL
S13W2_JDCNTL0_DDRDLL JF0
S13W2_JDCNTL1_DDRDLL JF1
S13W2_JDCNTL2_DDRDLL JF2
S13W2_JDCNTL3_DDRDLL JF3
S13W2_JDCNTL4_DDRDLL JF4
S13W2_JDCNTL5_DDRDLL JF5
S13W2_JDCNTL6_DDRDLL JF6
S13W2_JDCNTL7_DDRDLL JF7
JA0 S13W2_JFREEZE_DDRDLL
S13W2_JLOCK_DDRDLL JQ0
S13W2_JDIVOSC_DDRDLL JQ1
JLSR0 S13W2_JRST_DDRDLL
JB0 S13W2_JUDDCNTLN_DDRDLL