DCU5 Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
S
S
C
C
R
R
S
S
R
E
C
C
R
R
R
R
R
 
C
C
S
T
T
T
 
 
 
 
E
S
S
S
S
S
S
 
D
D
D
S
 
 
M
M
L
L
L
C
 
 
C
E
E
S
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
C
E
D
E
D
 
 
 
 
 
 
 
 
 
 
 
D
D
D
D
D
D
D
D

Mux driving W5_CH1_RX_REFCLK

Source F12B1
W5_JCH1RXREFCLKCIB 1

Configuration word DCU.CH1_DCOATDCFG

Default value: 2'b00

DCU.CH1_DCOATDCFG[0]F103B1
DCU.CH1_DCOATDCFG[1]F104B1

Configuration word DCU.CH1_DCOATDDLY

Default value: 2'b00

DCU.CH1_DCOATDDLY[0]F101B1
DCU.CH1_DCOATDDLY[1]F102B1

Configuration bit DCU.CH1_DCOBYPSATD

Default value: 1'b0

DCU.CH1_DCOBYPSATD[0]F105B1

Configuration word DCU.CH1_DCOCTLGI

Default value: 3'b000

DCU.CH1_DCOCTLGI[0]F98B1
DCU.CH1_DCOCTLGI[1]F99B1
DCU.CH1_DCOCTLGI[2]F100B1

Configuration bit DCU.CH1_FF_RX_F_CLK_DIS

Default value: 1'b0

DCU.CH1_FF_RX_F_CLK_DIS[0]F84B1

Configuration bit DCU.CH1_FF_RX_H_CLK_EN

Default value: 1'b0

DCU.CH1_FF_RX_H_CLK_EN[0]F83B1

Configuration bit DCU.CH1_FF_TX_F_CLK_DIS

Default value: 1'b0

DCU.CH1_FF_TX_F_CLK_DIS[0]F86B1

Configuration bit DCU.CH1_FF_TX_H_CLK_EN

Default value: 1'b0

DCU.CH1_FF_TX_H_CLK_EN[0]F85B1

Configuration bit DCU.CH1_LDR_RX2CORE_SEL

Default value: 1'b0

DCU.CH1_LDR_RX2CORE_SEL[0]F11B1

Configuration bit DCU.CH1_LEQ_OFFSET_SEL

Default value: 1'b0

DCU.CH1_LEQ_OFFSET_SEL[0]F24B1

Configuration word DCU.CH1_LEQ_OFFSET_TRIM

Default value: 3'b000

DCU.CH1_LEQ_OFFSET_TRIM[0]F25B1
DCU.CH1_LEQ_OFFSET_TRIM[1]F26B1
DCU.CH1_LEQ_OFFSET_TRIM[2]F27B1

Configuration bit DCU.CH1_PDEN_SEL

Default value: 1'b0

DCU.CH1_PDEN_SEL[0]F43B1

Configuration bit DCU.CH1_RATE_MODE_RX

Default value: 1'b0

DCU.CH1_RATE_MODE_RX[0]F9B1

Configuration bit DCU.CH1_RCV_DCC_EN

Default value: 1'b0

DCU.CH1_RCV_DCC_EN[0]F13B1

Configuration bit DCU.CH1_REQ_EN

Default value: 1'b0

DCU.CH1_REQ_EN[0]F32B1

Configuration word DCU.CH1_REQ_LVL_SET

Default value: 2'b00

DCU.CH1_REQ_LVL_SET[0]F37B1
DCU.CH1_REQ_LVL_SET[1]F38B1

Configuration bit DCU.CH1_RLOS_SEL

Default value: 1'b0

DCU.CH1_RLOS_SEL[0]F57B1

Configuration bit DCU.CH1_RPWDNB

Default value: 1'b0

DCU.CH1_RPWDNB[0]F8B1

Configuration word DCU.CH1_RTERM_RX

Default value: 5'b00000

DCU.CH1_RTERM_RX[0]F16B1
DCU.CH1_RTERM_RX[1]F17B1
DCU.CH1_RTERM_RX[2]F18B1
DCU.CH1_RTERM_RX[3]F19B1
DCU.CH1_RTERM_RX[4]F20B1

Configuration word DCU.CH1_RXIN_CM

Default value: 2'b00

DCU.CH1_RXIN_CM[0]F22B1
DCU.CH1_RXIN_CM[1]F23B1

Configuration word DCU.CH1_RXTERM_CM

Default value: 2'b00

DCU.CH1_RXTERM_CM[0]F14B1
DCU.CH1_RXTERM_CM[1]F15B1

Configuration word DCU.CH1_RX_DCO_CK_DIV

Default value: 3'b000

DCU.CH1_RX_DCO_CK_DIV[0]F40B1
DCU.CH1_RX_DCO_CK_DIV[1]F41B1
DCU.CH1_RX_DCO_CK_DIV[2]F42B1

Configuration bit DCU.CH1_RX_DIV11_SEL

Default value: 1'b0

DCU.CH1_RX_DIV11_SEL[0]F10B1

Configuration word DCU.CH1_RX_LOS_CEQ

Default value: 2'b00

DCU.CH1_RX_LOS_CEQ[0]F51B1
DCU.CH1_RX_LOS_CEQ[1]F54B1

Configuration bit DCU.CH1_RX_LOS_EN

Default value: 1'b0

DCU.CH1_RX_LOS_EN[0]F56B1

Configuration bit DCU.CH1_RX_LOS_HYST_EN

Default value: 1'b0

DCU.CH1_RX_LOS_HYST_EN[0]F55B1

Configuration word DCU.CH1_RX_LOS_LVL

Default value: 3'b000

DCU.CH1_RX_LOS_LVL[0]F48B1
DCU.CH1_RX_LOS_LVL[1]F49B1
DCU.CH1_RX_LOS_LVL[2]F50B1

Configuration word DCU.CH1_RX_RATE_SEL

Default value: 4'b0000

DCU.CH1_RX_RATE_SEL[0]F33B1
DCU.CH1_RX_RATE_SEL[1]F34B1
DCU.CH1_RX_RATE_SEL[2]F35B1
DCU.CH1_RX_RATE_SEL[3]F36B1

Configuration bit DCU.CH1_SEL_SD_RX_CLK

Default value: 1'b0

DCU.CH1_SEL_SD_RX_CLK[0]F82B1

Configuration word DCU.CH1_TDRV_DAT_SEL

Default value: 2'b00

DCU.CH1_TDRV_DAT_SEL[0]F4B1
DCU.CH1_TDRV_DAT_SEL[1]F5B1

Configuration word DCU.CH1_TDRV_SLICE5_CUR

Default value: 2'b00

DCU.CH1_TDRV_SLICE5_CUR[0]F6B1
DCU.CH1_TDRV_SLICE5_CUR[1]F7B1

Configuration Setting DCU.MODE

Default value: NONE

Value F46B1 F47B1
NONE - -
DCUA 1 1