DCU4 Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
1
1
2
2
3
3
4
4
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
 
 
M
M
 
 
B
B
A
A
 
 
 
 
 
 
 
 
T
T
S
S
E
E
S
S
T
T
T
T
T
S
S
 
S
S
S
S
S
S
S
S
S
S
S
S
C
C
C
C
C
C
C
C
C
C
C
C

Configuration word DCU.CH1_CC_MATCH_1

Default value: 10'b00XXXXXXXX

DCU.CH1_CC_MATCH_1[0]
DCU.CH1_CC_MATCH_1[1]
DCU.CH1_CC_MATCH_1[2]
DCU.CH1_CC_MATCH_1[3]
DCU.CH1_CC_MATCH_1[4]
DCU.CH1_CC_MATCH_1[5]
DCU.CH1_CC_MATCH_1[6]
DCU.CH1_CC_MATCH_1[7]
DCU.CH1_CC_MATCH_1[8]F16B1
DCU.CH1_CC_MATCH_1[9]F17B1

Configuration word DCU.CH1_CC_MATCH_2

Default value: 10'b00XXXXXXXX

DCU.CH1_CC_MATCH_2[0]
DCU.CH1_CC_MATCH_2[1]
DCU.CH1_CC_MATCH_2[2]
DCU.CH1_CC_MATCH_2[3]
DCU.CH1_CC_MATCH_2[4]
DCU.CH1_CC_MATCH_2[5]
DCU.CH1_CC_MATCH_2[6]
DCU.CH1_CC_MATCH_2[7]
DCU.CH1_CC_MATCH_2[8]F18B1
DCU.CH1_CC_MATCH_2[9]F19B1

Configuration word DCU.CH1_CC_MATCH_3

Default value: 10'b0000000000

DCU.CH1_CC_MATCH_3[0]F0B1
DCU.CH1_CC_MATCH_3[1]F1B1
DCU.CH1_CC_MATCH_3[2]F2B1
DCU.CH1_CC_MATCH_3[3]F3B1
DCU.CH1_CC_MATCH_3[4]F4B1
DCU.CH1_CC_MATCH_3[5]F5B1
DCU.CH1_CC_MATCH_3[6]F6B1
DCU.CH1_CC_MATCH_3[7]F7B1
DCU.CH1_CC_MATCH_3[8]F20B1
DCU.CH1_CC_MATCH_3[9]F21B1

Configuration word DCU.CH1_CC_MATCH_4

Default value: 10'b0000000000

DCU.CH1_CC_MATCH_4[0]F8B1
DCU.CH1_CC_MATCH_4[1]F9B1
DCU.CH1_CC_MATCH_4[2]F10B1
DCU.CH1_CC_MATCH_4[3]F11B1
DCU.CH1_CC_MATCH_4[4]F12B1
DCU.CH1_CC_MATCH_4[5]F13B1
DCU.CH1_CC_MATCH_4[6]F14B1
DCU.CH1_CC_MATCH_4[7]F15B1
DCU.CH1_CC_MATCH_4[8]F22B1
DCU.CH1_CC_MATCH_4[9]F23B1

Configuration bit DCU.CH1_LDR_CORE2TX_SEL

Default value: 1'b0

DCU.CH1_LDR_CORE2TX_SEL[0]F69B1

Configuration bit DCU.CH1_RATE_MODE_TX

Default value: 1'b0

DCU.CH1_RATE_MODE_TX[0]F67B1

Configuration word DCU.CH1_RTERM_TX

Default value: 5'b00000

DCU.CH1_RTERM_TX[0]F74B1
DCU.CH1_RTERM_TX[1]F75B1
DCU.CH1_RTERM_TX[2]F76B1
DCU.CH1_RTERM_TX[3]F77B1
DCU.CH1_RTERM_TX[4]F78B1

Configuration bit DCU.CH1_TDRV_POST_EN

Default value: 1'b0

DCU.CH1_TDRV_POST_EN[0]F71B1

Configuration bit DCU.CH1_TDRV_PRE_EN

Default value: 1'b0

DCU.CH1_TDRV_PRE_EN[0]F70B1

Configuration word DCU.CH1_TDRV_SLICE0_CUR

Default value: 3'b000

DCU.CH1_TDRV_SLICE0_CUR[0]F98B1
DCU.CH1_TDRV_SLICE0_CUR[1]F99B1
DCU.CH1_TDRV_SLICE0_CUR[2]F100B1

Configuration word DCU.CH1_TDRV_SLICE0_SEL

Default value: 2'b00

DCU.CH1_TDRV_SLICE0_SEL[0]F82B1
DCU.CH1_TDRV_SLICE0_SEL[1]F83B1

Configuration word DCU.CH1_TDRV_SLICE1_CUR

Default value: 3'b000

DCU.CH1_TDRV_SLICE1_CUR[0]F101B1
DCU.CH1_TDRV_SLICE1_CUR[1]F102B1
DCU.CH1_TDRV_SLICE1_CUR[2]F103B1

Configuration word DCU.CH1_TDRV_SLICE1_SEL

Default value: 2'b00

DCU.CH1_TDRV_SLICE1_SEL[0]F84B1
DCU.CH1_TDRV_SLICE1_SEL[1]F85B1

Configuration word DCU.CH1_TDRV_SLICE2_CUR

Default value: 2'b00

DCU.CH1_TDRV_SLICE2_CUR[0]F104B1
DCU.CH1_TDRV_SLICE2_CUR[1]F105B1

Configuration word DCU.CH1_TDRV_SLICE2_SEL

Default value: 2'b00

DCU.CH1_TDRV_SLICE2_SEL[0]F86B1
DCU.CH1_TDRV_SLICE2_SEL[1]F87B1

Configuration word DCU.CH1_TDRV_SLICE3_CUR

Default value: 2'b00

DCU.CH1_TDRV_SLICE3_CUR[0]F94B1
DCU.CH1_TDRV_SLICE3_CUR[1]F95B1

Configuration word DCU.CH1_TDRV_SLICE3_SEL

Default value: 2'b00

DCU.CH1_TDRV_SLICE3_SEL[0]F88B1
DCU.CH1_TDRV_SLICE3_SEL[1]F89B1

Configuration word DCU.CH1_TDRV_SLICE4_CUR

Default value: 2'b00

DCU.CH1_TDRV_SLICE4_CUR[0]F96B1
DCU.CH1_TDRV_SLICE4_CUR[1]F97B1

Configuration word DCU.CH1_TDRV_SLICE4_SEL

Default value: 2'b00

DCU.CH1_TDRV_SLICE4_SEL[0]F90B1
DCU.CH1_TDRV_SLICE4_SEL[1]F91B1

Configuration word DCU.CH1_TDRV_SLICE5_SEL

Default value: 2'b00

DCU.CH1_TDRV_SLICE5_SEL[0]F92B1
DCU.CH1_TDRV_SLICE5_SEL[1]F93B1

Configuration bit DCU.CH1_TPWDNB

Default value: 1'b0

DCU.CH1_TPWDNB[0]F66B1

Configuration word DCU.CH1_TX_CM_SEL

Default value: 2'b00

DCU.CH1_TX_CM_SEL[0]F79B1
DCU.CH1_TX_CM_SEL[1]F80B1

Configuration bit DCU.CH1_TX_DIV11_SEL

Default value: 1'b0

DCU.CH1_TX_DIV11_SEL[0]F68B1

Configuration bit DCU.CH1_TX_POST_SIGN

Default value: 1'b0

DCU.CH1_TX_POST_SIGN[0]F73B1

Configuration bit DCU.CH1_TX_PRE_SIGN

Default value: 1'b0

DCU.CH1_TX_PRE_SIGN[0]F72B1

Configuration word DCU.CH1_UDF_COMMA_A

Default value: 10'b0000000000

DCU.CH1_UDF_COMMA_A[0]F32B1
DCU.CH1_UDF_COMMA_A[1]F33B1
DCU.CH1_UDF_COMMA_A[2]F34B1
DCU.CH1_UDF_COMMA_A[3]F35B1
DCU.CH1_UDF_COMMA_A[4]F36B1
DCU.CH1_UDF_COMMA_A[5]F37B1
DCU.CH1_UDF_COMMA_A[6]F38B1
DCU.CH1_UDF_COMMA_A[7]F39B1
DCU.CH1_UDF_COMMA_A[8]F56B1
DCU.CH1_UDF_COMMA_A[9]F57B1

Configuration word DCU.CH1_UDF_COMMA_B

Default value: 10'b0000000000

DCU.CH1_UDF_COMMA_B[0]F40B1
DCU.CH1_UDF_COMMA_B[1]F41B1
DCU.CH1_UDF_COMMA_B[2]F42B1
DCU.CH1_UDF_COMMA_B[3]F43B1
DCU.CH1_UDF_COMMA_B[4]F44B1
DCU.CH1_UDF_COMMA_B[5]F45B1
DCU.CH1_UDF_COMMA_B[6]F46B1
DCU.CH1_UDF_COMMA_B[7]F47B1
DCU.CH1_UDF_COMMA_B[8]F54B1
DCU.CH1_UDF_COMMA_B[9]F55B1

Configuration word DCU.CH1_UDF_COMMA_MASK

Default value: 10'b0000000000

DCU.CH1_UDF_COMMA_MASK[0]F24B1
DCU.CH1_UDF_COMMA_MASK[1]F25B1
DCU.CH1_UDF_COMMA_MASK[2]F26B1
DCU.CH1_UDF_COMMA_MASK[3]F27B1
DCU.CH1_UDF_COMMA_MASK[4]F28B1
DCU.CH1_UDF_COMMA_MASK[5]F29B1
DCU.CH1_UDF_COMMA_MASK[6]F30B1
DCU.CH1_UDF_COMMA_MASK[7]F31B1
DCU.CH1_UDF_COMMA_MASK[8]F50B1
DCU.CH1_UDF_COMMA_MASK[9]F51B1