DCU3 Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
T
T
T
T
T
T
E
E
M
O
O
O
O
 
 
 
S
S
S
S
S
S
 
 
S
S
S
S
S
S
S
S
S
S
E
 
 
 
 
 
M
 
M
M
M
 
 
 
R
T
S
 
 
 
E
L
E
A
 
 
M
M
S
S
E
 
 
B
 
B
 
 
B
 
 
B
B
B
B
B
 
D
 
 
 
 
E
E
C
C
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2

Configuration bit DCU.CH0_AUTO_CALIB_EN

Default value: 1'b0

DCU.CH0_AUTO_CALIB_EN[0]F7B1

Configuration bit DCU.CH0_AUTO_FACQ_EN

Default value: 1'b0

DCU.CH0_AUTO_FACQ_EN[0]F6B1

Configuration word DCU.CH0_BAND_THRESHOLD

Default value: 6'b000000

DCU.CH0_BAND_THRESHOLD[0]F0B1
DCU.CH0_BAND_THRESHOLD[1]F1B1
DCU.CH0_BAND_THRESHOLD[2]F2B1
DCU.CH0_BAND_THRESHOLD[3]F3B1
DCU.CH0_BAND_THRESHOLD[4]F4B1
DCU.CH0_BAND_THRESHOLD[5]F5B1

Configuration bit DCU.CH0_CALIB_CK_MODE

Default value: 1'b0

DCU.CH0_CALIB_CK_MODE[0]F8B1

Configuration word DCU.CH0_REG_BAND_OFFSET

Default value: 4'b0000

DCU.CH0_REG_BAND_OFFSET[0]F9B1
DCU.CH0_REG_BAND_OFFSET[1]F10B1
DCU.CH0_REG_BAND_OFFSET[2]F11B1
DCU.CH0_REG_BAND_OFFSET[3]F12B1

Configuration word DCU.CH0_REG_BAND_SEL

Default value: 6'b000000

DCU.CH0_REG_BAND_SEL[0]F16B1
DCU.CH0_REG_BAND_SEL[1]F17B1
DCU.CH0_REG_BAND_SEL[2]F18B1
DCU.CH0_REG_BAND_SEL[3]F19B1
DCU.CH0_REG_BAND_SEL[4]F20B1
DCU.CH0_REG_BAND_SEL[5]F21B1

Configuration bit DCU.CH0_REG_IDAC_EN

Default value: 1'b0

DCU.CH0_REG_IDAC_EN[0]F34B1

Configuration word DCU.CH0_REG_IDAC_SEL

Default value: 10'b0000000000

DCU.CH0_REG_IDAC_SEL[0]F24B1
DCU.CH0_REG_IDAC_SEL[1]F25B1
DCU.CH0_REG_IDAC_SEL[2]F26B1
DCU.CH0_REG_IDAC_SEL[3]F27B1
DCU.CH0_REG_IDAC_SEL[4]F28B1
DCU.CH0_REG_IDAC_SEL[5]F29B1
DCU.CH0_REG_IDAC_SEL[6]F30B1
DCU.CH0_REG_IDAC_SEL[7]F31B1
DCU.CH0_REG_IDAC_SEL[8]F32B1
DCU.CH0_REG_IDAC_SEL[9]F33B1

Configuration word DCU.CH1_CC_MATCH_1

Default value: 10'bXX00000000

DCU.CH1_CC_MATCH_1[0]F90B1
DCU.CH1_CC_MATCH_1[1]F91B1
DCU.CH1_CC_MATCH_1[2]F92B1
DCU.CH1_CC_MATCH_1[3]F93B1
DCU.CH1_CC_MATCH_1[4]F94B1
DCU.CH1_CC_MATCH_1[5]F95B1
DCU.CH1_CC_MATCH_1[6]F96B1
DCU.CH1_CC_MATCH_1[7]F97B1
DCU.CH1_CC_MATCH_1[8]
DCU.CH1_CC_MATCH_1[9]

Configuration word DCU.CH1_CC_MATCH_2

Default value: 10'bXX00000000

DCU.CH1_CC_MATCH_2[0]F98B1
DCU.CH1_CC_MATCH_2[1]F99B1
DCU.CH1_CC_MATCH_2[2]F100B1
DCU.CH1_CC_MATCH_2[3]F101B1
DCU.CH1_CC_MATCH_2[4]F102B1
DCU.CH1_CC_MATCH_2[5]F103B1
DCU.CH1_CC_MATCH_2[6]F104B1
DCU.CH1_CC_MATCH_2[7]F105B1
DCU.CH1_CC_MATCH_2[8]
DCU.CH1_CC_MATCH_2[9]

Configuration bit DCU.CH1_CTC_BYPASS

Default value: 1'b0

DCU.CH1_CTC_BYPASS[0]F78B1

Configuration bit DCU.CH1_DEC_BYPASS

Default value: 1'b0

DCU.CH1_DEC_BYPASS[0]F77B1

Configuration bit DCU.CH1_ENABLE_CG_ALIGN

Default value: 1'b0

DCU.CH1_ENABLE_CG_ALIGN[0]F57B1

Configuration bit DCU.CH1_ENC_BYPASS

Default value: 1'b0

DCU.CH1_ENC_BYPASS[0]F69B1

Configuration bit DCU.CH1_GE_AN_ENABLE

Default value: 1'b0

DCU.CH1_GE_AN_ENABLE[0]F54B1

Configuration bit DCU.CH1_INVERT_RX

Default value: 1'b0

DCU.CH1_INVERT_RX[0]F48B1

Configuration bit DCU.CH1_INVERT_TX

Default value: 1'b0

DCU.CH1_INVERT_TX[0]F49B1

Configuration bit DCU.CH1_LSM_DISABLE

Default value: 1'b0

DCU.CH1_LSM_DISABLE[0]F81B1

Configuration bit DCU.CH1_MATCH_2_ENABLE

Default value: 1'b0

DCU.CH1_MATCH_2_ENABLE[0]F86B1

Configuration bit DCU.CH1_MATCH_4_ENABLE

Default value: 1'b0

DCU.CH1_MATCH_4_ENABLE[0]F87B1

Configuration word DCU.CH1_MIN_IPG_CNT

Default value: 2'b00

DCU.CH1_MIN_IPG_CNT[0]F88B1
DCU.CH1_MIN_IPG_CNT[1]F89B1

Configuration bit DCU.CH1_PCIE_EI_EN

Default value: 1'b0

DCU.CH1_PCIE_EI_EN[0]F64B1

Configuration bit DCU.CH1_PCIE_MODE

Default value: 1'b0

DCU.CH1_PCIE_MODE[0]F42B1

Configuration word DCU.CH1_PCS_DET_TIME_SEL

Default value: 2'b00

DCU.CH1_PCS_DET_TIME_SEL[0]F62B1
DCU.CH1_PCS_DET_TIME_SEL[1]F63B1

Configuration bit DCU.CH1_PRBS_ENABLE

Default value: 1'b0

DCU.CH1_PRBS_ENABLE[0]F56B1

Configuration bit DCU.CH1_PRBS_LOCK

Default value: 1'b0

DCU.CH1_PRBS_LOCK[0]F55B1

Configuration bit DCU.CH1_PRBS_SELECTION

Default value: 1'b0

DCU.CH1_PRBS_SELECTION[0]F50B1

Configuration bit DCU.CH1_RIO_MODE

Default value: 1'b0

DCU.CH1_RIO_MODE[0]F43B1

Configuration bit DCU.CH1_RX_GEAR_BYPASS

Default value: 1'b0

DCU.CH1_RX_GEAR_BYPASS[0]F79B1

Configuration bit DCU.CH1_RX_GEAR_MODE

Default value: 1'b0

DCU.CH1_RX_GEAR_MODE[0]F61B1

Configuration bit DCU.CH1_RX_SB_BYPASS

Default value: 1'b0

DCU.CH1_RX_SB_BYPASS[0]F75B1

Configuration bit DCU.CH1_SB_BYPASS

Default value: 1'b0

DCU.CH1_SB_BYPASS[0]F72B1

Configuration bit DCU.CH1_TX_GEAR_BYPASS

Default value: 1'b0

DCU.CH1_TX_GEAR_BYPASS[0]F67B1

Configuration bit DCU.CH1_TX_GEAR_MODE

Default value: 1'b0

DCU.CH1_TX_GEAR_MODE[0]F60B1

Configuration bit DCU.CH1_UC_MODE

Default value: 1'b0

DCU.CH1_UC_MODE[0]F40B1

Configuration bit DCU.CH1_WA_BYPASS

Default value: 1'b0

DCU.CH1_WA_BYPASS[0]F76B1

Configuration bit DCU.CH1_WA_MODE

Default value: 1'b0

DCU.CH1_WA_MODE[0]F44B1