DCU1 Bit Data

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
B
B
B
B
B
B
B
B
 
 
M
M
B
B
A
A
 
 
 
 
 
 
 
 
T
T
S
S
E
E
S
S
T
T
T
T
T
S
S
 
S
S
S
S
S
S
S
S
S
S
S
S
 
 
C
C
C
C
C
C
C
C
C
C
C
C
 
 
 
 
S
S
C
C
R
R
S
S
R
E
C
C
R
R
R
R
R
 
C
C
S
T
T
T
 
 
 
 
E
S
S
S
S
S
S
 

Mux driving W1_CH0_RX_REFCLK

Source F78B1
W1_JCH0RXREFCLKCIB 1

Configuration bit DCU.CH0_LDR_CORE2TX_SEL

Default value: 1'b0

DCU.CH0_LDR_CORE2TX_SEL[0]F27B1

Configuration bit DCU.CH0_LDR_RX2CORE_SEL

Default value: 1'b0

DCU.CH0_LDR_RX2CORE_SEL[0]F77B1

Configuration bit DCU.CH0_LEQ_OFFSET_SEL

Default value: 1'b0

DCU.CH0_LEQ_OFFSET_SEL[0]F90B1

Configuration word DCU.CH0_LEQ_OFFSET_TRIM

Default value: 3'b000

DCU.CH0_LEQ_OFFSET_TRIM[0]F91B1
DCU.CH0_LEQ_OFFSET_TRIM[1]F92B1
DCU.CH0_LEQ_OFFSET_TRIM[2]F93B1

Configuration bit DCU.CH0_RATE_MODE_RX

Default value: 1'b0

DCU.CH0_RATE_MODE_RX[0]F75B1

Configuration bit DCU.CH0_RATE_MODE_TX

Default value: 1'b0

DCU.CH0_RATE_MODE_TX[0]F25B1

Configuration bit DCU.CH0_RCV_DCC_EN

Default value: 1'b0

DCU.CH0_RCV_DCC_EN[0]F79B1

Configuration bit DCU.CH0_REQ_EN

Default value: 1'b0

DCU.CH0_REQ_EN[0]F98B1

Configuration word DCU.CH0_REQ_LVL_SET

Default value: 2'b00

DCU.CH0_REQ_LVL_SET[0]F103B1
DCU.CH0_REQ_LVL_SET[1]F104B1

Configuration bit DCU.CH0_RPWDNB

Default value: 1'b0

DCU.CH0_RPWDNB[0]F74B1

Configuration word DCU.CH0_RTERM_RX

Default value: 5'b00000

DCU.CH0_RTERM_RX[0]F82B1
DCU.CH0_RTERM_RX[1]F83B1
DCU.CH0_RTERM_RX[2]F84B1
DCU.CH0_RTERM_RX[3]F85B1
DCU.CH0_RTERM_RX[4]F86B1

Configuration word DCU.CH0_RTERM_TX

Default value: 5'b00000

DCU.CH0_RTERM_TX[0]F32B1
DCU.CH0_RTERM_TX[1]F33B1
DCU.CH0_RTERM_TX[2]F34B1
DCU.CH0_RTERM_TX[3]F35B1
DCU.CH0_RTERM_TX[4]F36B1

Configuration word DCU.CH0_RXIN_CM

Default value: 2'b00

DCU.CH0_RXIN_CM[0]F88B1
DCU.CH0_RXIN_CM[1]F89B1

Configuration word DCU.CH0_RXTERM_CM

Default value: 2'b00

DCU.CH0_RXTERM_CM[0]F80B1
DCU.CH0_RXTERM_CM[1]F81B1

Configuration bit DCU.CH0_RX_DIV11_SEL

Default value: 1'b0

DCU.CH0_RX_DIV11_SEL[0]F76B1

Configuration word DCU.CH0_RX_RATE_SEL

Default value: 4'b0000

DCU.CH0_RX_RATE_SEL[0]F99B1
DCU.CH0_RX_RATE_SEL[1]F100B1
DCU.CH0_RX_RATE_SEL[2]F101B1
DCU.CH0_RX_RATE_SEL[3]F102B1

Configuration word DCU.CH0_TDRV_DAT_SEL

Default value: 2'b00

DCU.CH0_TDRV_DAT_SEL[0]F70B1
DCU.CH0_TDRV_DAT_SEL[1]F71B1

Configuration bit DCU.CH0_TDRV_POST_EN

Default value: 1'b0

DCU.CH0_TDRV_POST_EN[0]F29B1

Configuration bit DCU.CH0_TDRV_PRE_EN

Default value: 1'b0

DCU.CH0_TDRV_PRE_EN[0]F28B1

Configuration word DCU.CH0_TDRV_SLICE0_CUR

Default value: 3'b000

DCU.CH0_TDRV_SLICE0_CUR[0]F58B1
DCU.CH0_TDRV_SLICE0_CUR[1]F59B1
DCU.CH0_TDRV_SLICE0_CUR[2]F60B1

Configuration word DCU.CH0_TDRV_SLICE0_SEL

Default value: 2'b00

DCU.CH0_TDRV_SLICE0_SEL[0]F40B1
DCU.CH0_TDRV_SLICE0_SEL[1]F41B1

Configuration word DCU.CH0_TDRV_SLICE1_CUR

Default value: 3'b000

DCU.CH0_TDRV_SLICE1_CUR[0]F61B1
DCU.CH0_TDRV_SLICE1_CUR[1]F62B1
DCU.CH0_TDRV_SLICE1_CUR[2]F63B1

Configuration word DCU.CH0_TDRV_SLICE1_SEL

Default value: 2'b00

DCU.CH0_TDRV_SLICE1_SEL[0]F42B1
DCU.CH0_TDRV_SLICE1_SEL[1]F43B1

Configuration word DCU.CH0_TDRV_SLICE2_CUR

Default value: 2'b00

DCU.CH0_TDRV_SLICE2_CUR[0]F64B1
DCU.CH0_TDRV_SLICE2_CUR[1]F65B1

Configuration word DCU.CH0_TDRV_SLICE2_SEL

Default value: 2'b00

DCU.CH0_TDRV_SLICE2_SEL[0]F44B1
DCU.CH0_TDRV_SLICE2_SEL[1]F45B1

Configuration word DCU.CH0_TDRV_SLICE3_CUR

Default value: 2'b00

DCU.CH0_TDRV_SLICE3_CUR[0]F54B1
DCU.CH0_TDRV_SLICE3_CUR[1]F55B1

Configuration word DCU.CH0_TDRV_SLICE3_SEL

Default value: 2'b00

DCU.CH0_TDRV_SLICE3_SEL[0]F46B1
DCU.CH0_TDRV_SLICE3_SEL[1]F47B1

Configuration word DCU.CH0_TDRV_SLICE4_CUR

Default value: 2'b00

DCU.CH0_TDRV_SLICE4_CUR[0]F56B1
DCU.CH0_TDRV_SLICE4_CUR[1]F57B1

Configuration word DCU.CH0_TDRV_SLICE4_SEL

Default value: 2'b00

DCU.CH0_TDRV_SLICE4_SEL[0]F48B1
DCU.CH0_TDRV_SLICE4_SEL[1]F49B1

Configuration word DCU.CH0_TDRV_SLICE5_CUR

Default value: 2'b00

DCU.CH0_TDRV_SLICE5_CUR[0]F72B1
DCU.CH0_TDRV_SLICE5_CUR[1]F73B1

Configuration word DCU.CH0_TDRV_SLICE5_SEL

Default value: 2'b00

DCU.CH0_TDRV_SLICE5_SEL[0]F50B1
DCU.CH0_TDRV_SLICE5_SEL[1]F51B1

Configuration bit DCU.CH0_TPWDNB

Default value: 1'b0

DCU.CH0_TPWDNB[0]F24B1

Configuration word DCU.CH0_TX_CM_SEL

Default value: 2'b00

DCU.CH0_TX_CM_SEL[0]F37B1
DCU.CH0_TX_CM_SEL[1]F38B1

Configuration bit DCU.CH0_TX_DIV11_SEL

Default value: 1'b0

DCU.CH0_TX_DIV11_SEL[0]F26B1

Configuration bit DCU.CH0_TX_POST_SIGN

Default value: 1'b0

DCU.CH0_TX_POST_SIGN[0]F31B1

Configuration bit DCU.CH0_TX_PRE_SIGN

Default value: 1'b0

DCU.CH0_TX_PRE_SIGN[0]F30B1

Configuration word DCU.CH0_UDF_COMMA_A

Default value: 10'b00XXXXXXXX

DCU.CH0_UDF_COMMA_A[0]
DCU.CH0_UDF_COMMA_A[1]
DCU.CH0_UDF_COMMA_A[2]
DCU.CH0_UDF_COMMA_A[3]
DCU.CH0_UDF_COMMA_A[4]
DCU.CH0_UDF_COMMA_A[5]
DCU.CH0_UDF_COMMA_A[6]
DCU.CH0_UDF_COMMA_A[7]
DCU.CH0_UDF_COMMA_A[8]F14B1
DCU.CH0_UDF_COMMA_A[9]F15B1

Configuration word DCU.CH0_UDF_COMMA_B

Default value: 10'b0000000000

DCU.CH0_UDF_COMMA_B[0]F0B1
DCU.CH0_UDF_COMMA_B[1]F1B1
DCU.CH0_UDF_COMMA_B[2]F2B1
DCU.CH0_UDF_COMMA_B[3]F3B1
DCU.CH0_UDF_COMMA_B[4]F4B1
DCU.CH0_UDF_COMMA_B[5]F5B1
DCU.CH0_UDF_COMMA_B[6]F6B1
DCU.CH0_UDF_COMMA_B[7]F7B1
DCU.CH0_UDF_COMMA_B[8]F12B1
DCU.CH0_UDF_COMMA_B[9]F13B1

Configuration word DCU.CH0_UDF_COMMA_MASK

Default value: 10'b00XXXXXXXX

DCU.CH0_UDF_COMMA_MASK[0]
DCU.CH0_UDF_COMMA_MASK[1]
DCU.CH0_UDF_COMMA_MASK[2]
DCU.CH0_UDF_COMMA_MASK[3]
DCU.CH0_UDF_COMMA_MASK[4]
DCU.CH0_UDF_COMMA_MASK[5]
DCU.CH0_UDF_COMMA_MASK[6]
DCU.CH0_UDF_COMMA_MASK[7]
DCU.CH0_UDF_COMMA_MASK[8]F10B1
DCU.CH0_UDF_COMMA_MASK[9]F11B1