BMID_0H Bit Data

 
 
 
 
 
 
 
 
 
M
M
M
M
M
M
M
M
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
 
 
 
 
 
 
 
 
 
 
 
P
P
P
P
 
 
 
 
P
G
P
P
P
P
 
 
 
 
P
G
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Mux driving G_BDCC0CLKI

Source F17B0 F18B0 F19B0 F20B0
G_JLLMPCLKCIB1 1 1 1 0
G_JBLQPCLKCIB0 0 0 0 1
G_JSEDCLKOUT 0 1 0 1
G_JPCSBRXCLK1 1 1 0 1
G_JPCSATXCLK0 0 0 1 1
N1_PCSCDIVX1 0 1 1 1
N1_PCSCDIV10 1 1 1 1

Mux driving G_BDCC1CLKI

Source F21B0 F22B0 F23B0 F24B0
G_JLLMPCLKCIB3 1 1 1 0
G_JBLQPCLKCIB1 0 0 0 1
N1_JJTCK 0 1 0 1
G_JPCSBRXCLK0 1 1 0 1
G_JPCSATXCLK1 0 0 1 1
N1_PCSCDIV11 0 1 1 1
N1_PCSCDIVX0 1 1 1 1

Mux driving G_BDCC2CLKI

Source F25B0 F26B0 F27B0 F28B0
G_JLRMPCLKCIB1 1 1 1 0
G_JBRQPCLKCIB0 0 0 0 1
G_JPCSBTXCLK0 1 1 0 1
G_JPCSARXCLK1 0 0 1 1
N1_JSERDESREFCLK1 1 0 1 1
N1_PCSCDIV11 0 1 1 1
N1_PCSCDIVX0 1 1 1 1

Mux driving G_BDCC3CLKI

Source F29B0 F30B0 F31B0 F32B0
G_JLRMPCLKCIB3 1 1 1 0
G_JBRQPCLKCIB1 0 0 0 1
G_JPCSBTXCLK1 1 1 0 1
G_JPCSARXCLK0 0 0 1 1
N1_JSERDESREFCLK0 1 0 1 1
N1_PCSCDIVX1 0 1 1 1
N1_PCSCDIV10 1 1 1 1

Mux driving G_BDCC4CLKI

Source F33B0 F34B0 F35B0 F36B0
G_JLLMPCLKCIB1 1 1 1 0
G_JBRQPCLKCIB1 0 0 0 1
G_JPCSBTXCLK1 1 1 0 1
G_JPCSARXCLK0 0 0 1 1
N1_JSERDESREFCLK0 0 1 1 1
N1_PCSCDIVX1 1 1 1 1

Mux driving G_BDCC5CLKI

Source F37B0 F38B0 F39B0 F40B0
G_JLLMPCLKCIB3 1 1 1 0
G_JBRQPCLKCIB0 0 0 0 1
G_JPCSBTXCLK0 1 1 0 1
G_JPCSARXCLK1 0 0 1 1
N1_JSERDESREFCLK1 0 1 1 1
N1_PCSCDIV11 1 1 1 1

Mux driving G_BDCC6CLKI

Source F41B0 F42B0 F43B0 F44B0
G_JLRMPCLKCIB1 1 1 1 0
G_JBLQPCLKCIB1 0 0 0 1
N1_JJTCK 0 1 0 1
G_JPCSBRXCLK0 1 1 0 1
G_JPCSATXCLK1 0 0 1 1
N1_JSERDESREFCLK1 0 1 1 1
N1_PCSCDIVX0 1 1 1 1

Mux driving G_BDCC7CLKI

Source F45B0 F46B0 F47B0 F48B0
G_JLRMPCLKCIB3 1 1 1 0
G_JBLQPCLKCIB0 0 0 0 1
G_JSEDCLKOUT 0 1 0 1
G_JPCSBRXCLK1 1 1 0 1
G_JPCSATXCLK0 0 0 1 1
N1_JSERDESREFCLK0 0 1 1 1
N1_PCSCDIV10 1 1 1 1

Mux driving N1_PCSCDIVI0

Source F60B0 F61B0 F62B0 F63B0 F68B0
G_JPCSATXCLK0 1 - - - -
G_JPCSATXCLK1 - 1 - - -
G_JPCSARXCLK0 - - 1 - -
G_JPCSARXCLK1 - - - 1 -
N1_JPCSCDIVCIB0 - - - - 1

Mux driving N1_PCSCDIVI1

Source F70B0 F71B0 F72B0 F73B0 F78B0
G_JPCSBTXCLK0 1 - - - -
G_JPCSBTXCLK1 - 1 - - -
G_JPCSBRXCLK0 - - 1 - -
G_JPCSBRXCLK1 - - - 1 -
N1_JPCSCDIVCIB1 - - - - 1

Configuration Setting DCC_B0.MODE

Default value: NONE

Value F9B0
NONE -
DCCA 1

Configuration Setting DCC_B1.MODE

Default value: NONE

Value F10B0
NONE -
DCCA 1

Configuration Setting DCC_B2.MODE

Default value: NONE

Value F11B0
NONE -
DCCA 1

Configuration Setting DCC_B3.MODE

Default value: NONE

Value F12B0
NONE -
DCCA 1

Configuration Setting DCC_B4.MODE

Default value: NONE

Value F13B0
NONE -
DCCA 1

Configuration Setting DCC_B5.MODE

Default value: NONE

Value F14B0
NONE -
DCCA 1

Configuration Setting DCC_B6.MODE

Default value: NONE

Value F15B0
NONE -
DCCA 1

Configuration Setting DCC_B7.MODE

Default value: NONE

Value F16B0
NONE -
DCCA 1

Configuration Setting PCSCLKDIV0.GSR

Default value: ENABLED

Value F69B0
DISABLED 1
ENABLED -

Configuration Setting PCSCLKDIV1.GSR

Default value: ENABLED

Value F79B0
DISABLED 1
ENABLED -

Fixed Connections

SourceSink
N1_PCSCDIVI0→ N1_CLKI_PCSCLKDIV0
N1_PCSCDIVI1→ N1_CLKI_PCSCLKDIV1
G_BDCC0CLKI→ G_CLKI_BDCC0
G_BDCC1CLKI→ G_CLKI_BDCC1
G_BDCC10CLKI→ G_CLKI_BDCC10
G_BDCC11CLKI→ G_CLKI_BDCC11
G_BDCC12CLKI→ G_CLKI_BDCC12
G_BDCC13CLKI→ G_CLKI_BDCC13
G_BDCC14CLKI→ G_CLKI_BDCC14
G_BDCC15CLKI→ G_CLKI_BDCC15
G_BDCC2CLKI→ G_CLKI_BDCC2
G_BDCC3CLKI→ G_CLKI_BDCC3
G_BDCC4CLKI→ G_CLKI_BDCC4
G_BDCC5CLKI→ G_CLKI_BDCC5
G_BDCC6CLKI→ G_CLKI_BDCC6
G_BDCC7CLKI→ G_CLKI_BDCC7
G_BDCC8CLKI→ G_CLKI_BDCC8
G_BDCC9CLKI→ G_CLKI_BDCC9
25K_N1W6_JD7→ G_JBLQPCLKCIB0
45K_N1W6_JD7→ G_JBLQPCLKCIB0
85K_N1W6_JD7→ G_JBLQPCLKCIB0
25K_N1W7_JD7→ G_JBLQPCLKCIB1
45K_N1W7_JD7→ G_JBLQPCLKCIB1
85K_N1W7_JD7→ G_JBLQPCLKCIB1
25K_N1E7_JD7→ G_JBRQPCLKCIB0
45K_N1E7_JD7→ G_JBRQPCLKCIB0
85K_N1E7_JD7→ G_JBRQPCLKCIB0
25K_N1E8_JD7→ G_JBRQPCLKCIB1
45K_N1E8_JD7→ G_JBRQPCLKCIB1
85K_N1E8_JD7→ G_JBRQPCLKCIB1
25K_N1_JB0→ G_JCE_BDCC0
45K_N1_JB0→ G_JCE_BDCC0
85K_N1_JB0→ G_JCE_BDCC0
25K_N1_JB1→ G_JCE_BDCC1
45K_N1_JB1→ G_JCE_BDCC1
85K_N1_JB1→ G_JCE_BDCC1
25K_N1E1_JA2→ G_JCE_BDCC10
45K_N1E1_JA2→ G_JCE_BDCC10
85K_N1E1_JA2→ G_JCE_BDCC10
25K_N1E1_JA3→ G_JCE_BDCC11
45K_N1E1_JA3→ G_JCE_BDCC11
85K_N1E1_JA3→ G_JCE_BDCC11
25K_N1E1_JA4→ G_JCE_BDCC12
45K_N1E1_JA4→ G_JCE_BDCC12
85K_N1E1_JA4→ G_JCE_BDCC12
25K_N1E1_JA5→ G_JCE_BDCC13
45K_N1E1_JA5→ G_JCE_BDCC13
85K_N1E1_JA5→ G_JCE_BDCC13
25K_N1E1_JA6→ G_JCE_BDCC14
45K_N1E1_JA6→ G_JCE_BDCC14
85K_N1E1_JA6→ G_JCE_BDCC14
25K_N1E1_JA7→ G_JCE_BDCC15
45K_N1E1_JA7→ G_JCE_BDCC15
85K_N1E1_JA7→ G_JCE_BDCC15
25K_N1_JB2→ G_JCE_BDCC2
45K_N1_JB2→ G_JCE_BDCC2
85K_N1_JB2→ G_JCE_BDCC2
25K_N1_JB3→ G_JCE_BDCC3
45K_N1_JB3→ G_JCE_BDCC3
85K_N1_JB3→ G_JCE_BDCC3
25K_N1_JB4→ G_JCE_BDCC4
45K_N1_JB4→ G_JCE_BDCC4
85K_N1_JB4→ G_JCE_BDCC4
25K_N1_JB5→ G_JCE_BDCC5
45K_N1_JB5→ G_JCE_BDCC5
85K_N1_JB5→ G_JCE_BDCC5
25K_N1_JB6→ G_JCE_BDCC6
45K_N1_JB6→ G_JCE_BDCC6
85K_N1_JB6→ G_JCE_BDCC6
25K_N1_JB7→ G_JCE_BDCC7
45K_N1_JB7→ G_JCE_BDCC7
85K_N1_JB7→ G_JCE_BDCC7
25K_N1E1_JA0→ G_JCE_BDCC8
45K_N1E1_JA0→ G_JCE_BDCC8
85K_N1E1_JA0→ G_JCE_BDCC8
25K_N1E1_JA1→ G_JCE_BDCC9
45K_N1E1_JA1→ G_JCE_BDCC9
85K_N1E1_JA1→ G_JCE_BDCC9
25K_N13W10_JCLK1→ G_JLLMPCLKCIB1
45K_N13W10_JCLK1→ G_JLLMPCLKCIB1
85K_N13W10_JCLK1→ G_JLLMPCLKCIB1
85K_N25W10_JCLK1→ G_JLLMPCLKCIB3
25K_N13E10_JCLK1→ G_JLRMPCLKCIB1
45K_N13E10_JCLK1→ G_JLRMPCLKCIB1
85K_N13E10_JCLK1→ G_JLRMPCLKCIB1
85K_N25E10_JCLK1→ G_JLRMPCLKCIB3
G_CLKO_BDCC0→ G_VPFN0000
G_CLKO_BDCC1→ G_VPFN0100
G_CLKO_BDCC2→ G_VPFN0200
G_CLKO_BDCC3→ G_VPFN0300
G_CLKO_BDCC4→ G_VPFN0400
G_CLKO_BDCC5→ G_VPFN0500
G_CLKO_BDCC6→ G_VPFN0600
G_CLKO_BDCC7→ G_VPFN0700
G_CLKO_BDCC8→ G_VPFN0800
G_CLKO_BDCC9→ G_VPFN0900
G_CLKO_BDCC10→ G_VPFN1000
G_CLKO_BDCC11→ G_VPFN1100
G_CLKO_BDCC12→ G_VPFN1200
G_CLKO_BDCC13→ G_VPFN1300
G_CLKO_BDCC14→ G_VPFN1400
G_CLKO_BDCC15→ G_VPFN1500
N1_JCLK0→ N1_JPCSCDIVCIB0
N1E1_JCLK1→ N1_JPCSCDIVCIB1
N1_JLSR0→ N1_JRST_PCSCLKDIV0
N1E1_JLSR1→ N1_JRST_PCSCLKDIV1
N1_JA4→ N1_JSEL0_PCSCLKDIV0
N1E1_JB4→ N1_JSEL0_PCSCLKDIV1
N1_JA5→ N1_JSEL1_PCSCLKDIV0
N1E1_JB5→ N1_JSEL1_PCSCLKDIV1
N1_JA6→ N1_JSEL2_PCSCLKDIV0
N1E1_JB6→ N1_JSEL2_PCSCLKDIV1
N1_CDIV1_PCSCLKDIV0→ N1_PCSCDIV10
N1_CDIV1_PCSCLKDIV1→ N1_PCSCDIV11
N1_CDIVX_PCSCLKDIV0→ N1_PCSCDIVX0
N1_CDIVX_PCSCLKDIV1→ N1_PCSCDIVX1